EC1356

(COMMON TO ECE & EEE)

NAME REG NO

: :

YEAR/BRANCH : SEMESTER :

PREPARED BY
1. Mr.T.M.Baskar Asst.Prof/ECE 2. Mr.B.GunaSeelan Asst.Prof/ECE

Syllabus
EC1356 VLSI DESIGN LABORATORY LIST OF EXPERIMENTS 1. Study of simulation using tools. 2. Study of synthesis tools. 3. Place and root and back annotation for FPGAs. 4. Study of development tool for FPGA for schematic entry and Verilog. 5. Design of traffic light controller using Verilog and above tools. 6. Design and simulation of pipelined serial and parallel adder to add/subract 8 number of size, 12-bits each in 2's complement. 7. Design and simulation of back annotated Verilog files for multiplying two signed, 8-bit numbers in 2's complement. Design must be pipelined and completely RTL compliant. 8. Study of FPGA board and testing on board LEDs and switches using Verilog codes. 9. Testing the traffic controller design developed In SI. NO.5 on the FPGA board. 10. Design a realtime clock (2 digits, 7 segments LED displays each for HRS, MTS,and SECS) and demonstrate its working on the FPGA board (an expansion card is required for the displays). LTPC 0032

Total: 45

Ponnaiyah Ramajayam College of Engineering & Techonology VALLAM, THANJAVUR - 613403

CONTENTS
S.No Date Name Of the Experiment Marks obtained Signature Of Staff

1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. Total Marks Out 10

Completed /Not Completed

3

Staff In-charge Signature

EX.NO:1 DATE:

STUDY OF SIMULATION USING TOOLS

1.1 AIM: To verify the functionality and timing of your design or portion of your design. To interprets VHDL or Verilog code into circuit functionality and displays logical results of the described HDL to determine correct circuit operation and to create and verify complex functions in a relatively small amount of time. 1.2 TOOLS REQUIRED: 1.Xilinx-ISE 9.1i 2.Xilinx-XST 3. PC 1.3 PROCEDURE: 1. Start by clicking Xilinx ISE-9.1(i) icon. 2. Go to File new project Enter project name, select the top level source as HDL & click next. 3. Enter device properties as Product category Family Device Package Speed Top level Source type Synthesis Tool Simulator Tool Peripheral language & Click next 4. Right click the device name(XCS3540) in the source window to create new source. 5. Select verilog module and enter file name in the new source window & click next. 6. Assign port name as input, output. If you have more than 1-bit just click bus and set the MSB,LSB value click next and finish. 7. Write the verilog code in the verilog editor window. 8. Run Check syntax through Process window synthesize double click check syntax and remove errors, if present, with proper syntax & coding. 9. Click on the symbol of FPGA device and then right click.click on new source. 10. Select the Test Bench Waveform and give the file name select entity click next and finish. : all : Spartan3 :XC3540 :PQ208 :-4 :HDL :XST (VHDL/Verilog) :Xilinx ISE((VHDL/Verilog) : Verilog

11. Select the desired parameters for simulating the design. In this case combinational circuit and simulation time click finish. 12. Assign all input signal (high or low) using just click on this and save file. 13. From the source process window. Click Behavioral simulation from drop-down menu. 14. Select the test bench file (.tbw)and click process button double click Model 15. Verify your design in wave window by seeing behavior of output signal with respect to input signal. 1.4 VERILOG SAMPLE CODE: the Simulation Behavioral

(i)HALF ADDER: module halfadd(c,s,a,b); input a,b; outputs,c; assign s = a^b; assign c = a&b; endmodule (ii) FULL ADDER: module fulladd (Cin, x, y, s, Cout); input Cin, x, y; output s, Cout; assign s = x ^ y ^ Cin; assign Cout = (x & y) | (Cin & x) | (Cin & y); endmodule

HALF-ADDER LOGIC DIAGRAM

A B

S=A B

C=A. B O O

FULL ADDER LOGIC DIAGRAM

A
B

S= A B C
6

C= A.B AB.C

TRUTH TABLE
HALF ADDER: FULL ADDER

A 0 0 1 1

B 0 1 0 1

S 0 1 1 0

C 0 0 0 1

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

S 0 1 1 0 1 0 0 1

C 0 0 0 1 0 1 1 1

(iii) MULTIPLEXER: module mux (w0, w1, s, f); input w0, w1, s; output f; reg f; always @(w0 or w1 or s) begin f = w0; if (s == 1) f = w1; end endmodule (iv) PRIORITY ENCODER: 6

module priority (W, Y, f); input [3:0] W; output [1:0] Y; output f; reg [1:0] Y; assign f = (W == 0); always @(W) begin casex (W) 'b1xxx: Y = 3; 'b01xx: Y = 2; 'b001x: Y = 1; default: Y = 0; endcase end endmodule 1.5. RESULT: Thus the above verilog codes was entered and test bench waveforms were verified.

EX.NO:2 DATE:

STUDY OF SYNTHESIS TOOLS

2.1 AIM: To create a gate level net list from a register-transfer level model of the circuit described in Verilog design that contains both logical design data and constraints. 2.2 TOOLS REQUIRED: 1.Xilinx-ISE 9.1i 2.Xilinx-XST 3. PC 2.3 PROCEDURE: 1. Start by clicking Xilinx ISE-9.1(i) icon. 2. Go to File new project Enter project name, select the top level source as HDL & click next. 3. Enter device properties as Product category Family Device Package Speed Top level Source type Synthesis Tool Simulator Tool Peripheral language & Click next 4. Right click the device name(XCS3540) in the source window to create new source. 5. Select verilog module and enter file name in the new source window & click next. 6. Assign port name as input, output. If you have more than 1-bit just click bus and set the MSB,LSB value click next and finish. 7. Write the verilog code in the verilog editor window. : all : Spartan3 :XC3540 :PQ208 :-4 :HDL :XST (VHDL/Verilog) :Xilinx ISE((VHDL/Verilog) : Verilog

BASIC LOGIC GATES: AND: A C B A 0 0 1 1 B 0 1 0 1 C 0 0 0 1

OR: A 0 0 1 1 B 0 1 0 1 C 0 1 1 1

A C

B EX-OR: A C B A 0 0 1 1 B 0 1 0 1 C 0 1 1 0

NOT: A 0 1 B 1 0

NAND: A C B NOR: A C

A 0 0 1 1

B 0 1 0 1

C 1 1 1 0

A 0 0 1 1

B 0 1 0 1

C 1 0 0 0

8. Run Check syntax through Process window synthesize double click check syntax and remove errors, if present, with proper syntax & coding. 9. Synthesize the design from the source window select, Synthesize/Implementation from the window .Now double click synthesize XST. 10. After HDL synthesis phase of synthesis process ,we can display a schematic representation of our synthesized source file. This schematic show a representation of the pre optimized design in terms of generic symbols such as address, multipliers,counters,AND and OR gates. Double click View RTL schematic. 11. Double click the schematic to internal view. 12. Double click the schematic outside to move one level block. 13. This schematic shows a representation of the design in terms of logical elements optimized to the target device. For e.g. in terms of LUTs , carry logic, I/O buffer and other technology specific components. double click View technology schematic. 14. Double click schematic to inner view. 15. Double click LUT to inner view. 16. This is the gate level view of LUT ,If u want to see the truth table and K Map for your design just click the respective Tabs. 17. After finishing synthesis we can view number of slices, LUT,I/O are taken by our design in the FPGA device using device summary. 2.4 PROGRAM: (i) MULTIPLEXER: module mux (w0, w1, s, f); input w0, w1, s; output f; reg f; always @(w0 or w1 or s) begin f = w0; if (s == 1) f = w1; end endmodule (ii) HALF ADDER: module halfadd(c,s,a,b); input a,b; outputs,c; assign s = a^b; assign c = a&b; endmodule 10

(iii) FULL ADDER: module fulladd (Cin, x, y, s, Cout); input Cin, x, y; output s, Cout; assign s = x ^ y ^ Cin; assign Cout = (x & y) | (Cin & x) | (Cin & y); endmodule 2.5 RESULT: XILINX SYNTHESIS TOOL enables us to study: 1) Utilization of LUTs & Slices 2) I/O Buffer assignment 3) RTL Schematic in gate level 4) Time delay between I/Os and path

11

EX.NO:3 DATE:

STUDY OF DEVELOPMENT TOOL FOR FPGA FOR SCHEMATIC ENTRY

3.1 AIM: To obtain overview of schematic entry of the design problem through synthesis. 3.2 REQUIREMENTS: 1.Xilinx-ISE 9.1i 2.Xilinx-XST 3. PC 3.3. PROCEDURE: 1. Start the Xilinx ISE by using START PROGRAM FILES Xilinx ISE 9.1i Project Navigator. 2. File New Project. 3. Enter project name and location, then click next. 4. Select the device and other category and click next twice and finish. 5. Click on the symbol of FPGA device and then right click click on new source . 6. Select the schematic and give file name. Click next. 7. Use the symbol window and start the schematic entry using gates and other tools from the box. 8. with the help of wires, connect the gates for the respective operation. 9. Perform simulation or synthesis process through experiment 1& 2.

12

Comparator

FULL ADDER:

DECODER:

13

EX.NO:4 DATE:

PLACE AND ROUTE AND BACK ANNOTATION FOR FPGA

4.1. To create a net list file and fit into FPGA architecture through Place and Route Process. To translate the routed or fitted design to a timing simulation net list to optimize point propagation delay. 4.2 REQUIREMENTS: 1.Xilinx-ISE 9.1i 2.Xilinx-XST 3. PC 4.3. PROCEDURE: 1. Start the xilinx ISE by using Start Program files Xilinx ISE(9.1i) project Navigator. 2. File New Project. 3. Enter the Project name and location, then click next twice and finish. 4. Click on symbol on FPGA device, right click on new source. 5. Select verilog module and give the file name. Click next & define ports, click next and finish. 6. Write the verilog code in verilog editor window. 7. Run check syntax. 8. Synthesize design from Synthesis /Implementation click synthesize XST. 9. After synthesis assign PIN values for pin packages. 10. Enter PIN values for Input and Output signals. TO see the pin assignment on FPGA Zoom in Architecture view or Package view. Save file. 11. Assign FPGAs pin assignment and save file. 12.Save file as XST default click ok and close windows. 13. Double click implementation design. 14. After implementation we can see design summary and get all details about design. Edit the place and route by double click to view/edit placed design 15. New window shows, where I/O pins are placed in FPGA and zoom to view how pins are placed on FPGA.

14

17. Just double click View/Edit Routed Design to view interconnection wires and blocks 18. Click the pin to see where it is placed in FPGA. And Zoom particular area to see Place and Routing. 19. If you want to change the place of the design, click and trace to another slice . 20. Now place and route of the design is changed. 21. Double click Back annotated Pin Location. Once back annotation is completed, constraint file is generated. 22. New design shows minimized run time. 4.4.PROGRAM (i)HALF ADDER: module halfadd(c,s,a,b); input a,b; outputs,c; assign s = a^b; assign c = a&b; endmodule (ii) FULL ADDER: module fulladd (Cin, x, y, s, Cout); input Cin, x, y; output s, Cout; assign s = x ^ y ^ Cin; assign Cout = (x & y) | (Cin & x) | (Cin & y); endmodule

4.5 RESULT: Place & Route, the process of optimization of logic cells for effective utilization of FPGA area and the speed of operation, is used to modify and infer the following: 1) Re-assignment of Pins 2) Re-location of Slices 3) Run time minimization

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EX.NO:5

STUDY OF FPGA BOARD AND TESTING ON BOARD LEDs & SWITCHES

DATE:

5.1 AIM: To study FPGA board and test the on board LEDs and switches using Spartan 3kit. 5.2 TOOLS REQUIRED .Xilinx ISE 9.li project navigator . Personal computer 5.3 PROCEDURE: 1. Start the xilinx ISE by using start program files xilinx (9.li) New project. 2. File New Project 3. Enter the file name and location then click next 4. Select the device and other category and click next twice and finish. 5. Click on the symbol of FPGA device and then click rightclick on new source Select verilog module and give file name, click next and define ports. 6. Write the behavioral Verilog Code in Verilog Editor. Select user constraint file to assign pin values for the design. 7. Check SyntaxRun the Check syntax Process window synthesize double click check syntax to remove errors. 8. Synthesis your design, from the source window select, synthesis/implementation from the window Now double click the Synthesis -XST 9. Design Implementation begins with the mapping or fitting of a logical design file to a specific device and is complete when the physical design is successfully routed and a bit stream is generated. Double Click Implementation Design. 10. Double click the Generate Programming file. 11. Double click Configure device (IMPACT). 12. Select configure device using JTAG in the IMPACT window and then click finish. 13. Open the bit file of our design. 14. Window now shows the FPGA device. Xilinx Right click program click Programming properties will be opened click Ok.

16

14. Then system shows whether program succeeded or failed. 15. If the program succeeded give the input through switches and check the output from LEDs.

5.4 PROGRAM: `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 16:16:44 06/24/2007 // Design Name: // Module Name: keydisplay_verilog // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module keydisplay_verilog(clk_4m,reset,il,ol); input clk_4m,reset; input [15:0]il; output [15:0] ol; //-- test input switches and output leds assign ol = il; endmodule

17

UCF FILE:
net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net "clk_4m" "reset" "IL<0>" "IL<1>" "IL<2>" "IL<3>" "IL<4>" "IL<5>" "IL<6>" "IL<7>" "IL<8>" "IL<9>" "IL<10>" "IL<11>" "IL<12>" "IL<13>" "IL<14>" "IL<15>" "OL<0>" "OL<1>" "OL<2>" "OL<3>" "OL<4>" "OL<5>" "OL<6>" "OL<7>" "OL<8>" "OL<9>" "OL<10>" "OL<11>" "OL<12>" "OL<13>" "OL<14>" "OL<15>" loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = p181; p182; "p57"; "p52"; "p51"; "p50"; "p48"; "p46"; "p45"; "p44"; "p43"; "p42"; "p40"; "p39"; "p37"; "p36"; "p35"; "p34"; "p68"; "p67"; "p65"; "p64"; "p63"; "p62"; "p61"; "p58"; "p80"; "p79"; "p78"; "p77"; "p76"; "p74"; "p72"; "p71";

5.5 RESULT: Thus FPGAs on board and test LEDs & Switches using Spartan 3kit was studied.

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EX.NO:6

DESIGN AND SIMULATION OF SIGNED 8 BIT MULTIPLIER

DATE:

6.1 AIM: To design and simulate 8-bit signed multiplier. 6.2 TOOLS REQUIRED:
Xilinx ISE (9.li) project Navigator.

6.3 PROCEDURE: 1. Start the xilinx ISE by using startprogram files xilinx (9.li) New project. 2. File New Project 3. Enter the file name and location then click next. 4. Select the device and other category and click next twice and finish. 5. Click on the symbol of FPGA device and then click rightclick on new source Select verilog module and give file name, click next and define ports. 7. Write the behavioral verilog code in verilog editor. 8. Run the check syntax process window synthesize double click check syntax and remove errors if present with proper syntax and coding. 9. Click on the symbol of FPGA device and then right click click on new source. 10. Select the desired parameter for simulating your design. In this case combinational circuit and simulation time click finish. 11. Assign all input signal using just click on this and save. 12. From the source process window, click behavioral simulation from drop down menu. 13. Select test bench file. (tbw) and click process button double simulation. Behaviour model. 14. Verify your design in wave by using behaviour of output signal with respect to input signal. 6.4 PROGRAM: module multi_signed(prod,multiplicand,multiplier); output [15:0] prod; input [7:0] multiplicand; input [7:0] multiplier;

19

wire [15:0] shift1,shift2,shift3,shift4,shift5,shift6,shift7,shift8; wire [15:0] add1,add2,add3,add4,add5,add6,add7,add8; wire [15:0] prod_s;

assign shift1 = {8'b0,multiplicand}; assign shift2 = {7'b0,multiplicand,1'b0}; assign shift3 = {6'b0,multiplicand,2'b0}; assign shift4 = {5'b0,multiplicand,3'b0}; assign shift5 = {4'b0,multiplicand,4'b0}; assign shift6 = {3'b0,multiplicand,5'b0}; assign shift7 = {2'b0,multiplicand,6'b0}; assign shift8 = {1'b0,multiplicand,7'b0};

assign add1 = (multiplier[0] == 1'b1) ? shift1 : 16'b0; assign add2 = (multiplier[1] == 1'b1) ? shift2 : 16'b0; assign add3 = (multiplier[2] == 1'b1) ? shift3 : 16'b0; assign add4 = (multiplier[3] == 1'b1) ? shift4 : 16'b0; assign add5 = (multiplier[4] == 1'b1) ? shift5 : 16'b0; assign add6 = (multiplier[5] == 1'b1) ? shift6 : 16'b0; assign add7 = (multiplier[6] == 1'b1) ? shift7 : 16'b0; assign add8 = (multiplier[7] == 1'b1) ? shift8 : 16'b0;

assign prod_s = add1 + add2 + add3 + add4 + add5 + add6 + add7 + add8; assign prod = prod_s;

endmodule

6.5 RESULT: Thus the simulation of two signed 8 bit numbers are multiplied and results are verified.

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EX.NO:7

TESTING OF TRAFFIC LIGHT CONTROLLER

DATE:

7.1 AIM: To implement traffic light controller in FPGA and verify using traffic light interface module.

7.2 TOOLS REQUIRED:

Xilinx ISE (9.li) project Navigator.

7.3 PROCEDURE: 1. Start the xilinx ISE by using start program file xilinx ISE (9.li) project Navigator. 2. File New project 3. Enter project name and location then click next select device and other category and click next twice and finish. 4. Select the device click on FPGA symbol device and right -> click on new source. 5. Select verilog module, give file name click next then define ports & click next and finish. 6. Writing the behavioral verilog code in verilog editor. 7. Run check syntax by clicking on process window double click on check syntax. 8. Synthesize the design by selecting synthesize/implementation from the window. Now double click synthesize XST. 9. Design implementation begins with mapping or filtering of a logical design file a specific device and is complete when physical design is successfully routed. 10. Double click implementation on design programming files configure device(IMPACT). 11. Select configure device using JTAG in the IMPACT window and then click finish. 12. Open the bit file of design. 13. Window now shows the FPGA device. Xilinx Right click program click 14. Programming properties will be opened click Ok. 21

15. Then system shows whether program succeeded or failed. 16. Now the design code is routed to FPGA kit which in turn interfaced with the traffic light module shows the result. 7.4 PROGRAM:
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 20:56:04 05/29/2007 // Design Name: // Module Name: v_traffic // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module traffic_controller_verilog(clk, rst, ls,lw,ln,le, ss,sw,sn,se, rs,rw,rn,re, red_s,red_w,red_n,red_e, ys,yw,yn,ye, ps_r,pw_r,pn_r,pe_r, ps_g,pw_g,pn_g,pe_g, l_n,y_n,redn,png,l_w,y_w,redw,pwg,l_e,y_e,rede,peg,l_s,y_s,reds,psg);

input clk; input rst; output ls,lw,ln,le; output ss,sw,sn,se; output rs,rw,rn,re; output red_s,red_w,red_n,red_e; output ys,yw,yn,ye; output ps_r,pw_r,pn_r,pe_r; output ps_g,pw_g,pn_g,pe_g; output l_n,y_n,redn,png ; output l_w,y_w,redw,pwg ; output l_e,y_e,rede,peg ; output l_s,y_s,reds,psg ; //*********************** Abbreviation used *************************** //South PSG ? Pedestrian south (Green) //-PSR ? Pedestrian south (Red) //-SS ? Straight south //-RS ? Right south //-LS ? Left south-//-YS ? Yellow south

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//-REDS ? Red south //-//--West PWR ? Pedestrian west (red ) //-PWG ? Pedestrian west (Green) //-SW ? South west //-RW ? Right west //-LW ? Left west //-YW ? Yellow west //-REDW ? Red west //-//--North PNR- Pedestrian north red //-PNG ? Pedestrian north green //-SN ? Straight North //-RN ? Right north //-LN ? Left North //-YN - Yellow north //-REDN ? Red north //--East PEG ? Pedestrian East (green) //-PER ? Pedestrian Ease (Red) //-SE ? Straight East //-RE ? Right East //-LE ? Left East //-YE ? Yellow east //-REDE ? Red east //--*********************************************************************** reg l_n,y_n,redn,png ; reg l_w,y_w,redw,pwg ; reg l_e,y_e,rede,peg ; reg l_s,y_s,reds,psg ; reg ls,lw,ln,le; reg ss,sw,sn,se; reg rs,rw,rn,re; reg red_s,red_w,red_n,red_e; reg ys,yw,yn,ye; reg ps_r,pw_r,pn_r,pe_r; reg ps_g,pw_g,pn_g,pe_g;

reg [3:0]ps,ns; reg [30:0] div; reg [3:0] cnt; wire clk_s; parameter [3:0]start = 4'b0000; parameter [3:0]south_g = 4'b0001; parameter [3:0]south_orange = 4'b0010; parameter [3:0]south_r = 4'b0011; parameter [3:0]west_g = 4'b0100; parameter [3:0]west_orange = 4'b0101; parameter [3:0]west_r = 4'b0110; parameter [3:0]east_g = 4'b0111; parameter [3:0]east_orange = 4'b1000;

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parameter [3:0]east_r = 4'b1001; parameter [3:0]north_g = 4'b1010; parameter [3:0]north_orange = 4'b1011; parameter [3:0]north_r = 4'b1100; always@ (posedge clk or posedge rst) begin if (rst) div <= 2'b00; else div <= div + 1; end assign clk_s = div[20]; //*************************** Counter ************************** always@(posedge clk_s or posedge rst) begin if (rst) cnt <= 4'b0; else cnt <= cnt + 1; end //*************************** Memory_logic ********************* always@(posedge clk_s or posedge rst) begin if (rst) ps <= start; else ps <= ns; end always @(ps) case (ps) start : ns <= south_g; south_g: begin if(cnt == 10) ns <= south_orange; else ns <= south_g; end south_orange: begin if(cnt == 14) ns <= south_r; else ns <= south_orange; end south_r : begin if(cnt == 15) ns <= west_g; else ns <= south_r;

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end west_g : begin if(cnt == 10) ns <= west_orange; else ns <= west_g; end west_orange : begin if(cnt == 14) ns <= west_r; else ns <= west_orange; end west_r : begin if(cnt == 15 ) ns <= north_g; else ns <= west_r; end north_g : begin if(cnt == 10) ns <= north_orange; else ns <= north_g; end north_orange : begin if(cnt == 14) ns <= north_r; else ns <= north_orange; end north_r: begin if(cnt == 15) ns <= east_g; else ns <= north_r; end east_g : begin if(cnt == 10) ns <= east_orange; else ns <= east_g; end east_orange : begin if(cnt == 14) ns <= east_r; else ns <= east_orange; end east_r : begin if(cnt == 15) ns <= south_g; else ns <= east_r; end default : ns <= start;

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endcase //*************************** Output_logic ************************** always@(ps) begin red_s <= 0; red_w <= 0; red_n <= 0; red_e <= 0; redn <= 0; redw <= 0; rede <= 0; reds <= 0; rs <= 0; rw <= 0; rn <= 0; re <= 0; ss <= 0; sw <= 0; sn <= 0; se <= 0; ls <= 0; lw <= 0; ln <= 0; le <= 0; l_n <= 0; l_w <= 0; l_e <= 0; l_s <= 0; ps_g <= 0; pw_g <= 0; pn_g <= 0; pe_g <= 0; png <= 0; pwg <= 0; peg <= 0; psg <= 0; ys <= 0; yw <= 0; yn <= 0; ye <= 0; y_n <= 0; y_w <= 0; y_e <= 0; y_s <= 0; ps_r <= 0; pw_r <= 0; pn_r <= 0; pe_r <= 0; case (ps) start : begin red_s <= 1; red_w <= 1; red_n <= 1; red_e <= 1;

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redn <= 1; redw <= 1; rede <= 1; reds <= 1; end south_g : begin ls <= 1; l_s <= 1; rs <= 1; ss <= 1; le <= 1; l_e <= 1; red_w <= 1; red_n <= 1; red_e <= 1; redw <= 1; redn <= 1; rede <= 1; ps_r <= 1; pw_r <= 1; pn_r <= 1; pe_r <= 1; end south_orange : begin pn_g <= 1; png <= 1; le <= 1; ls <= 1; l_s <= 1; ys <= 1; y_s <= 1; red_w <= 1; red_n <= 1; red_e <= 1; redw <= 1; redn <= 1; rede <= 1; ps_r <= 1; pw_r <= 1; pe_r <= 1; end south_r : begin ls <= 1; l_s <= 1; red_w <= 1; red_n <= 1; red_e <= 1; ps_r <= 1; pw_r <= 1; pn_r <= 1; pe_r <= 1; end west_g : begin lw <= 1; ls <= 1; rw <= 1;

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sw <= 1; l_w <= 1; l_s <= 1; red_s <= 1; red_n <= 1; red_e <= 1; redw <= 1; redn <= 1; rede <= 1; ps_r <= 1; pw_r <= 1; pn_r <= 1; pe_r <= 1; end west_orange : begin lw <= 1; ls <= 1; l_w <= 1; l_s <= 1; pe_g <= 1; peg <= 1; yw <= 1; y_w <= 1; red_s <= 1; red_n <= 1; red_e <= 1; reds <= 1; redn <= 1; rede <= 1; ps_r <= 1; pw_r <= 1; pn_r <= 1; end west_r : begin lw <= 1; l_w <= 1; red_s <= 1; red_n <= 1; red_e <= 1; reds <= 1; redn <= 1; rede <= 1; ps_r <= 1; pw_r <= 1; pn_r <= 1; pe_r <= 1; end north_g : begin ln <= 1; l_n <= 1; rn <= 1; sn <= 1; lw <= 1; l_w <= 1; red_s <= 1; red_w <= 1;

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red_e <= 1; reds <= 1; redw <= 1; rede <= 1; ps_r <= 1; pw_r <= 1; pn_r <= 1; pe_r <= 1; end north_orange : begin ln <= 1; lw <= 1; l_n <= 1; l_w <= 1; ps_g <= 1; psg <= 1; yn <= 1; y_n <= 1; red_s <= 1; red_w <= 1; red_e <= 1; reds <= 1; redw <= 1; rede <= 1; pw_r <= 1; pn_r <= 1; pe_r <= 1; end north_r : begin ln <= 1; l_n <= 1; red_s <= 1; red_w <= 1; red_e <= 1; reds <= 1; redw <= 1; rede <= 1; ps_r <= 1; pw_r <= 1; pn_r <= 1; pe_r <= 1; end east_g : begin re <= 1; se <= 1; le <= 1; ln <= 1; l_n <= 1; l_e <= 1; red_s <= 1; red_w <= 1; red_n <= 1; reds <= 1; redw <= 1; rede <= 1;

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ps_r <= 1; pw_r <= 1; pn_r <= 1; pe_r <= 1; end east_orange : begin ln <= 1; le <= 1; l_n <= 1; l_e <= 1; pw_g <= 1; pwg <= 1; ye <= 1; y_e <= 1; red_s <= 1; red_w <= 1; red_n <= 1; reds <= 1; redw <= 1; rede <= 1; ps_r <= 1; pn_r <= 1; pe_r <= 0; end east_r : begin le <= 1; l_e <= 1; red_s <= 1; red_w <= 1; red_n <= 1; reds <= 1; redw <= 1; rede <= 1; ps_r <= 1; pw_r <= 1; pn_r <= 1; pe_r <= 1; end default : begin red_s <= 0; red_w <= 0; red_n <= 0; red_e <= 0; rs <= 0; rw <= 0; rn <= 0; re <= 0; ss <= 0; sw <= 0; sn <= 0; se <= 0; ls <= 0; lw <= 0; ln <= 0; le <= 0;

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ps_g <= 0; pw_g <= 0; pn_g <= 0; pe_g <= 0; ys <= 0; yw <= 0; yn <= 0; ye <= 0; ps_r <= 0; pw_r <= 0; pn_r <= 0; pe_r <= 0; l_n <= 0; l_w <= 0; l_e <= 0; l_s <= 0; png <= 0; pwg <= 0; peg <= 0; psg <= 0; y_n <= 0; y_w <= 0; y_e <= 0; y_s <= 0; redn <= 0; redw <= 0; rede <= 0; reds <= 0; end endcase end

endmodule

UCF FILE:
net clk loc = p181; net rst loc = p182; net net net net net net net net net net net net net ls lw ln le ss sw sn se rs rw rn re loc loc loc loc loc loc loc loc loc loc loc loc = = = = = = = = = = = = p150; P130; P125; p107; p152; P146; p123; p115; p111; P147; P122; P114; #J3-25 #J3-6 #J3-9 #J3-20 #J3-26 #J3-4 #J3-11 #J3-17 #J3-23 #J3-3 #J3-12 #J3-18

red_s loc = p108; #J3-21

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net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net

red_w loc = P126; #J3-8 red_n loc = P120; #J3-13 red_e loc = p109; #J3-22 ys yw yn ye ps_r pw_r pn_r pe_r ps_g pw_g pn_g pe_g l_n y_n redn png l_w y_w redw pwg l_e y_e rede peg l_s y_s reds psg loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc loc = = = = = = = = = = = = = = = = = = = = = = = = = = = = p113; P131; P119; p106; P13; p149; p117; P124; p12; P148; p128; P116; P71; P72; P74; p76; P58; P61; P62; P63; p80; p79; p78; P77; p68; p67; p65; p64; #J3-24 #J3-5 #J3-14 #J3-19 #J3-27 #J3-1 #J3-10 #J3-15 #J3-28 #J3-2 #J3-7 #J3-16

7.5 RESULT:Thus traffic light controller is implemented on FPGA and verified using traffic light interface.

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EX.NO:8 DATE:

DESIGN A REAL TIME CLOCK &ITS WORKING ON FPGA BOARD

8.1 AIM: To design a real time clock and its working on a FPGA board using Spartan 3 kit.

8.2 TOOLS REQUIRED: Xilinx ISE (9.li) project navigator. Xilinx -XST Personal Computer

8.3 PROCEDURE: 1. Start the xilinx ISE by using start program file xilinx ISE (9.li) project Navigator. 2. File New project 3. Enter project name and location then click next select device and other category and click next twice and finish. 4. Select the device click on FPGA symbol device and right -> click on new source. 5. Select verilog module, give file name click next then define ports & click next and finish. 6. Writing the behavioral verilog code in verilog editor. 7. Run check syntax by clicking on process window double click on check syntax. 8. Synthesize the design by selecting synthesize/implementation from the window. Now double click synthesize XST. 9. Design implementation begins with mapping or filtering of a logical design file a specific device and is complete when physical design is successfully routed. 10. Double click implementation on design programming files configure device(IMPACT). 11. Select configure device using JTAG in the IMPACT window and then click finish. 12. Open the bit file of design.

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13. Window now shows the FPGA device. Xilinx Right click program click 14. Programming properties will be opened click Ok. 15. Then system shows whether program succeeded or failed. 16. If the program succeeded give the input in the RIL and check the output. 8.4 PROGRAM( onboard)
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 20:26:48 06/20/2007 // Design Name: // Module Name: finalclock_verilog // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // //--This is real time clock in this we use //4mhz clock //to generate 1 sec clock we use enable signal high for last 1 count // sec1 counter for reading sec // sec2 counter for reading sec // min1 counter for reading min // min2 counter for reading min // hr1 counter for reading hr // hr2 counter for reading hr ////////////////////////////////////////////////////////////////////////////////// module finalclock_verilog(sgout,dis,hr2,hr1,min2,min1,sec1,sec2,load,tc1,tc2,tc3,tc4,tc5,tc6,enable,reset,clock); output [3:0]sec1,sec2,min1,min2,hr1,hr2; output [7:0]sgout; output [5:0]dis; output tc1,tc2,tc3,tc4,tc5,tc6,enable; input reset,clock,load;

reg [3:0]sec1_rg,sec2_rg,min1_rg,min2_rg,hr1_rg,hr2_rg; reg [21:0] pulsegen ; reg [2:0]cnk2; reg [3:0]mout; reg [7:0]sgout_rg;

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reg [5:0]dis_sig; //reg tc,tc1,tc2,tc3,tc4,tc5,tc6,enable; //reg sec1_rg(3:0),sec2_rg(3:0),min1_rg(3:0),min2_rg(3:0),hr1_rg(3:0); //reg hr2_rg(3:0),pulsegen(21:0),sel(2:0); //reg mout(3:0),sgout(7:0),ck1(22:0),cnk2(2:0);

//*************************** Pulse Generator ****************** always@(posedge clock or posedge reset) begin if (reset) pulsegen <= 22'b0; else begin if (pulsegen == 22'b1111010000100100000000) pulsegen <= 22'b0; else pulsegen <= pulsegen + 1; end end

//Enable signal to generate 1-sec pulse for sec1 counter assign enable = (pulsegen == 22'b1111010000100100000000) ; //enable signal for sec1 counter

//************************ Second_cntr1 ************************* always@(posedge clock or posedge reset) begin if (reset ) sec1_rg <= 4'b0000; else if (load) begin sec1_rg <= 4'b0100; end else begin if (enable) begin if (sec1_rg == 4'b1001) sec1_rg <= 4'b0000; else sec1_rg <= sec1_rg + 1; end end end assign sec1 = sec1_rg; //------------------tc1 signal to start sec2 counter--------------------------assign tc1 = (sec1_rg == 4'b1001) && (enable == 1);

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//--************************* Second_cntr2 *********************** always@(posedge clock or posedge reset) begin if (reset ) sec2_rg <= 4'b0000; else if (load) begin sec2_rg <= 4'b0100; end

else begin if (tc1) begin if (sec2_rg == 4'b0101) begin sec2_rg <= 4'b0000; end else begin sec2_rg <= sec2_rg + 1; end end end end assign sec2 = sec2_rg; //-------------------------tc2 signal to start min1 counter------------------assign tc2 = (sec2_rg == 4'b0101) && (tc1 == 1);

//--************************ Minute_cntr1 ************************* always@(posedge clock or posedge reset) begin if (reset ) min1_rg <= 4'b0000; else if (load) begin min1_rg <= 4'b0100; end

else begin if (tc2) begin if (min1_rg == 4'b1001) begin min1_rg <= 4'b0000; end else begin min1_rg <= min1_rg + 1; end end end

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end assign min1 = min1_rg; //------------------------tc3 signal to start min2 counter-------------------assign tc3 = (min1_rg == 4'b1001) && (tc2 == 1); //--************************ Hour_cntr1 ************************* always@(posedge clock or posedge reset) begin if (reset) min2_rg <= 4'b0000; else if (load) begin min2_rg <= 4'b0100; end

else begin if (tc3) begin if (min2_rg == 4'b0101) begin min2_rg <= 4'b0000; end else begin min2_rg <= min2_rg + 1; end end end end assign min2 = min2_rg; //---------------------tc4 signal to start hr1 counter-------------------------assign tc4 = (min2_rg == 4'b0101) && (tc3 == 1);

//--************************ Hour_cntr1 ************************* always@(posedge clock or posedge reset) begin if (reset) hr1_rg <= 4'b0000; else if (load) begin hr1_rg <= 4'b0001; end

else begin if (tc6) begin hr1_rg <= 4'b0000;

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end else begin if (tc4) begin if (hr1_rg == 4'b1001) begin hr1_rg <= 4'b0000; end else begin hr1_rg <= hr1_rg + 1; end end end end end assign hr1 = hr1_rg; //---------------------tc5 signal to start hr2 counter-------------------------assign tc5 = (hr1_rg == 4'b1001) && (tc4 == 1); //------------------------tc6 signal to reset at 23:59:59-------------------------assign tc6 = (hr2_rg == 4'b0010) && (hr1_rg == 4'b0011) && (tc4 == 1);

//--************************ Hour_cntr2 ************************* always@(posedge clock or posedge reset) begin if (reset) hr2_rg <= 4'b0000; else if (load) begin hr2_rg <= 4'b0000; end else begin if (tc6) begin hr2_rg <= 4'b0000; end else begin if (tc5) begin if (hr2_rg == 4'b0010) begin hr2_rg <= 4'b0000; end else begin hr2_rg <= hr2_rg + 1; end end

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end end end assign hr2 = hr2_rg;

always@(posedge pulsegen[9] or posedge reset) begin if (reset) cnk2 <= 3'b0; else begin if (cnk2 == 3'b101) cnk2 <= 3'b0 ; else cnk2 <= cnk2 + 1; end end always@(cnk2) case (cnk2) 3'b000 : mout <= sec1; 3'b001 : mout <= sec2; 3'b010 : mout <= min1; 3'b011 : mout <= min2; 3'b100 : mout <= hr1; 3'b101 : mout <= hr2; endcase

always@(mout) case (mout) 4'b0000 : sgout_rg <= 8'b11000000; 4'b0001 : sgout_rg <= 8'b11111001; 4'b0010 : sgout_rg <= 8'b10100100; 4'b0011 : sgout_rg <= 8'b10110000; 4'b0100 : sgout_rg <= 8'b10011001; 4'b0101 : sgout_rg <= 8'b10010010; 4'b0110 : sgout_rg <= 8'b10000010; 4'b0111 : sgout_rg <= 8'b11111000; 4'b1000 : sgout_rg <= 8'b10000000; 4'b1001 : sgout_rg <= 8'b10011000; endcase

always@(cnk2) case (cnk2) 3'b000 : dis_sig <= 6'b111110; 3'b001 : dis_sig <= 6'b111101; 3'b010 : dis_sig <= 6'b111011; 3'b011 : dis_sig <= 6'b110111; 3'b100 : dis_sig <= 6'b101111; 3'b101 : dis_sig <= 6'b011111; endcase

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assign sgout = sgout_rg; assign dis = dis_sig; //always@(mout) //case (mout) //4'b0000 : sgout_rg <= 8'b00111111; //4'b0001 : sgout_rg <= 8'b00000110; //4'b0010 : sgout_rg <= 8'b01011011; //4'b0011 : sgout_rg <= 8'b01001111; //4'b0100 : sgout_rg <= 8'b01100110; //4'b0101 : sgout_rg <= 8'b01101101; //4'b0110 : sgout_rg <= 8'b01111101; //4'b0111 : sgout_rg <= 8'b00000111; //4'b1000 : sgout_rg <= 8'b01111111; //4'b1001 : sgout_rg <= 8'b01100111; //endcase // // //always@(cnk2) //case (cnk2) //3'b000 : dis_sig <= 6'b000001; //3'b001 : dis_sig <= 6'b000010; //3'b010 : dis_sig <= 6'b000100; //3'b011 : dis_sig <= 6'b001000; //3'b100 : dis_sig <= 6'b010000; //3'b101 : dis_sig <= 6'b100000; // endcase // //assign sgout = ~ sgout_rg; //assign dis = ~ dis_sig; endmodule UCF FILE: net net net net net net net net net net net net net net net net net clock loc ="p181"; reset loc = "p182"; load loc = "p57"; dis<5> loc = "p133"; dis<4> loc = "p132"; dis<3> loc = "p102"; dis<2> loc = "p101"; dis<1> loc = "p100"; dis<0> loc = "p97"; sgout<7> sgout<6> sgout<5> sgout<4> sgout<3> sgout<2> sgout<1> sgout<0> loc loc loc loc loc loc loc loc = = = = = = = = "p135"; "p137"; "p138"; "p139"; "p140"; "p141"; "p143"; "p144";

8.5 RESULT: Thus the real time clock and its working on a FPGA board using Spartan 3kit is designed.

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EX.NO:9 DATE:

DESIGN AND SIMULATION OF PIPELINED SERIAL AND PARALLEL ADDER/SUBTRACTOR

9.1 AIM: To design and simulate the pipelined adder of subtractor using verilog module (9.li) project navigator. 9.2 TOOLS REQUIRED: Xilinx ISE (9.li) project Navigator. Xilinx ISE-XST PC DESCRIPTION:Pipeline technique allows a operating circuit at high clock rate by dividing a large task into smaller non-overlapping sub task. This allows for prequel without the need of extra computing units. Final results are obtained after completing all stages. Careful selection of latch insertion points is an important factor for obtaining optimal throughput. SERIAL ADDER/ SUBIRACTOR:The serial adder is the basics of any adder structure. Since it is simply composed of n-bit adders are connected in series. Prequel adder/ subtractor connect all the inputs then all values at same time. The prequel subtractor gives out different values at same time. 9.3 PROCEDURE: 1. Start the xilinx ISE (9.li) project navigator. 2. File New project. 3. Enter the project name and location then click next 4. Select device & other category & click next and finish. 5. Click on the symbol FPGA device and then right. click click on new source select verilog module and give file name, click next and define ports. 6. In this input and output ports are assigned. 7. Write the behavioral verilog code in verilog editor. Run check syntax process window Synthesize XST. 8. Click on the symbol FPGA and then right click click on new source.

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9. Select the test bench waveform and give the file name. Select entity click next and finish. 10. Select desired parameter for selecting our design in this single clock and simulation line click finish. 11. Assign all input signal using just click behavioral simulation from drop down menu. 12. Select the test bench waveform (.tbw) and click process button double click the simulation behavioral model. 13. Verify your design in wave window by using the behaviour of output signal with respect to input signal.

9.4 PROGRAM:
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 13:54:26 09/19/2005 // Design Name: // Module Name: alu // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module alu(inp, sel,clk,rst,cntrl,outps,outpp); input [11:0] inp; input sel; input clk; input rst; input cntrl; output [15:0] outps; output [15:0] outpp; reg [15:0] outps; reg [15:0] outpp; reg [11:0] mem [7:0];

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reg [2:0]cnt; reg en;

always @(inp or clk or rst or sel or cntrl) begin if(clk) begin if(rst) begin outps = 15'b0; outpp = 15'b0; mem[0]=12'b0; mem[1]=12'b0; mem[2]=12'b0; mem[3]=12'b0; mem[4]=12'b0; mem[5]=12'b0; mem[6]=12'b0; mem[7]=12'b0; cnt = 3'b0; en = 1'b1; end else begin if(sel) begin if(cntrl) begin if(en) begin mem[cnt] = inp; en = 1'b0; if(cnt <= 3'b111) begin outps = outps + mem[cnt]; cnt = cnt + 1; end if(cnt == 3'b111) begin outpp = mem[0] + mem[1] + mem[2] + mem[3] + mem[4] + mem[5] + mem[6] + mem[7]; end end end else begin en = 1'b1; end end else

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begin if(cntrl) begin if(en) begin mem[cnt] = inp; if(cnt == 3'b0) begin outps = mem[cnt]; cnt = 3'b001; end else if(cnt <= 3'b111) begin outps = outps - mem[cnt]; cnt = cnt + 1; en = 1'b0; end if(cnt == 3'b111) begin outpp = mem[0] - mem[1] - mem[2] - mem[3] - mem[4] - mem[5] - mem[6] - mem[7]; end end end else begin // end end end end end

en = 1'b1;

endmodule

9.5 RESULT: Thus the Pipelined Serial and Parallel Adder/Subtractor was designed and waveforms are verified.

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