CPS 104 Computer Organization and Programming Lecture- 21: Building a Datapath

Feb 27, 2004 Gershon Kedem http://kedem.duke.edu/cps104/Lectures

CPS104 Lec21.1

GK Spring 2004

Admin.

Homework-4 is posted. Due March. 1st. In class. Midterm Exam March 5th. u In Class u 1 hour u Closed books u Covers all material including Data-path. u Bring SPIM manual and/or Common MIPS Instructions. Wednesday March 3, Review Session u Bring questions about ANY topic we covered in the course.

CPS104 Lec21.2

GK Spring 2004

Review: RTL: The Load Instruction

31

26 op 6 bits

21 rs 5 bits

16 rt 5 bits immediate 16 bits

lw
u

rt, rs, imm16 mem[PC]

Fetch the instruction from memory

Addr <- R[rs] + SignExt(imm16) Calculate the memory address R[rt] <- Mem[Addr] Load the data into the register PC <- PC + 4
31

Calculate the next instructions address

0 immediate 16 bits 0 immediate 16 bits

16 15 0 0000000000000000 16 bits 16 15 1111111111111111 1 16 bits

31

CPS104 Lec21.3

GK Spring 2004

Review: Datapath for Load Operations

R[rt] <- Mem[R[rs] + SignExt[imm16]] imm16 31 26 21 16

op 6 bits Rd RegDst Rt Rs 5 5 Dont Care (Rt) busA 32 busB 32 Extender 32 ALUSrc
0

Example: lw
0

rt, rs,

rs 5 bits

rt 5 bits

immediate 16 bits

1 Mux 0

RegWr 5 busW 32 Clk

ALUctr MemtoReg
0

Rw Ra Rb 32 32-bit Registers

ALU

Mux

32 MemWr WrEn Adr

32

Mux Data In 32 Clk

imm16

16

Data Memory

CPS104 Lec21.4

GK Spring 2004

ExtOp

RTL: The Store Instruction

31 26 op 6 bits

21 rs 5 bits

16 rt 5 bits immediate 16 bits

sw rt, rs, imm16

u

mem[PC]

Fetch the instruction from memory

Addr <- R[rs] + SignExt(imm16) Calculate the memory address Mem[Addr] <- R[rt] PC <- PC + 4 Store the register into memory Calculate the next instructions address

CPS104 Lec21.5

GK Spring 2004

Review: Datapath for Store Operations

Mem[R[rs] + SignExt[imm16] ] <- R[rt] sw rt, rs, imm16

31 26 op 6 bits Rd Rt Rs Rt 5 5 busA 32 busB 32 Extender 32
0

21 rs 5 bits

16 rt 5 bits immediate 16 bits

RegDst

1 Mux 0

RegWr 5 busW 32 Clk

ALUctr MemWr ALU MemtoReg

Rw Ra Rb 32 32-bit Registers

Mux

32 32 WrEn Adr

Mux Data In 32 ALUSrc Clk

imm16

16

Data Memory

CPS104 Lec21.6

ExtOp

GK Spring 2004

RTL: The Branch Instruction

31 26 op 6 bits

21 rs 5 bits

16 rt 5 bits immediate 16 bits

beq rs, rt, imm16

u

mem[PC] Cond <- R[rs] - R[rt] if (COND eq 0)

Fetch the instruction from memory Calculate the branch condition

Calculate the next instructions address

PC <- PC + 4 + ( SignExt(imm16) x 4 ) PC <- PC + 4

else

CPS104 Lec21.7

GK Spring 2004

Datapath for Branch Operations

beq

rs, rt, imm16

31 26 op 6 bits Rd Rt Rs Rt 5 5 busA 21 rs 5 bits

We need to compare Rs and Rt!

16 rt 5 bits immediate 16 bits Branch Clk 0

RegDst

PC

1 Mux 0

RegWr 5 busW 32 Clk

ALUctr

imm16 16

Next Address Logic

Rw Ra Rb 32 32-bit Registers

32 busB 32 Extender 32 ALUSrc

0

ALU

Zero

To Instruction Memory

Mux

imm16

16

CPS104 Lec21.8

GK Spring 2004

ExtOp

Binary Arithmetic for the Next Address

In theory, the PC is a 32-bit byte address into the instruction memory: u Sequential operation: PC<31:0> = PC<31:0> + 4 u Branch operation: PC<31:0> = PC<31:0> + 4 + SignExt[Imm16] * 4 The magic number 4 always comes up because: u The 32-bit PC is a byte address u And all our instructions are 4 bytes (32 bits) long In other words: u The 2 LSBs of the 32-bit PC are always zeros u There is no reason to have hardware to keep the 2 LSBs In practice, we can simplify the hardware by using a 30-bit PC<31:2>: u Sequential operation: PC<31:2> = PC<31:2> + 1 u Branch operation: PC<31:2> = PC<31:2> + 1 + SignExt[Imm16] u In either case: Instruction-Memory-Address = PC<31:2> concat 00
GK Spring 2004

CPS104 Lec21.9

Next Address Logic: Expensive and Fast Solution

Using a 30-bit PC: u Sequential operation: PC<31:2> = PC<31:2> + 1 u Branch operation: PC<31:2> = PC<31:2> + 1 + SignExt[Imm16] u In either case: Instruction-Memory-Address = PC<31:2> concat 00
30 30 30 1 Clk imm16 Instruction<15:0> 16 SignExt 00 0 30 Adder Mux Adder Addr<31:2> Addr<1:0> Instruction Memory 32 PC

1 30

30

Instruction<31:0> Branch Zero

GK Spring 2004

CPS104 Lec21.10

Next Address Logic

30 30 0 Clk imm16 Instruction<15:0> 16 0 Mux Addr<31:2> Addr<1:0> Instruction Memory 32 PC

1 Carry In Adder

00

1 30 30

30

SignExt

Instruction<31:0> Branch Zero

CPS104 Lec21.11

GK Spring 2004

RTL: The Jump Instruction

31 26 op 6 bits target address 26 bits 0

j
u

target mem[PC] Fetch the instruction from memory

PC<31:2> <- PC<31:28> concat target<26:0> concat <00> Calculate the next instructions address

CPS104 Lec21.12

GK Spring 2004

Instruction Fetch Unit

j
u

target PC<31:2> <- PC<31:28> concat target<25:0>

30 PC<31:28> Target Instruction<25:0> PC Clk 30 1 4 30 26 0 30 Adder Mux 30 00 1 Mux 0 Addr<31:2> Addr<1:0> Instruction Memory 32

Adder SignExt 30

1 30

Jump

Instruction<31:0>

imm16 Instruction<15:0> 16

Branch
CPS104 Lec21.13

Zero
GK Spring 2004

Putting it All Together: A Single Cycle Datapath

We have everything except control signals.

Branch Rd RegDst Rt Rs 5 5 busA 32 0 Mux ALU Rt Jump Clk Instruction Fetch Unit

Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

1 Mux 0 RegWr 5 ALUctr

Rt Zero

Rs

Rd

Imm16 MemtoReg 0 Mux

busW 32 Clk

Rw Ra Rb 32 32-bit Registers busB 32 Extender

MemWr

32 32 WrEn Adr

1 32

imm16

Data In 32 Clk

16

Data Memory

ALUSrc
CPS104 Lec21.14

ExtOp

GK Spring 2004

RTL: The ADD Instruction

31 op 6 bits 26 rs 5 bits 21 rt 5 bits 16 rd 5 bits 11 shamt 5 bits 6 funct 6 bits 0

add rd, rs, rt

u

mem[PC] R[rd] <- R[rs] + R[rt] PC <- PC + 4

Fetch the instruction from memory The actual operation

Calculate the next instructions address

CPS104 Lec21.15

GK Spring 2004

Instruction Fetch Unit at the Beginning of Add / Subtract

Fetch the instruction from Instruction memory: Instruction <mem[PC] u This is the same for all instructions
30 PC<31:28> Target Instruction<25:0> PC Clk 30 1 4 30 26 0 30 Adder Mux 30 00 1 Mux 0 Addr<31:2> Addr<1:0> Instruction Memory 32

Adder SignExt 30

1 30

Jump = previous Instruction<31:0>

imm16 Instruction<15:0> 16

Branch = previous Zero = previous

CPS104 Lec21.16
GK Spring 2004

The Single Cycle Datapath during Add and Subtract

31 op

26 rs

21 rt

16 rd

11 shamt

6 funct

R[rd] <- R[rs] + / - R[rt]

Branch = ? Rd Rt Rs 5 5 Jump = ? Clk Rt Instruction Fetch Unit ALUctr = ?

Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

RegDst = ?

1 Mux 0

RegWr = ? 5 busW 32 Clk

Rt Zero ALU

Rs

Rd

Imm16 MemtoReg = ?

busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

MemWr = ? 0 Mux 32

32 WrEn Adr

Mux Data In 32 Clk

imm16

16

Data Memory

ALUSrc = ?
CPS104 Lec21.17

ExtOp = ?

GK Spring 2004

The Single Cycle Datapath during Add and Subtract

31 op

26 rs

21 rt

16 rd

11 shamt

6 funct

R[rd] <- R[rs] + / - R[rt]

Branch = 0 Rd Rt Rs 5 5 Jump = 0 Clk Rt Instruction Fetch Unit ALUctr = Add or Sub

Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

RegDst = 1

1 Mux 0

RegWr = 1 5 busW 32 Clk

Rt Zero

Rs

Rd

Imm16 MemtoReg = 0

busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

MemWr = 0 0 Mux 32

ALU

32 WrEn Adr

Mux Data In 32 Clk

imm16

16

Data Memory

ALUSrc = 0
CPS104 Lec21.18

ExtOp = x

GK Spring 2004

Instruction Fetch Unit at the End of Add and Subtract

PC <- PC + 4 u This is the same for all instructions except: Branch and Jump
30 PC<31:28> Target Instruction<25:0> PC Clk 30 1 4 30 26 0 30 Adder Mux 30 00 1 Mux 0 Addr<31:2> Addr<1:0> Instruction Memory 32

Adder SignExt 30

1 30

Jump = ?

Instruction<31:0>

imm16 Instruction<15:0> 16

Branch = ? Zero = ?
CPS104 Lec21.19
GK Spring 2004

Instruction Fetch Unit at the End of Add and Subtract

PC <- PC + 4 u This is the same for all instructions except: Branch and Jump
30 PC<31:28> Target Instruction<25:0> PC Clk 30 1 4 30 26 0 30 Adder Mux 30 00 1 Mux 0 Addr<31:2> Addr<1:0> Instruction Memory 32

Adder SignExt 30

1 30

Jump = 0

Instruction<31:0>

imm16 Instruction<15:0> 16

Branch = 0 Zero = x
CPS104 Lec21.20
GK Spring 2004

The Single Cycle Datapath during Or Immediate

31 op

26 rs

21 rt

16 immediate

R[rt] <- R[rs] or ZeroExt[Imm16]

Branch = ? Rd Rt Rs 5 5 Jump = ? Clk Rt Instruction Fetch Unit Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

RegDst = ?

1 Mux 0 ALUctr = ?

RegWr = ? 5 busW 32 Clk

Rt Zero ALU

Rs

Rd

Imm16 MemtoReg = ?

busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

MemWr = ? 0 Mux 32

32 WrEn Adr

Mux Data In 32 Clk

imm16

16

Data Memory

ALUSrc = ?
CPS104 Lec21.21

ExtOp = ?

GK Spring 2004

The Single Cycle Datapath during Or Immediate

31 op

26 rs

21 rt

16 immediate

R[rt] <- R[rs] or ZeroExt[Imm16]

Branch = 0 Rd Rt Rs 5 5 Jump = 0 Clk Rt Instruction Fetch Unit Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

RegDst = 0

1 Mux 0 ALUctr = Or

RegWr = 1 5 busW 32 Clk

Rt Zero

Rs

Rd

Imm16 MemtoReg = 0

busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

MemWr = 0 0 Mux 32

ALU

32 WrEn Adr

Mux Data In 32 Clk

imm16

16

Data Memory

ALUSrc = 1
CPS104 Lec21.22

ExtOp = 0

GK Spring 2004

The Single Cycle Datapath during Load

31 op

26 rs

21 rt

16 immediate

R[rt] <- Data Memory {R[rs] + SignExt[imm16]}

Branch = ? Rd Rt Rs 5 5 Jump = ? Clk Rt Instruction Fetch Unit ALUctr = ? Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

RegDst = ?

1 Mux 0

RegWr = ? 5 busW 32 Clk

Rt Zero

Rs

Rd

Imm16 MemtoReg = ?

busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

MemWr = ? 0 Mux

ALU

32 WrEn Adr

Mux Data In 32 Clk

1 32

imm16

16

Data Memory

ALUSrc = ?
CPS104 Lec21.23

ExtOp = ?

GK Spring 2004

The Single Cycle Datapath during Load

31 op

26 rs

21 rt

16 immediate

R[rt] <- Data Memory {R[rs] + SignExt[imm16]}

Branch = 0 Rd Rt Rs 5 5 Jump = 0 Clk Rt Instruction Fetch Unit ALUctr = Add Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

RegDst = 0

1 Mux 0

RegWr = 1 5 busW 32 Clk

Rt Zero

Rs

Rd

Imm16 MemtoReg = 1

busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

MemWr = 0 0 Mux

ALU

32 WrEn Adr

Mux Data In 32 Clk

1 32

imm16

16

Data Memory

ALUSrc = 1
CPS104 Lec21.24

ExtOp = 1

GK Spring 2004

The Single Cycle Datapath during Store

31 op

26 rs

21 rt

16 immediate

Data Memory {R[rs] + SignExt[imm16]} <- R[rt]

Branch = Rd Rt Jump = Clk Instruction Fetch Unit ALUctr Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

RegDst =

1 Mux 0 5 Rs Rt 5 5

RegWr = busW 32 Clk

Rt Zero ALU

Rs

Rd

Imm16 MemtoReg =

busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

MemWr = 0 Mux 32

32 WrEn Adr

Mux Data In 32 Clk

imm16

16

Data Memory

ALUSrc =
CPS104 Lec21.25

ExtOp =

GK Spring 2004

The Single Cycle Datapath during Store

31 op

26 rs

21 rt

16 immediate

Data Memory {R[rs] + SignExt[imm16]} <- R[rt]

Branch = 0 Rd Rt Jump =0 Clk Instruction Fetch Unit ALUctr Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

RegDst =x

1 Mux 0 Rs Rt 5 5

RegWr = 0 5 busW 32 Clk

Rt Zero ALU

Rs

Rd

Imm16 MemtoReg =x

busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

MemWr =1 0 Mux 32

32 WrEn Adr

Mux Data In 32 Clk

imm16

16

Data Memory

ALUSrc =1
CPS104 Lec21.26

ExtOp = 1

GK Spring 2004

The Single Cycle Datapath during Branch

31 op

26 rs

21 rt

16 immediate

if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0

Branch = ? Rd Rt Rs 5 5 5 Zero ALU MemWr = ? 0 Mux 32 WrEn Adr Data In 32 Clk ALUSrc = ? Data Memory Jump = ? Clk Rt Instruction Fetch Unit ALUctr =? Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

RegDst = ?

1 Mux 0

RegWr = ?

Rt

Rs

Rd

Imm16 MemtoReg = ?

busW 32 Clk

busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

32

Mux

imm16

16

CPS104 Lec21.27

ExtOp = ?

GK Spring 2004

The Single Cycle Datapath during Branch

31 op

26 rs

21 rt

16 immediate

if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0

Branch = 1 Rd Rt Rs 5 5 5 Jump = 0 Clk Rt Instruction Fetch Unit ALUctr = Subtract Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

RegDst = x

1 Mux 0

RegWr = 0

Rt Zero ALU

Rs

Rd

Imm16 MemtoReg = x

busW 32 Clk

busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

MemWr = 0 0 Mux 32

32 WrEn Adr

Mux Data In 32 Clk

imm16

16

Data Memory

ALUSrc = 0
CPS104 Lec21.28

ExtOp = x

GK Spring 2004

Instruction Fetch Unit at the End of Branch

31 op

26 rs

21 rt

16 immediate

if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4

30 PC<31:28> Target Instruction<25:0> PC Clk 30 1 4 30 26 0 30 Adder Mux Jump = ? 1 0 32 Adder SignExt 30 Assume Zero = 1 to see the interesting case. Branch = ? Zero = 1
GK Spring 2004

30 00 Mux

Addr<31:2> Addr<1:0> Instruction Memory

1 30

Instruction<31:0>

imm16 16 Instruction<15:0>

CPS104 Lec21.29

Instruction Fetch Unit at the End of Branch

31 op

26 rs

21 rt

16 immediate

if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4

30 PC<31:28> Target Instruction<25:0> PC Clk 30 1 4 30 26 0 30 Adder Mux Jump = 0 1 0 32 Adder SignExt 30 Assume Zero = 1 to see the interesting case. Branch = 1 Zero = 1
GK Spring 2004

30 00 Mux

Addr<31:2> Addr<1:0> Instruction Memory

1 30

Instruction<31:0>

imm16 16 Instruction<15:0>

CPS104 Lec21.30

The Single Cycle Datapath during Jump

31 op

26 target address

Nothing to do! Make sure control signals are set correctly!

Branch = 0 Rd Rt Rs 5 5 Zero ALU MemWr = 0 0 Mux 32 WrEn Adr Data In 32 Clk ALUSrc = x Data Memory Jump = 1 Clk Rt Instruction Fetch Unit ALUctr = x Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

RegDst = x

1 Mux 0

RegWr = 0 5 busW 32 Clk

Rt

Rs

Rd

Imm16 MemtoReg = x

busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

32

Mux

imm16

16

CPS104 Lec21.31

ExtOp = x

GK Spring 2004

Instruction Fetch Unit at the End of Jump

31 op

26 target address

PC <- PC<31:28> concat target<25:0> concat 00

30 PC<31:28> Target Instruction<25:0> PC Clk 30 1 4 30 26 0 30 Adder Mux 30 00 1 Mux 0 Addr<31:2> Addr<1:0> Instruction Memory 32

Adder SignExt 30

1 30

Jump = 1

Instruction<31:0>

imm16 Instruction<15:0> 16

Branch = X Zero = x
CPS104 Lec21.32
GK Spring 2004