CMOS HSPICE

MODELSIM

CMOS . CMOS

N 2N .

. CMOS .

CMOS HSPICE Verilog

CMOS

CMOS pseudo-NMOS

Modelsim HSPICE

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CMOS . N
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vdd
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pmos vdd
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modelsim .

15 .

-3
CMOS
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.

*M1 out1 in1 vdd 0 pch w='6*lmin' l=lmin

*M2 out1 in1 0 0 nch w='2*lmin' l=lmin
.*ends
******************NAND
Dynamic
Gate**********************
Mp out clk vdd vdd pch w=" 22*lmin" l=lmin
M1 out A s1 0 nch w="2*lmin" l=lmin
M2 s1 B s2 0 nch w="2*lmin" l=lmin
Me s2 clk 0 0 nch w="2*lmin" l=lmin
*Mb s1 clk vdd vdd pch w="22*lmin" l=lmin
*Mb1 out c vdd vdd pch w="22*lmin" l=lmin
****************Adding
the
inverter***********************
*XINV_1 c out vdd 0 inv1
*******NAND
CMOS******************************
*
*M1 out A vdd vdd pch w="4*lmin" l=lmin
*M2 out B vdd vdd pch w="4*lmin" l=lmin
*M3 out A s3 0 nch w="2*lmin" l=lmin
*M4 s3 B 0 0 nch w="2*lmin" l=lmin
*****************Elements**************
******************
Cl out 0 10f
************simulations******************
******
.tran 051n 1u start=051p
************Analysis********************
***
***********output
************************
.end
Modelsim

`timescale 1ps/1ps

] 1 [J. M. Rabaey, A. Chandrakasan, and B. Nikolic,

Digital Integrated Circuits: Prentice Hall Press ,

.2118
] 2 [N. H. E. Weste and D. M. Harris, CMOS VLSI
Design; A Circuits and Systems Perspective. Boston ,
United States of America: Addison-Wesley, 2111.

:
****Farzin Akbar CA6****
.prot
.lib 'crn90g_2d5_lk_v1d2p1.l' tt
.unprot
.temp 27
.option node list post
.param lmin=100n
.param vdd=1
.option ingold=2
.option accurate=1
**************sources*******************
****
.ic v(out)=1
vdd vdd 0 vdd
vc clk 0 pulse(0 vdd 250n 0 0 250n 500n)
*Vname N1 N2 PULSE(V1 V2 TD Tr Tf PW Period)
vb b 0 pulse(0 vdd 50n 0 0 100n 200n)
va a 0 pulse(0 vdd 0 0 0 100n 200n)
*va a 0 vdd
*vb b 0 vdd

module DyNand(input a,b,clk, output nandout;)

supply1 vdd;
supply0 gnd;

*************Inverter
Subcircuit*************************
.*subckt inv1 out1 in1 vdd 0

wire s1,s2,clk;_
wire o_delay;
parameter d=100;
pmos (nandout,vdd,clk;)
nmos (nandout,s1,a;)
nmos (s1,s2,b;)
nmos (s2,gnd,clk;)
not(clk_,clk;)
trireg (medium) #(0010) storage;
assign #d o_delay = nandout;
rcmos (storage,o_delay,clk,clk;)_

endmodule

:
`timescale 1ps/1ps
module

clkGen #(parameter halfCycle=10)(output reg

clk);
initial clk=0;
always @(clk)
#halfCycle clk<=~clk;
endmodule

:
`timescale 1ps/1ps

module tb_DyNand();
wire clk;
clkGen clkgen(clk);
reg a1,b1;
wire out1;

DyNand Dnand (a1,b1,clk,out1);

initial begin

011
a1=1;
b1=1;

051;
a1=1;
b1=1;

051;
a1=1;
b1=1;

051;
a1=1;
b1=1;

051;
end
endmodule