Advanced CMOS Process Technology

MICROELECTRONIC ENGINEERING ROCHESTER INSTITUTE OF TECHNOLOGY

Advanced CMOS Process Technology Part 1 and 2 Dr. Lynn Fuller

Webpage: http://people.rit.edu/lffeee Microelectronic Engineering Rochester Institute of Technology 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585) 475-2035 Fax (585) 475-5041 Email: Lynn.Fuller@rit.edu Department webpage: http://www.microe.rit.edu
Rochester Institute of Technology Microelectronic Engineering

4-19 -2010 ADV_CMOS_Part1-2.ppt

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OUTLINE Devices for 0.15 m CMOS High Performance Sub 0.1 m Channel nMOSFETs Sub - 1/4 m Dual-Gate CMOS Technology High-Performance 0.07 - m CMOS Enhanced Strain Effects in 25-nm Gate-Length Thin-Body nMOSFET

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1995

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In Preamorphization As Implant 50nm deep

Sb Preamorphization BF2 Implant 60nm deep

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Rochester Institute of Technology Microelectronic Engineering

Silicon on Insulator
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~75 mV/dec nMOS ~80 mV/dec pMOS

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0.08 m MOSFETS

The T shaped gate structure helps reduce resistance of the gate connection
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Rochester Institute of Technology Microelectronic Engineering

December 8, 1998
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(Continued)
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0.06 m MOSFETS

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IEDM 1999
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0.05 m MOSFET Dopant Profile

IEEE Spectrum July 1999

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ATOMIC SCALE TRANSISTORS

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0.03 m Leff MOSFETS IMEC Meeting December 1999

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0.03 m MOSFETS

Xox 4.0 nm gate oxide

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0.03 m MOSFETS

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0.025m

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0.025m

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0.025m

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0.02 m MOSFET

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0.02 m MOSFET

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0.02 m MOSFET

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0.006 m MOSFET

Channel is 4 nm thick on Buried Oxide. 8-19-2002

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MULTILAYER METAL, W PLUGS, CMP

8 Layers Metal
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REFERENCES 1. IEEE Electron Device Letters 2. Electronics News 3. Silicon Processing for the VLSI Era Vol 2. - Process Integration. 4. The Science and Engineering of Microelectronic Fabrication, Stephen A. Campbell. 5. May 1999, IEEE Electron Device Letters, Fabrication and Characterization of Sub 0.25 m Copper Gate MOSFET with copper gate, page 254 6. July 1999 IEEE Transactions on Electron Devices, An 0.18 um CMOS for Mixed Digital and Analog Applications with Zero-Volt-Vth Epitaxial Channel MOSFETs, page 1378. 7. IEEE Journal of Solid-State Circuits, CMOS Technology - Year 2010 and Beyond, H. Iwai, Pg 357. 8. Solid State Technology, July 1999, Cobalt Silicide Processing in a Susceptor Based LP-RTP System, pg 125.
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REFERENCES 9. Solid State Technology's WaferNEWS - www.wafernews.com 10. EE Times Newsletter [from_EETimes@newsletter.eetimes.com] 11. Internationa Technology Roadmap for Semiconductors (ITRS) http://www.itrs.net

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HOMEWORK- ADVANCED CMOS PART 1&2 1. Briefly describe the following CMOS process enhancements, a) silicide, b) salicide, c) dual doped gate CMOS, d) side wall spacers, e) gate stack formation, f) multi layer metal. 2. What types of lithography technology was used to make the < 0.2 m transistors described in this set of notes? 3. What types of isolation technology was used to make the CMOS devices described in this set of notes? 4. What technology is used to reduce Boron penetration through the gate oxide for the devices described in this set of notes? 5. Sketch the crossection of the 0.07 m CMOS described in this set of notes. Make the sketch to scale in both the lateral direction and the direction into the wafer.
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