CIRCUIT DIAGRAM FOR FULL ADDER

a b

SUM

C2

CARRY

Cin

TRUTH TABLE A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1 SUM 0 1 1 0 1 0 0 1 CARRY 0 0 0 1 0 1 1 1

EXPRESSION FOR FULL ADDER

SUM = a xor b xor Cin; CARRY = ab + bCin + aCin;

ADDERS
AIM: To design Full adder in all models using VHDL and verify the same using Modelsim simulator. VHDL CODE: FULL ADDER USING DATAFLOW MODELLING library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity fulladder_df is Port ( a,b,cin : in std_logic; sum,cy : out std_logic); end fulladder_df; architecture fa_df of fulladder_df is begin sum <= a xor( b xor cin); cy <= (a and b)or(b and cin)or(cin and a); end fa_df;

FULL ADDER USING BEHAVIOURAL MODELLING library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity fa2 is port ( a,b,cin : in std_logic; sum,cy :out std_logic); end fa2; architecture fa2_bv of fa2 is

begin process(a,b,cin) begin if(a='0' and b='0' and cin='0')then sum<='0';cy<='0'; elsif(a='0' and b='0' and cin='1')then sum<='1';cy<='0'; elsif(a='0' and b='1' and cin='0')then sum<='1';cy<='0'; elsif(a='0' and b='1' and cin='1')then sum<='0';cy<='1'; elsif(a='1' and b='0' and cin='0')then sum<='1';cy<='0'; elsif(a='1' and b='0' and cin='1')then sum<='0';cy<='1'; elsif(a='1' and b='1' and cin='0')then sum<='0';cy<='1'; elsif(a='1' and b='1' and cin='1')then sum<='1';cy<='1'; end if; end process; end fa2_bv;

FULL ADDER USING STRUCTURAL MODELLING library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity or2 is port ( a,b: in std_logic; --component OR2

OUTPUT WAVE FORM FOR FULL ADDER

z:out std_logic); end or2; architecture or_2 of or2 is begin z<=a or b; end or_2;

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity fa3 is port ( p,q,r: in std_logic; sum,cy:out std_logic); end fa3; architecture fa_str of fa3 is component ha is port ( a,b: in std_logic; s,cy: out std_logic); end component; component or2 is port ( a,b: in std_logic; z:out std_logic); end component; signal s,cy1,cy2: std_logic; begin h1: ha port map (p,q,s,cy1); h2: ha port map (s,r,sum,cy2); a3: or2 port map (cy1,cy2,cy); end fa_str;

--main program

--component HA

--component OR2

RESULT: Thus source codes in VHDL for Full Adders have been written, compiled and simulated using modelsim simulator.

CIRCUIT DIAGRAM FOR 4 BIT ADDER

A3 A3 B3 B3 A2 AA B2 A1 A1 B1 B1 A0 A0 B0 B0

Cin

FA3

FA2

FA1

FA0

cout cout

S3

C2

S2

C1

S1

C0

S0

OUTPUT WAVE FORM FOR 4 BIT ADDER

4-BIT ADDER USING STRUCTURAL MODELLING AIM: To design a 4 Bit ripple carry adder using VHDL and verify the same using Modelsim simulator VHDL CODE library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity adder is port ( A,B: in std_logic_vector(3 downto 0); Cin: in std_logic; S: out std_logic_vector(3 downto 0); C: out std_logic); end adder; architecture bit_adder of adder is component fa1 is port (a,b,cin: in std_logic; s,cy: out std_logic); end component; signal c0,c1,c2:std_logic; begin x1: fa1 port map (A(0),B(0),Cin,S(0),c0); x2: fa1 port map (A(1),B(1),c0,S(1),c1); x3: fa1 port map (A(2),B(2),c1,S(2),c2); x4: fa1 port map (A(3),B(3),c2,S(3),C); end bit_adder;

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RESULT: Thus source codes in VHDL for 4 bit Ripple carry Adder have been written, compiled and simulated using modelsim simulator.

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Circuit Diagram:

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4 BIT CARRY LOOK AHEAD ADDER

AIM: To design 4 bit carry look ahead adder using VHDL and verify the same using Modelsim simulator. VHDL CODE --Library declaration library ieee; use ieee.std_logic_1164.all; --Entity declaration entity mux8to1 is port(d : in std_logic_vector(7 downto 0); s : in std_logic_vector(2 downto 0); y : out std_logic); end mux8to1; --Architecture declaration architecture mux8to1_s of mux8to1 is signal z: std_logic_vector(1 downto 0); component mux4to1 is port(i : in std_logic_vector(3 downto 0); s : in std_logic_vector(1 downto 0); y : out std_logic); end component; component mux2to1 is port(i : in std_logic_vector(1 downto 0); --Component declaration mux 2x1 --Component declaration mux 4x1

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SIMULATED OUTPUT:

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s : in std_logic; y : out std_logic); end component; begin s1: mux4to1 port map (d(3 downto 0),s(1 downto 0),z(0)); s2: mux4to1 port map (d(7 downto 4),s(1 downto 0),z(1)); s3: mux2to1 port map (z(1 downto 0),s(2),y); end mux8to1_s; RESULT: Thus source codes in VHDL for 8x1 mux have been written, compiled and simulated using modelsim simulator.

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COMBINATIONAL CIRCUITS

8x1 MULTIPLEXER
AIM: To design 8x1 multiplexer using VHDL and verify the same using Modelsim simulator. VHDL CODE: --Library declaration library ieee; use ieee.std_logic_1164.all; --Entity declaration entity mux8to1 is port(d : in std_logic_vector(7 downto 0); s : in std_logic_vector(2 downto 0); y : out std_logic); end mux8to1; --Architecture declaration architecture mux8to1_s of mux8to1 is signal z: std_logic_vector(1 downto 0); component mux4to1 is port(i : in std_logic_vector(3 downto 0); s : in std_logic_vector(1 downto 0); y : out std_logic); end component; component mux2to1 is port(i : in std_logic_vector(1 downto 0); s : in std_logic; y : out std_logic);
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--Component declaration mux 4x1

--Component declaration mux 2x1

SIMULATED OUTPUT:

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end component; begin s1: mux4to1 port map (d(3 downto 0),s(1 downto 0),z(0)); s2: mux4to1 port map (d(7 downto 4),s(1 downto 0),z(1)); s3: mux2to1 port map (z(1 downto 0),s(2),y); end mux8to1_s;

RESULT: Thus source codes in VHDL for 8x1 mux have been written, compiled and simulated using modelsim simulator.

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CIRCUIT DIAGRAM OF ENCODER:

TRUTH TABLE

D0 1 0 0 0 0 0 0 0

D1 0 1 0 0 0 0 0 0

D2 0 0 1 0 0 0 0 0

D3 0 0 0 1 0 0 0 0

D4 0 0 0 0 1 0 0 0

D5 0 0 0 0 0 1 0 0

D6 0 0 0 0 0 0 1 0

D7 0 0 0 0 0 0 0 1

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

EXPRESSION FOR ENCODER

A=d(4) or d(5) or d(6) or d(7); B=d(2) or d(3) or d(6) or d(7); C=d(1) or d(3) or d(5) or d(7);

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ENCODER & DECODER

AIM: Write a program for a Encoder and Decoder using three modeling in HDL

VHDL CODE:
8:3 ENCODER USING DATA FLOW MODELLING library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity encoder1 is port(d:in std_logic_vector(7 downto 0); A,B,C: out std_logic); end encoder1; architecture encode_df of encoder1 is begin A<=d(4) or d(5) or d(6) or d(7); B<=d(2) or d(3) or d(6) or d(7); C<=d(1) or d(3) or d(5) or d(7); end encode_df;

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8:3 ENCODER USING BEHAVIORAL MODELLING

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity encoder2 is port(d:in std_logic_vector(7 downto 0); z:out std_logic_vector(2 downto 0)); end encoder2; architecture encode_bv of encoder2 is signal sel:std_logic_vector(7 downto 0); begin process(sel,d(0),d(1),d(2),d(3),d(4),d(5),d(6),d(7)) begin sel<=d(0)&d(1)&d(2)&d(3)&d(4)&d(5)&d(6)&d(7); case sel is when "10000000"=>z<="000"; when "01000000"=>z<="001"; when "00100000"=>z<="010"; when "00010000"=>z<="011"; when "00001000"=>z<="100"; when "00000100"=>z<="101"; when "00000010"=>z<="110"; when others=>z<="111"; end case; end process; end encode_bv;

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8:3 ENCODER USING STRUCTURAL MODELLING

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity or4 is port (w,x,y,z : in std_logic; p: out std_logic); end or4; architecture or_4 of or4 is begin p<=w or x or y or z ; end or_4;

--component or4

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity encoder_str is port (s: in std_logic_vector (7 downto 0); A,B,C: out std_logic); end encoder_str; architecture encoder3 of encoder_str is component or4 is port (w,x,y,z : in std_logic; p: out std_logic); end component; begin
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--main program

--component OR4

WAVEFORMS OF ENCODER:

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x1: or4 port map( s(4),s(5),s(6),s(7),A); x2: or4 port map( s(7),s(6),s(3),s(2),B); x3: or4 port map( s(1),s(3),s(5),s(7),C); end encoder3;

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CIRCUIT DIAGRAM OF DECODER

TRUTH TABLE A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 D0 1 0 0 0 0 0 0 0 D1 0 1 0 0 0 0 0 0 D2 0 0 1 0 0 0 0 0 D3 0 0 0 1 0 0 0 0 D4 0 0 0 0 1 0 0 0 D5 0 0 0 0 0 1 0 0 D6 0 0 0 0 0 0 1 0 D7 0 0 0 0 0 0 0 1

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3:8 DECODER USING DATA FLOW MODELLING

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity decoder1 is port ( A,B,C : in std_logic; d : out std_logic_vector (7 downto 0)); end decoder1; architecture decoder_df of decoder1 is begin d(0)<=(not A) and (not B) and (not C); d(1)<=(not A) and (not B) and C; d(2)<=(not A) and B and (not C); d(3)<=(not A) and B and C; d(4)<= A and (not B) and (not C); d(5)<= A and (not B) and C; d(6)<= A and B and (not C); d(7)<= A and B and C; end decoder_df;

3:8 DECODER USING BEHAVIORAL MODELING

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity decoder2 is port (sel: in std_logic_vector (2 downto 0); D: out std_logic_vector (7 downto 0));
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EXPRESSION FOR DECODER d(0)<=(not A) and (not B) and (not C); d(1)<=(not A) and (not B) and C; d(2)<=(not A) and B and (not C); d(3)<=(not A) and B and C; d(4)<= A and (not B) and (not C); d(5)<= A and (not B) and C; d(6)<= A and B and (not C); d(7)<= A and B and C;

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end decoder2; architecture decoder_bv of decoder2 is begin process(sel) begin case sel is when "000"=>D<="00000001"; when "001"=>D<="00000010"; when "010"=>D<="00000100"; when "011"=>D<="00001000"; when "100"=>D<="00010000"; when "101"=>D<="00100000"; when "110"=>D<="01000000"; when others =>D<="10000000"; end case; end process; end decoder_bv;

3:8 DECODER USING STRUCTURAL MODELLING

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity and3 is port(p,q,r : in std_logic ; m : out std_logic); end and3; architecture and_3 of and3 is
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--component AND3

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begin m<=p and q and r; end and_3; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity decoder_str is port (A,B,C: in std_logic; D: out std_logic_vector (0 to 7)); end decoder_str; architecture decoder3 of decoder_str is component and3 is port(p,q,r : in std_logic ; m : out std_logic); end component; signal Cbar,Bbar,Abar: std_logic ; begin Abar<=not A; Bbar<=not B; Cbar<=not C; x1: and3 port map (Abar,Bbar,Cbar,D(0)); x2: and3 port map (Abar,Bbar,C,D(1)); x3: and3 port map (Abar,B,Cbar,D(2)); x4: and3 port map (Abar,B,C,D(3)); x5: and3 port map (A,Bbar,Cbar,D(4)); x6: and3 port map (A,Bbar,C,D(5)); x7: and3 port map (A,B,Cbar,D(6));
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--main program

--component AND3

WAVEFORMS OF DECODER:

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x8: and3 port map (A,B,C,D(7)); end decoder3;

RESULT: Thus the Encoder and Decoder programs have been simulated and verified in VHDL using ModelSim XE II 5.7c.

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MULTIPLIERS

Braun Multiplier :
AIM: To design 4 bit array Braun multiplier using VHDL and verify the same using Modelsim

VHDL CODE (Structural modeling) --Library declaration library ieee; use ieee.std_logic_1164.all; --Entity declaration entity braun1 is port ( a : in std_logic_vector(3 downto 0); b : in std_logic_vector(3 downto 0); p : out std_logic_vector(7 downto 0)); end braun1; --Architecture declaration Architecture arch of braun1 is signal z:std_logic_vector( 0 to 15); signal y:std_logic_vector(0 to 16); component and2 is port(a,b : in std_logic; y :out std_logic); end component; component fa is port( a,b,ci : in std_logic; s,co : out std_logic);
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39

end component; begin u0:and2 port map (a(0),b(0),z(0)); u1:and2 port map (a(1),b(0),z(1)); u2:and2 port map (a(2),b(0),z(2)); u3:and2 port map (a(3),b(0),z(3)); u4:and2 port map (a(0),b(1),z(4)); u5:and2 port map (a(1),b(1),z(5)); u6:and2 port map (a(2),b(1),z(6)); u7:and2 port map (a(3),b(1),z(7)); u8:and2 port map (a(0),b(2),z(8)); u9:and2 port map (a(1),b(2),z(9)); u10:and2 port map (a(2),b(2),z(10)); u11:and2 port map (a(3),b(2),z(11)); u12:and2 port map (a(0),b(3),z(12)); u13:and2 port map (a(1),b(3),z(13)); u14:and2 port map (a(2),b(3),z(14)); u15:and2 port map (a(3),b(3),z(15)); p(0)<=z(0); v1:fa port map(z(1),z(4),'0',p(1),y(0)); v2:fa port map(z(2),z(5),'0',y(1),y(2)); v3:fa port map(z(3),z(6),'0',y(3),y(4)); v4:fa port map(z(8),y(0),y(1),p(2),y(5)); v5:fa port map(z(9),y(2),y(3),y(6),y(7)); v6:fa port map(z(10),y(4),z(7),y(8),y(9)); v7:fa port map(z(12),y(5),y(6),p(3),y(10)); v8:fa port map(z(13),y(7),y(8),y(11),y(12));
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SIMULATED OUTPUT:

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v9:fa port map(z(11),z(14),y(9),y(13),y(14)); v10:fa port map(y(10),y(11),'0',p(4),y(15)); v11:fa port map(y(12),y(13),y(15),p(5),y(16)); v12:fa port map(y(16),y(14),z(15),p(6),p(7)); end arch;

RESULT: Thus source codes in VHDL for Braun Multiplier have been written, compiled and simulated using modelsim simulator.

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Booths Multiplier
AIM: To design 4 bit signed Booth multiplier using VHDL and verify the same using Modelsim simulator.

VHDL CODE (Behavioral modeling) --Library declaration library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --Entity declaration entity BoothMult4 is port(A, B: in std_logic_vector(3 downto 0); O: out std_logic_vector(7 downto 0)); end BoothMult4; --Architecture declaration architecture Arch of BoothMult4 is begin process(A, B) variable num: std_logic_vector(8 downto 0); variable Y, Z: unsigned(3 downto 0); variable i:integer; begin num := "000000000"; Y := unsigned(B); num(4 downto 1) := A; for i in 0 to 3 loop

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SIMULATED OUTPUT:

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if(num(1) = '1' and num(0) = '0') then Z := unsigned(num(8 downto 5)); elsif(num(1) = '0' and num(0) = '1') then Z := unsigned(num(8 downto 5)); num(8 downto 5) := std_logic_vector(Z + Y); end if; num(7 downto 0) := num(8 downto 1); end loop; O(7 downto 0) <= num(8 downto 1); end process; end Arch;

RESULT: Thus source codes in VHDL for Booths Multiplier have been written, compiled and simulated using modelsim simulator.

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