1

.
( ) Add &shift
.

1 1

( ... ) clk
( )
.
11 1 )(Bus
.
( ) ( ) .
:
.1 ) :(Dedicated Bus .
. .
n m mn ( . 1 1 ).
.2 ) :(Common Bus .
) (media .
( 1( 1) ).

.

()

()

-1-1 () ()

. 2
: . 1( 2)
. sel 0 1
sel 1 2 .
sel 0 1 .
( 1( 2) ). s 0 1
1 s 1 1 2 . s 0 s 1

1 .
) (Bus conflict .
s 0 s 1 . s 1
s 0 ) (Drive
. .

( )DMA .
.

()

()

-2-1 () ()

11 2 )(Data-Path Controller Partioning

) (Data-Path ) (Controller
.
.

112 1
( )... ( )...
.

: .

. R 0 R 3

/
(
) .
:
. /
R 0 /
R 0 R 3 . / B A
R 0 R 3 .
:

i , j0 ,1, 2 , 3

R0 R j

Ri

R 0 R3

R2

1.

R1 R 2

R3

2.

1 . R 0
R 3 .
R 2 .
2 . R 1
.

112 2

.
.
: R 2 R 0 R 3
( sel 11 : 3 R 3 )( f 1
) ( ld2 1 R 2 ).

11 3
4
. 1( 3) .
4 d in start 4 d out
done . clk clk .
1( 3) .

-3-1 4 () ()

1( 3) start (
1 clk ) .

clk multiplier multiplicand d in .

clk done 2
d out .
4 4 d out .
. 14
4 .

1. P0 8 0
. P 8
2. for i 0 to 3 do
reset ( 0) .
)2.1. if (x i 0
Y X 4
;Pi H Pi H Y
. E
2.2. Pi 1 21 Pi

-4-1 4
.
reset ( 0)

( 4

Y
P




E , P
. P

E
E . 1 5
.
.
Y X d in
-5-1
d in

E


P

.

Y P H

P L P H

E P
P E

out
d. . 4

d out .

.
P 0 . 0 X 1 .
P
0 P
.
3 , 2 , 1 .
( P ) P L
X .

-6-1

0 X 1
x 0
. 1 6 .

. 1 7
.
)) (Primary Inputs (PI
( ) d in PI
( )start -7-1

)) (Primary Outputs (PO d out
PO ( ) done
() ) (status
( ) x 0 .
.
. . 18
4 .
moore . moore
clk clk
.

-8-1

start . start
0 A X Y . 4
x 0 1 x 0 0 .
2 done 1 ( )
select d out .
(
) .
.
( sel )...
( clk
.). (
.)... clk .
. 1 9
.
.
clk .
( ) . moore
. . PO F PS :
clk
1 8 s1 . shX 1 . clk
s2 shX 0 (
.).
clk s1 Edge1

clk s1 s2 . Edge2
clk x . 1 10 clk
shx . Edgel s1
( ) ( ) shX 1
. Edge 2 s1 s2 (
) ( ) shX 0 .
Edge1 shX 0 Edge 2 shx 1 X
( Edge 2 s1 ) ( Edge1 s1
).
: (
clk) clk clk
.
: clk
.
s1
X ( ) shX ( X 0 )X .
1 8 X

-9-1

-11-1

1 2 SMPL-CPU
( )Single Cycle ( )Multi-Cycle
SMPL-CPU .
.

12 1 SMPL-CPU
. -
.
.

: SMPL-CPU SMPL-CPU 16
13 . / /
.
.

: SMPL-CPU SMPL-CPU
16 ) Accumulator (acc . .
- acc .
.
acc .

: SMPL-CPU SMPL-CPU 8192 16

. / / .

.
.

: SMPL-CPU SMPL-CPU 16
. 11-1
( )Explicit Operand ( )Implicit Operand acc . SMPL-CPU
8 : - ( AND SUB ADD
)NOT ( )STA LDA (.)JZ JMP

-11-1 SMPL-CPU

. 1-1
.
: ADD adr adr acc acc
.
: SUB adr adr acc acc
.
: AND adr adr acc and
acc.

: NOT adr adr not

acc.
: LDA adr adr acc.
: STA adr acc adr.
: JMP adr adr .
: JZ adr acc adr -
.
-1-1 SMPL-CPU

Description
]acc acc + Mem[adr
]acc acc - Mem[adr
]acc acc & Mem[adr
]acc NOT Mem[adr
]acc Mem[adr
Mem[adr] acc
Unconditional jump to adr
Conditional jump to adr

Instruction Class
Arithmetic-Logical
Arithmetic-Logical
Arithmetic-Logical
Arithmetic-Logical
Data-Transfer
Data-Transfer
Control-Flow
Control-Flow

Instruction
ADD
adr
SUB
adr
AND
adr
NOT
adr
LDA
adr
STA
adr
JMP
adr
JZ
adr

Opcode
000
001
010
011
100
101
110
111

: SMPL-CPU SMPL-CPU
. acc
.

12 2 ( )Single Cycle SMPL-CPU

122 1

.
. .

.
:1 . ( Instruction Fetch

) )(IF . .
() )Program Counter (pc .
( ) .
pc .
SMPL-CPU 8192 = 213 pc 13 . 12-1
.

-12-1

:2 - . - ( )NOT
. acc . adr
. acc .
) Arithmetic Logical Unit (alu
. - alu alu_op .
13-1 alu not and .

-13-1 -

14-1 - .
adr . .
(-)
.
acc.
:3 .
( adr 12 ) 0 .
- . 15-1 .

-14-1 -

-15-1 -

:4 . SMPL-CPU LDA :
. STA LDA adr 16
acc . STA acc adr
. LDA STA
mem_write mem_read
. write Clk
. acc acc_write (
LDA acc STA) . 16-1
.

-16-1

:5 .
. ( 3 )15-1 alu acc 4
( )16-1 ReadData acc .
acc . acc_src 0
alu acc_src 1 .
17-1 .

-17-1 -

:6 . SMPL-CPU
JMP : JZ . JMP
( 12 )0 pc . JZ acc (-

12 )0 pc . ( 12 )0 pc .
18-1 . acc NOR
acc . JZ .

-18-1

:7 . 6
. ( 6 5 )17-1 16-1
. pc . 1
( pc 1 ) 6 .
acc 5
pc . pc_src 0
pc 1 . 19-1
.
. ADD 100
SMPL-CPU . Clk pc
ADD 100 .
.
.
Clk alu acc
pc+1 pc . pc .
.

122 2
( 15 )13
. .
.
20-1 SMPL-CPU .
pc_src
. JZ JPM jmp_uncond

jmp_cond 0 . Jump Logic pc_src 0

pc . JMP jmp_uncond 1 pc_src 1
pc . JZ jmp_cond 1 acc
0 ( ) acc_zero 1 pc_src 1
pc . JZ ( acc_zero 0
) pc+1 pc .
.
.
SMPL-CPU 2-1 .
.

-19-1 SMPL-CPU

-:
o
o
o
o
o

mem_read=1
acc_write=1 alu acc
- ( )NEG AND SUB ADD alu_op 00
11 10 01.
acc_src=0 alu acc
jmp_uncond=0 jmp_cond=0 pc+1 pc


SMPL-CPU -2-1
Instruction
Class
Arithmetic
Logical
Data
Transfer
Control
Flow

Inst

Opcode

ADD
SUB
AND
NOT
LDA
STA
JMP
JZ

000
001
010
011
100
101
110
111

mem
read
1
1
1
1
1
0
0
0

mem
write
0
0
0
0
0
1
0
0

acc
write
1
1
1
1
1
0
0
0

acc
src
0
0
0
0
1
X
X
X

alu
op
00
01
10
11
XX
XX
XX
XX

jmp
uncond
0
0
0
0
0
0
1
0

Jmp
cond
0
0
0
0
0
0
0
1

-21-1

:
LDA

mem_read=1
acc acc_write=1
. alu alu_op=xx
acc acc_src=1

STA

jmp_uncond=0 jmp_cond=0 pc+1 pc

mem_write=1
acc_write=0 acc
alu_op=xx alu .
acc_src=x acc
.
jmp_uncond=0 jmp_cond=0 pc+1 pc

:
o

JMP

mem_write mem_read 0
.
acc_write=0 acc .
alu_op=xx alu .
acc_src=x acc
.
jmp_uncond=1 jmp_cond=0 pc_src=1
( 12 )0 pc .

JZ

mem_write mem_read 0
.
acc_write=0 acc .
alu_op=xx alu .
acc_src=x acc
.
jmp_uncond=0 jmp_cond=1 acc_zero=1 pc_src=1
( 12 )0 pc
acc_zero=0 pc_src=0 pc+1
pc .

12 3 ( )Multi-Cycle SMPL-CPU
SMPL-CPU ( alu ) -
. . -
SMPL-CPU .
.

123 1

alu .

.
pc
( 12 )0 .
alu alu . alu pc
acc alu 1 . alu 16
3 0 pc alu .
) instruction register (ir . -1
21 .
. .

( :)IF pc .
pc
ir . pc alu 1 alu
pc.

( :)ID ( ir )
.

( :)EX .
o

- : 12 0 ir
. acc alu
alu - ( and not)
alu acc.

: 12 0 ir . LDA

acc .
STA acc .
o

: JMP 12 0 ir pc
. JZ acc 12 0 ir pc
.

123 2
SMPL-CPU .
. -
.

22-1 .
pc_write
.

-21-1 SMPL-CPU

23-1 SMPL-CPU ( Moore State

)Machine .
. : Clk
.
0 . pc
( )i_or_d=0 ( )mem_read=1 ir pc
( .)src_a=0, src_b=1, aluop=00, pc_src=1, pc_write_cond=1 ( 1 )

. :

- : 12 0 ir ()i_or_d=1
( )mem_read=1 acc alu
( )src_a=1, src_b=0 - alu ( ] )alu_op=ir[14-13
alu acc ( )acc_src=0 alu acc
( .)acc_write=1 - ( 0 )
.

-22-1

-23-1 SMPL-CPU

:LDA 12 0 ir ( )i_or_d=1
( )mem_read=1 acc ( )acc_src=1
acc ( .)acc_write=1 LDA
( 0 ) .

:STA 12 0 ir ( )i_or_d=1
acc ( .)mem_write=1 STA
( 0 ) .

:JMP 12 0 ir pc (.)pc_src=0, pc_write_uncond=1

JMP ( 0 )
.

:JZ acc 12 0 ir pc
( .)pc_src=0, pc_write_cond=1 JZ ( 0 )
.