TLS2118 TW-201471394521383

: TLS2118
Microchip PIC18 MCU

C18
TLS2118
z
z
z
z
z
z
z
z
MPLAB C18
I/O
: MPLAB C
PIC18F
Configuration Bits
: I/O
Interrupts
Timers
: Timer1
10-bit ADC
: ADC
:
PIC18F Family
C18 Memory Models
2011 Microchip Technology Incorporated. All Rights Reserved.
TLS2118
Slide
Microchip
TLS2118
z
MPLAB IDE v8.70 ()

MPLAB C18 v3.38 Lite Mode ()
MPASM , MPLINK , MPLIB
MPLAB ICD 3
Microchip APP001 Rev. 3 (PIC18F4520)
MPLAB C18 Compiler Users Guide & Library

MPASM Users Guide with MPLINK and MPLIB
MPLAB IDE Users Guide
APP001 Vre. 3
TLS2118
Slide

Download the
MPLAB IDE (Free)
Select a Debugger/
Programmer
Free
Free
Select Your
C Compiler
Free
Free
MPLAB C Compilers
Lite & Standard Versions
Support for PIC18, PIC24,
dsPIC & PIC32
+
Free
Free
Lite
STD
Support
for all
PIC
MCUs
PRO
TLS2118
Slide

MPLAB
IDE and
Components
MPLAB
Integrated Development Environment

Programmers
Editor
Software
Simulators
MPLAB C
Compilers
MPLAB
SIM
MPLAB
MPLAB
Simulator
HI-TECH C
Compilers
Source Level
Debugger
Project
Manager
HW Debuggers
Programmers
Plug-ins
MPLAB PM3
Application
Segment
MPLAB
REAL ICE
SIM
SIM
Third Party
MPLAB ICD
Data
Monitor
& Control
Interface
PICkit
Compilers,
RTOS,
Software Tools
Version
Control
RTOS
Viewer
Proteus
SPICE
MPLAB Starter Kits
PC Lint
MATLAB
Emulators and
Debuggers
TLS2118
Production, Gang,
Hobbyist
Programmers
Many
others
Slide
PICkit 3
Debugger/Programmer Probe
z
z
z
z
z
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Full-speed real-time emulation with run/halt, step

and breakpoints
Firmware upgradable via the free MPLAB IDE
USB 2.0 Full Speed communications for fast
downloads
USB powered with target
power, up to 30mA
VDD range 3 - 5.5V
VPP range 3 - 13V
CE and RoHS-compliant
TLS2118
Slide
MPLAB ICD 3
New In-Circuit Debugger
z
z
Full PIC portfolio support

Many other Improvements
z
z
z
z
z
Can provide limited target power (100mA)

Fast USB HS, HW accelerator, SRAM
SW breakpoints (1000)
Completely USB powered

No external power supply
required
High Voltage protection on ICSP
Over Current Protection
Test Interface Module
DV164035
$219.99
Validate interface and connection integrity

Helps isolate target faults vs. tool issues
Test module includes small PIC
TLS2118
Slide
MPLAB REAL ICE Probe Kit

z
MPLAB IDE compatible
Standard Driver Board
Complex Breakpoints
Real Time Data Watchpoints
Stack/WDT/Sleep Breakpoints
USB High Speed Connection
DV244005
MPLAB REAL ICE List $499.98
TLS2118
Slide
Feature
PICkit 2
ICD 2
PICkit 3
ICD 3
REAL ICE
USB Speed
Full
Full
Full
High and Full
High and Full
USB Driver
HID
Custom
HID
Custom
Custom
USB powered
Yes
Yes
Yes
Yes
Yes
External power supply required
No
Yes
No
No
No
Programmable VPP Range
(3-13V)
( 10-14V)
(2-14v)
(2-14V)
(2-14V)
VPP Current Supplied
30ma
30ma
30ma
100ma
100ma
Power to Target
Yes
5V only
Yes
Yes
No
Programmable VDD
3 -5V
No
2-5V
2-5V
2-5V internal
VDD Current Supplied
30ma
200ma
30ma
100ma
100ma
VDD drain from target
20ma
20ma
20ma
<1ma
<1ma
Over voltage Protection
No
Yes
Yes
Yes
Yes
Over current Protection
Yes
Yes
Yes
Yes
Yes
Emulation Support
Full Speed
Full Speed
Full Speed
Full Speed
Full Speed
Software Breakpoints
No
No
No
Yes
Yes
Program Image
128K bytes
No
512K bytes
No
No
TLS2118
Slide
10
Selection criteria / Recomm. tool
Advantage / comment
Debug capability
Can program all PICs & dsPICs
Fast Project Development
Pickit2
Pickit3
limited
limited
ICD2
ICD3
REAL-ICE
adap. Need
Faster daily debug / programming
Tool cost
PIC10/12/16 (except PIC16E)
PIC16 Enhanced
Need Vpp = 8.5V
PIC18 std (non J, non K)

PIC18FxxJxx
PIC18FxxKxx
Need Vpp = 8.5V
PIC18 fast programming
max 15s up to 128KB
16 bits fast programming
max 15s up to 256KB
32 bits fast programming
max 15s up to 512KB
Programmer-To-Go
Standalone programming
Real-Time variables watch
PIC18J, 16/32 bits except dsPIC30
Real-Time measurement of program

execution time (STOPWATCH)
PIC18, 16/32 bits except dsPIC30
SW breakpoints
PIC18, 16/32 bits except dsPIC30
Real-Time Data Monitoring (RTDM)
dsPIC30/dsPIC33 PIC24H
TRACE (Instructions)
PIC32 only
TRACE (Ports / SPI)
PIC18, 16 bits (not PIC32)
External breakpoint Trigger
For all PICs
TLS2118
Slide
11
APP001 V3a
TLS2118
Slide
12
APP001
z
APP001
Microchip :
http://www.microchip.com.tw/Taiwan_
CAE/EVM_Pages/Index1.htm
APP001 v1.0,
v2.0 v3.0
TLS2118
Slide
13
APP001 REV.3a
RS-232
9V
CAN
RS-485
AD Reset ICD3

VR1
PICkit3
Debug & Prog.

Jumper
5V & 3.3V
Jumper
I2C & SPI

EEPROM
9V & USB
PIC18F4520
5V
CCP2
PWM LED
ICSP
CCP1
2 x 16 LCD
USB
PORTD
LED x8
16MHz
Crystal
TLS2118
SW3 & SW2

Slide
14
MPLAB C18
MPLAB C18
z
z
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z
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ANSI x3.159-1989 C
PIC18
MPLAB IDE
MPASM MPLINK
MPLAB C for PIC18 Lite /Evaluation
Microchip
TLS2118
Slide
16
C18
C Compiler
C Source Files
(and Preprocessor)
Compiler
Driver
Program
Assembly Source Files
MPASM
Assembly Source Files
C Header Files
(Assembler)
Object
Files
MPLIB
(Librarian)
Assembly Include Files
MPLINK
Object File Libraries
(Linker)
MPLAB IDE
Linker Script
COFF
Debug File
TLS2118
Slide
17

MPLAB
C for PIC18
(Header Files)
Program Files
microchip
mplabc18
V3.38
h
p18cxxx.h
p18f4520.h
Header files MPLAB C18

:
p18cxxx.h
p18cxxx.h
MPLAB IDE
( p18f4520.h )
:

C
TLS2118
Slide
18
p18f4520.h
z
extern near unsigned char ADCON0;

extern near union {
struct {
unsigned ADON:1;
unsigned :1;
:C:\Program Files
unsigned GO:1;
\Microchip\mplabc18\v3.38\h
unsigned CHS0:1;
unsigned CHS1:1;
unsigned CHS2:1;
unsigned ADCS0:1;
Nop( )
extern ?
unsigned ADCS1:1;
ClrWdt( )
} ;
struct {
Sleep( )
unsigned :2;
unsigned NOT_DONE:1;
} ;
struct {
unsigned :2;
unsigned DONE:1;
} ;
struct {
unsigned :2;
unsigned GO_DONE:1;
} ;
} ADCON0bits ;
ADCON0
18F4520
(SFR)
#include
<p18fxxx.h>
P18fxxx.h
MPLAB IDE
TLS2118
Slide
19
C18
( p18f4520.h )
z
(Header file)
: PIC18F4520 p18f4520.h
Data Book
bits
PORTD
1.1. PORTD
0x55
0x5516
16
PORTD
PORTD
PORTD
PORTD
bit3
bit3&
&bit5
bit5
2.2.
11
PORTDbits.RD3==11;;
PORTDbits.RD3
PORTDbits.RD5==11;;
PORTDbits.RD5
TRISD==00;;
TRISD
PORTD==0x55
0x55;;
PORTD
TLS2118
Slide
20

MPLAB
C for PIC18
(Linker Scripts)
Program Files
microchip
mplabc18
V3.38
Bin
LKR
Linker Script files are included as part of the

MPLAB installation :
g
p18f4520_g.lkr
p18f4520_g.lkr
:

debug release
MPLAB IDE
TLS2118
Slide
21
18f4520_g.lkr
LIBPATH
FILES c018i.o
FILES clib.lib
FILES p18f4520.lib
#IFDEF _DEBUGCODESTART
CODEPAGE NAME=page
START=0x0
END=_CODEEND
CODEPAGE NAME=debug
START=_DEBUGCODESTART END=_CEND
#ELSE
CODEPAGE NAME=page
START=0x0
END=0x7FFF
#FI
CODEPAGE
CODEPAGE
CODEPAGE
CODEPAGE
NAME=idlocs
NAME=config
NAME=devid
NAME=eedata
START=0x200000
START=0x300000
START=0x3FFFFE
START=0xF00000
END=0x200007
END=0x30000D
END=0x3FFFFF
END=0xF000FF
ACCESSBANK NAME=accessram START=0x0

#FI
DATABANK
DATABANK
DATABANK
DATABANK
DATABANK
NAME=gpr0
NAME=gpr1
NAME=gpr2
NAME=gpr3
NAME=gpr4
START=0x80
START=0x100
START=0x200
START=0x300
START=0x400
PROTECTED
PROTECTED
PROTECTED
PROTECTED
END=0x7F
END=0xFF
END=0x1FF
END=0x2FF
END=0x3FF
END=0x4FF
#IFDEF _DEBUGDATASTART
DATABANK NAME=gpr5
START=0x500
END=_DATAEND
DATABANK NAME=dbgspr START=_DEBUGDATASTART END=_DEND
#ELSE //no debug
DATABANK NAME=gpr5
START=0x500
END=0x5FF
#FI
ACCESSBANK NAME=accesssfr START=0xF80
PROTECTED
END=0xFFF
PROTECTED
PROTECTED
#IFDEF _DEBUGDATASTART
STACK SIZE=0x100 RAM=gpr4
#ELSE
STACK SIZE=0x100 RAM=gpr5
TLS2118
Slide
22
C Linker
Section Type
Default Name
Purpose
code
.code_filename
romdata
.romdata_filename
udata
.udata_filename
idata
.idata_filename
stack (udata)
.stack
z
z
Linker (*.o)
TLS2118
Slide
23

MPLAB
C for PIC18
Program Memory
goto
_startup
_startup:
... ...
... ...
call _main
Reset Vector (Address 0x000000)

MPLINK
c018i.o ( _startup label)
c018i.o ()
C
main( ) ( : c018*.c)
_main:
...
...
...
...
...
...
...
...
main.c
main( ) Linker
TLS2118
Slide
24
lkr
// File: 18f4520i.lkr
// Sample ICD2 linker script
LIBPATH .
FILES
FILES
FILES
FILES
PIC18F
c018i.o idata & udata
c018iz.o idata & zeroed udata
c018.o
udata only
c018i.o
TLS2118.lib
clib.lib
p18f4520.lib
CODEPAGE
CODEPAGE
CODEPAGE
CODEPAGE
CODEPAGE
CODEPAGE
NAME=page
NAME=debug
NAME=idlocs
NAME=config
NAME=devid
NAME=eedata
START=0x0
START=0x7D
START=0x20
START=0x30
START=0x3F
START=0xF0
TLS2118
PIC18F
c018i_e.o idata & udata
c018iz_e.o idata & zeroed udata
c018_e.o udata only
Slide
25
c018i.c
#pragma code _entry_scn = 0x000000
static void
entry (void)
{ _asm goto _startup _endasm }
RESET :
0x000000
#pragma code _startup_scn

static void _startup (void)
{
_asm
// Initialize the stack pointer
LFSR 1, _stack LFSR 2, _stack CLRF TBLPTRU, 0
// Initialize rounding flag for floating point libs
BSF FPFLAGS,RND,0
_endasm
STACK
TBLPTRU
_do_cinit ( );
loop:
// Call the user's main routine
main ( );
goto loop;
}
/* end _startup() */
main( )
TLS2118
Slide
26
p18f4520.lib
18F4520 (SFR)
p18F4520.asm obj p18f4520.lib
C:\Program Files\Microchip\mplabc18\v3.38\src\traditional\proc
p18f4520.lib
obj
p18f4520.lib
MPLAB C18 Reference Manual
A/D , USART , Timer x , EEPROM
C:\Program Files\Microchip\mplabc18
\v3.38\src\pmc_common
TLS2118
Slide
27
PIC18F4520
p18f4520.o (asm)

C18
LIST P=18F4520
NOLIST
;---------------------------------------------------; MPLAB-Cxx PIC18F4520 processor definition module
;
; (c) Copyright 1999-2007 Microchip Technology,
;----------------------------------------------------SFR_UNBANKED0
p18f4520.h

p18f4520.inc

PORTA
PORTAbits
PORTB
PORTBbits
PORTC
PORTCbits
PORTD
PORTDbits
PORTE
PORTEbits
LATA
LATAbits
LATB
LATBbits
LATC
LATCbits
LATD
LATDbits
LATE
LATEbits
TLS2118
UDATA_ACS H'F80'
RES 1
; 0xF80
RES 1
; 0xF81
RES 1
; 0xF82
RES 1
; 0xF83
RES 1
RES 4
; 0xF84
RES 1
; 0xF89
RES 1
; 0xF8A
RES 1
; 0xF8B
RES 1
; 0xF8C
RES 1
; 0xF8D
Slide
28
PIC18 Family
- I/O
I/O Ports
z
High Drive Capability
Can directly drive LEDs
Direct, single cycle

bit manipulation
Each pin has individual

direction control under software
All pins have ESD protection diodes
Pin RA4 is usually open drain
I/O ()
I/O
: I/O ( AD )
TLS2118
Slide
30
I/O Ports
z
z
TRISx Bit n
PORTx n
1 = Input, 0 = Output
TLS2118
Slide
31
Digital I/O Ports PIC18
::PORTx
PORTx
LATx
LATx
??
TLS2118
Slide
32
LATx
Read-Modify-Write
BSF PORTx,PINy
Q4
V on PORTx,PINy
BSF PORTx,PINz
Q1
Q2
Q3
I/O
VIL
t
High Level
BSF PORTx,PINy BSF PORTx,PINz
Q4 Q1 Q2 Q3 Q4
V on PORTx,PINy
I/O
VIL
t
High Level!
TLS2118
Slide
33
Analog or Digital I/O?

z
I/O
(Power On analog mode)
Digital
I/O Digital mode !
PIC18F4520 , ADCON1
.
Set lower 4 bits to 1 to make all multiplexed pins digital
TLS2118
Slide
34
I/O Ports
Summary
z PIC18 Family I/O

zTRISx
z I/O port
zPORTx
z I/O port /
zLATx
z I/O port
TLS2118
Slide
35
Lab Exercise 1
MPLAB IDE
MPLAB C
Lab Exercise 1
MPLAB C18
MPLAB C18 C18

Hello, TLS2118!
APP001 Demo Board LCD.
Hello, TLS2118
MPLAB C18
TLS2118
Slide
37
Lab Exercise 1
MPLAB C18
MPLAB IDE Project

:
Project ` Project Wizard
After the Project Wizard opens,
Click
Next >
to continue
TLS2118
Slide
38
Lab Exercise 1
MPLAB C18
PIC18F4520
Click
Next >
to continue
TLS2118
Slide
39
Lab Exercise 1
MPLAB C18
(Toolsuite) :
Microchip C18 Toolsuite
Click
Next >
to continue
TLS2118
Slide
40
Lab Exercise 1
MPLAB C18
Browse
C:\RTC\TLS2118\Lab1
Lab1.mcp
Create New Project File

C:\RTC\TLS2118\Lab1\Lab1
Click
Next >
to continue
TLS2118
Slide
41
Lab Exercise 1
MPLAB C18
C:\RTC\TLS2118\Lab1
Lab1.c
Add >>
Library :
C:\RTC\TLS2118\TLS2118_LIB
TLS2118.lib
Click
Add >>
TLS2118
Slide
42
Lab Exercise 1
MPLAB C18
MPLAB
( LKR )

MPLAB
Linker Script ( : p18f4520_g.lkr)
TLS2118
Slide
43
Lab Exercise 1
MPLAB C18
( )
#IFDEF _DEBUGCODESTART
CODEPAGE NAME=page
START=0x0
CODEPAGE NAME=debug
START=_DEBUGCODESTART
#ELSE
CODEPAGE NAME=page
START=0x0
#FI
CODEPAGE NAME=idlocs
START=0x200000
CODEPAGE NAME=config
START=0x300000
CODEPAGE NAME=devid
START=0x3FFFFE
CODEPAGE NAME=eedata
START=0xF00000
#IFDEF _EXTENDEDMODE
DATABANK NAME=gpre
START=0x0
ACCESSBANK NAME=accessram
START=0x60
#ELSE
ACCESSBANK NAME=accessram
START=0x0
#FI
DATABANK NAME=gpr0
START=0x80
DATABANK NAME=gpr1
START=0x100
TLS2118
END=_CODEEND
END=_CEND
PROTECTED
END=0x7FFF
END=0x200007
END=0x30000D
END=0x3FFFFF
END=0xF000FF
PROTECTED
PROTECTED
PROTECTED
PROTECTED
END=0x5F
END=0x7F
END=0x7F
END=0xFF
END=0x1FF
Slide
44
Lab Exercise 1
MPLAB C18
Finish
View ` Project
Lab 1 Project Tree
PIC18F4520
TLS2118
Slide
45
Lab Exercise 1
MPLAB C18
Project ` Build Options ` Project

:
TLS2118
Slide
46
Lab Exercise 1
MPLAB C18
Directories
:
C:\RTC\TLS2118\
Project :
C:\RTC\TLS2118\lab1\lab1.mcp
TLS2118
Slide
47
Lab Exercise 1
MPLAB C18
C18 v3.37
c:\mcc18\
C:\Program Files\
Include
Select Include Search Path

from the combo box
Click on New
: ..\Microchip\
mplabc18\v3.38\h (Default )
C:\RTC\TLS2118 ()
TLS2118
TLS2118
Slide
48
Header ?
1.
2.
3.
#include <p18cxxx.h>
#include TLS2118_LIB/P18F_LCD.h
#include P18F_LCD.H
< xxxx.h> :
..\Microchip\mplabc18\v3.38\h Header File
xxxxxx/xxxxx.h
Project
xxxx.h
Project
TLS2118
Slide
49
Lab Exercise 1
MPLAB C18
C18 v3.37
c:\mcc18\
C:\Program Files\
Library
Select Library Search Path from

the combo box
Click on New
:
..\Microchip\mplabc18\v3.38\lib
C:\RTC\TLS2118\TLS2118_LIB
c 0 1 8 i . o ?

Click
OK
when finished.
TLS2118
TLS2118_LIB
Slide
50
Lab Exercise 1
MPLAB C18
Lab1.c
project , Double click Lab1.c
#include .
z ()
z C Microchip (if used)
z (if used)
Lab1.c
13
14
15
#include <p18fcxxx.h>
#include "TLS2118_LIB/P18F_LCD.h"
TLS2118
project options
Slide
51
Lab Exercise 1
MPLAB C18
Lab1.c
configuration bits
z
#pragma config
help file device ,
hlpPIC18ConfigSet.chm
Lab1.c
17
C18 Lite extend instruction
#pragma config OSC=INTIO7, WDT=OFF, BOREN = ON, BORV = 1, LVP=OFF,

PBADEN=OFF, XINST = OFF, MCLRE = ON
TLS2118
Slide
52
Lab Exercise 1
MPLAB C18
:
Debugger ` Select Tool `
:
MPLAB PICkit 3
MPLAB ICD 3
REAL ICE
MPLAB SIM
APP001
Debugger
Select Tool
Clear Memory
None
1 MPLAB ICD 2
2 PICkit 3
3 MPLAB ICE 4000
4 MPLAB SIM
5 MPLAB ICE 2000
6 REAL ICE
7 PICkit 2
8 MPLAB ICD 3
9 PIC32 Starter Kit
10 Starter Kits
DO NOT enable tool from

the Programmer menu.
TLS2118
Slide
53
Lab Exercise 1
MPLAB C18
Debug
Select Debug mode.
When programming
completes,click
Reset button.
Click Build All button.
Click Run button.
If no errors reported,
Click Program
button.
Click Halt button.
TLS2118
Slide
54
Exercise 1
z
LCD
Hello,TLS2118!
D1 LED !
TLS2118
Slide
55
LIB
LCD
(TLS2118.LIB)
Library Exercise
Lab1 Review
Library functions LCD

z Library file project file
z
z
z
Library header file:

P18F_LCD.h
Lab1 function OpenLCD( ) putrsLCD( )
TLS2118.lib function
void
void
void
void
void
void
OpenLCD (void) ;
putsLCD( char * ) ;
putrsLCD( const rom far char * ) ;
putcLCD( unsigned char ) ;
puthexLCD( unsigned char ) ;
LCD_Set_Cursor( unsigned char , unsigned char ) ;
TLS2118
Slide
57
LIB
z
Project C
Project
obj
Linker
Linker
Library
TLS2118
Slide
58
LIB
z
Project Build
Options Project
Library Output
Build
Library Target
Build All
TLS2118.LIB
TLS2118
Slide
59
PIC18 Family
Special Features
PIC18 Oscillator Options
XT
XT
HS
HS
Standard
Standard frequency
frequency crystal
crystal oscillator
oscillator
High
High frequency
frequency crystal
crystal oscillator
oscillator
100kHz
100kHz -- 4MHz
4MHz
DC
DC -- 40MHz
40MHz
HS+PLL
HS+PLL
LP
LP
High
High frequency
frequency crystal
crystal with
with 4x
4x PLL
PLL
Low
Low frequency
frequency crystal
crystal oscillator
oscillator
4MHz
4MHz -- 10MHz
10MHz
5kHz
5kHz -- 200kHz
200kHz
RC
RC
RCIO
RCIO
External
External RC
RC oscillator
oscillator
External
External RC
RC oscillator,
oscillator, OSC2=RA6
OSC2=RA6
DC
DC -- 4MHz
4MHz
DC
DC -- 4MHz
4MHz
INTRC
INTRC
EC
EC
Internal
Internal RC
RC oscillator
oscillator
External
/4
External Clock,
Clock, OSC2=f
OSC2=fosc
osc/4
Various
Various
DC
DC -- 40MHz
40MHz
ECIO
ECIO
External
External Clock,
Clock, OSC2=RA6
OSC2=RA6
DC
DC -- 40MHz
40MHz
Selectable clock options provide greater flexibility for

the designer:
LP Oscillator designed to draw least amount of current

RC or INTRC provide ultra low cost oscillator solution
XT optimized for most commonly used oscillator frequencies
HS optimized to drive high frequency crystals or resonators
Speed ranges are guidelines only
TLS2118
Slide
61
POR, OST, PWRT

z
POR: Power On Reset
PWRT: Power Up Timer
With MCLR tied to VDD, a reset

pulse is generated when VDD
rise is detected
Device is held in reset for 72ms
(nominal) to allow VDD to rise to
an acceptable level (after POR
only)
OST: Oscillator Start-up Timer
Holds device in reset for 1024

cycles to allow crystal or
resonator to stabilize in
frequency and amplitude; not
active in RC modes; used only
after POR or Wake Up from
SLEEP
TLS2118
Slide
62
Sleep Mode
z
The processor can be put into a power-down

mode by executing the SLEEP instruction
System oscillator is stopped

Processor status is maintained (static design)
Watchdog timer continues to run, if enabled
Minimal supply current is drawn - mostly due to leakage (0.1 2.0A typical) , XLP device is much lower than std. device
Sleep
Sleep Mode
Mode
CPU
CPU
MCLR
MCLR
WDT
WDT
Master
Master Clear
Clear Pin
Pin Asserted
Asserted (pulled
(pulled low)
low)
Watchdog
Watchdog Timer
Timer Timeout
Timeout
INT
INT
TMR1
TMR1
INT
INT Pin
Pin Interrupt
Interrupt
Timer
Timer 11 Interrupt
Interrupt (or
(or also
also TMR3
TMR3 on
on PIC18)
PIC18)
ADC
ADC
CMP
CMP
A/D
A/D Conversion
Conversion Complete
Complete Interrupt
Interrupt
Comparator
Comparator Output
Output Change
Change Interrupt
Interrupt
CCP
Input
CCP
Input Capture
Capture Event
Event
PORTB
PORTB PORTB
PORTB Interrupt
Interrupt on
on Change
Change
SSP
Synchronous
SSP
Synchronous Serial
Serial Port
Port (I(I22C
C Mode)
Mode) Start
Start // Stop
Stop Bit
Bit Detect
Detect Interrupt
Interrupt
PSP
PSP
Parallel
Parallel Slave
Slave Port
Port Read
Read or
or Write
Write
TLS2118
Slide
63
Watchdog Timer
z
z
z
z
z
z
z
Helps recover from software malfunction

Uses its own free-running on-chip RC oscillator
WDT is cleared by CLRWDT instruction
Enabled WDT (WDTEN) cannot be disabled by software
WDT overflow resets the chip
Programmable timeout period: 18ms to 3.0s typical
Operates in SLEEP; on time out, wakes up CPU
TLS2118
Slide
64
In-Circuit Serial
Programming
Vpp(MCLR)
PIC18
device
Function
Function
Programming
Programming Voltage
Voltage == 13V
13V
Supply
Supply Voltage
Voltage
Ground
Ground
Clock
Clock Input
Input
Data
Data I/O
I/O &
& Command
Command Input
Input
In-System Programming
ICSP Data
ICSP Clock
Pin
Pin
V
VPP
PP
V
VDD
DD
V
VSS
SS
RB6
RB6
RB7
RB7
Calibration Data
Serialization Data
Application PCB
MPLAB ICD3 PICKit 3 Real

ICE /
PIC18 device
VDD
VDD
ICSP Connector
MCLR/VPP
PIC18Fxxxx
ICSP Connector
VDD
VSS
RB6
RB7
To application circuit
TLS2118
Isolation
circuits
Slide
65
BOR Brown Out Reset

z
BOR
: BOR
TLS2118
Slide
66
PBOR
Programmable Brown Out Reset
z
Configuration ( IC )
enabled / disabled (XLP
BOR Sleep Mode )
BVDD : ( device
)
2.5V
2.7V
4.2V
4.5V
device ,
supervisor (MCP1xx, MCP8xx/TCM8xx, or TC12xx)
TLS2118
Slide
67
PBOR Programmable
Brown Out Reset
z
Holds PICmicro MCU in reset until ~72ms after VDD rises back above
threshold
TLS2118
Slide
68
PLVD Programmable Low

Voltage Detect
brown out
device
16 selectable trip
points:
LVDCON
16-bit Multiplexer
VDD LVDIN
1.8V up to 4.5V in
0.1 to 0.2V steps
External analog
input
z
Internal VREF
LVDIF
VREF
LVDIN
LVDIN
TLS2118
Slide
69
PIC18F
Configuration Bits
Configuration Bits?
z
:
Code Protect
Watchdog Timer
Oscillator Options
Debug Options
More
CONFIG
( @ 0x300001 )
TLS2118
16-bit Program Memory

Reset Vector
High Interrupt Vector
Low Interrupt Vector
User Flash
Data EEPROM
Configurations Registers
Device ID
Slide
71
Configuration Bits
PIC18F4520 Registers (4 of 11)
CONFIG1H Register
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IESO
FCMEN
FOSC3
FOSC2
FOSC1
FOSC0
bit 7
bit 0
CONFIG2L Register
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BORV1
BORV0
BOREN1
BOREN0
PWRTEN
bit 7
bit 0
CONFIG2H Register
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WDTPS3
WDTPS2
WDTPS1
WDTPS0
WDTEN
bit 7
bit 0
CONFIG3H Register
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MCLRE
LPT1OSC
PBADEN
CCP2MX
bit 7
bit 0
TLS2118
Slide
72

Configuration Bits
Syntax
#pragma config setting-list

z
Config
Program Files
microchip
mplabc18
Values for the setting list are defined in the

PIC18 Config Set help file.
V3.38
doc
#pragma config OSC = INTIO67, WDT = OFF, BOREN = OFF

TLS2118
Slide
73
Configuration Bits
TLS2118
Slide
74
How to Set Configuration Bits

PIC18F4520 (Part 1)
Feature Symbol
Description
OSC
Oscillator Selection
FCMEN
IESO
PWRT
BOREN
BORV
WDT
Fail-Safe Clock Monitor Enable

Internal/External Oscillator Switchover
Power Up Timer Enable
Brown Out Reset Enable
Brown Out Reset Voltage
Watchdog Timer Enable
WDTPS
Watchdog Timer Postscale Select
MCLRE
LPT1OSC
PBADEN
CCP2MX
STVREN
LVP
XINST
DEBUG
CPn
CPB
WRTn
WRTB
MCLR Pin Enable

Low Power TMR1 Oscillator Enable
PORTB A/D Input Enable
CCP2 Mux
Stack Overflow/Underflow Reset Enable
Single Supply ICSP Enable
Extended Instruction Set Enable
Background Debugger Enable
Code Protection Enable Block n (n = 0-3)
Boot Block Code Protection Enable
Write Protection Enable Block n (n = 0-3)
Boot Block Write Protection Enable
Setting Options
LP,XT,HS,RC,EC,ECIO6,
HSPLL,RCIO6,INTIO67,INTIO7
ON,OFF
ON,OFF
ON,OFF
ON,OFF,NOSLP,SBORDIS
0,1,2,3
ON,OFF
1,2,4,8,16,32,64,128,256,512,
1024,2048,4096,8192,16384,32768
ON,OFF
ON,OFF
ON,OFF
PORTBE,PORTC
ON,OFF
ON,OFF
ON,OFF
ON,OFF
ON,OFF
ON,OFF
ON,OFF
ON,OFF
TLS2118
Slide
75
How to Set Configuration Bits

PIC18F4520 (Part 2)
Feature Symbol
Description
Setting Options
WRTC
WRTD
EBTRn
EBTRB
Configuration Register Write Protection
ON,OFF
ON,OFF
ON,OFF
ON,OFF
z
z
z
z
Data EEPROM Write Protection

Table Read Protection Block n (n = 0-3)
Boot Block Table Read Protection Enable
Watch-Dog Timer
Debug/Release
Config. Debug Bit
hlpPIC18ConfigSet.chm PIC18F
MPLAB C18
Data Sheet configuration
TLS2118
Slide
76
TLS2118
Configuration Bits
z
TLS2118
Configuration Bits
#pragma config OSC=INTIO7, WDT=OFF, BOREN = ON,
BORV = 1, LVP=OFF, PBADEN=OFF, XINST = OFF,
MCLRE = ON
:
: WDT LVP
MCLRE ON MCLR Pin Reset
C18 Lite Extended Instruction

Sets
TLS2118
Slide
77

MPLAB
C for PIC18
Byte little
endian :
LSB
MSB
0x4321 @ 0x100 (RAM)
7
0x0FF
0x100
0x101
21
43
0x102
TLS2118
Slide
79

MPLAB
C for PIC18
Type
Bits
Min
Max
char, signed char
-128
127
unsigned char
255
short, signed short
16
-32768
32767
unsigned short
16
65535
int, signed int
16
-32768
32767
unsigned int
16
65535
short long, signed short long
24
-8,388,608
8,388,607
unsigned short long
24
16,777,215
long, signed long
32
-231
231 - 1
unsigned long
32
232 - 1
TLS2118
Slide
80

MPLAB
C for PIC18
MPLAB C18 IEEE 754
TLS2118
Slide
81

MPLAB
C for PIC18
E = Exponent
N = Normalized
z
z
z
double float
C18 64-bit double
C30 64-bit double
TLS2118
Slide
82

MPLAB
C for PIC18
z
z
z
data memory Table Read

program memory
memory model
near far
far
near
(rom)
(ram)
2M bytes
(24-bit
<64K bytes
(16-bit
4K bytes
(16-bit
Access RAM
(8-bit
TLS2118
Slide
83
(byte)
char
Data Sheet
Example
PORTB = 0x31;
AtoD_Result = ADRESH;
TXREG = 'a';
if (RXREG == 'x') { }
while (RXREG) { }
//
//
//
//
//
TLS2118
Write 0x31 to PORTB

Read A/D Result (High)
Send 'a' out UART
If received char is 'x'
While char is not '\0'
Slide
84

PIC18F4520
PORTA Variable Declaration from p18f4520.h Header File
extern volatile near unsigned char PORTA;
z
z
extern: PORTA
p18f4520.o
volatile:
(:
)
near: Access RAM
Bank
TLS2118
Slide
85

RAM Location)
z
Access Bank
#pragma {udata/idata}
RAM
#pragma udata [data-qualifier] [section-name [=address]]
#pragma idata [data-qualifier] [section-name [=address]]
#pragma udata/idata
#pragma udata/idata
TLS2118
Slide
86
#pragma udata
z
Option
#pragma udata [data-qualifier] [section-name [= addr]]

#pragma udata [xxx]
#pragma udata
udata : (idata)
[data-qualifier] :
z
z
Option
access ==> ACCESS Bank RAM (0x00-0x7F)

==> ACCESS Bank (GPR)
[section-name [= addr]] :
z
section-name: Linkersection-name
z
section-name: Linker
section-nameunprotected
z
= addr :
TLS2118
Slide
87
#pragma udata
#pragma udata
near unsigned
near unsigned
near unsigned
near unsigned
access AccessSection
char Temp_Code[4];
char Rec_Data;
char PWM_Duty;
char On_Flag;
#pragma udata
unsigned char
unsigned char
unsigned char
unsigned char
abc=0x100
j;
i;
e;
f;
#pragma udata
unsigned char
unsigned char
unsigned char
unsigned char
test
EE_Write_Data;
EE_Addr;
Send_UR;
Err;
Access Bank
Linker
GPR
0x100
GPRLinker
section name
Bank 2
SECTION
NAME=test
RAM=gpr2
#pragma udata
TLS2118
Slide
88
REGNAMEbits.BITNAME
p18f4520.h
z
z
'bits'
data sheet
Example
LATBbits.LATB5 = 1;
Flag = PORTBbits.RB5;
while (!ADCONbits.DONE) { }
ADCON0bits.ADON = 1;
TLS2118
//
//
//
//
Set bit 5 of PORTB

Read bit 5 of PORTB
While A/D converting
Enable A/D
Slide
89

Example for PIC18F4520
TRISEbits Variable Declaration from p18f4520.h Header File
extern volatile near unsigned char TRISE;
extern volatile near union {
Bit Field Structure Definitions
struct {
unsigned TRISE0:1;
unsigned TRISE1:1;
Primary Bit Names
unsigned TRISE2:1;
};
struct {
unsigned :4;
unsigned PSPMODE:1;
Secondary Bit Names
unsigned IBOV:1;
unsigned OBF:1;
unsigned IBF:1;
Bit Field
};
Variable
} TRISEbits;
Declaration
TLS2118
Slide
90
Register and Bit Field Variables

Definition in Processor Specific Library
z
z
Both REGNAME and REGNAMEbits defined in a

processor specific library
Both are allocated at the same address
Excerpt from p18f4520.asm (p18f4520.lib) Library File
SFR_UNBANKED0
PORTA
PORTAbits
PORTB
PORTBbits
PORTC
PORTCbits
UDATA_ACS H'F80'
RES 1
; 0xF80
RES 1
; 0xF81
RES 1
; 0xF82
TLS2118
Slide
91
Lab Exercise 2
I/O Port
MPLAB SIM
LCD
C18
Lab Exercise 2
I/O Library
: C:\RTC\TLS2118\Lab2\Lab2.mcp
Microchip Head File (p18f4520.h)
TLS2118
Slide
93
Lab Exercise 2
I/O Library
Lab Exercise 2
z
I/O
z
z
z
APP001 , LED
(: LCD LED)
C18 ,
MPLAB SIM delay( )

Library TLS2118.lib LCD function
libraries .
MPLAB C18 standard library
itoa(int value, char *string ) ?

Key_Count Loop_Count
putsLCD( ) LCD
TLS2118
Slide
94
PIC18 Family
Interrupts
18F4520
z
18F4520
==>0x0008
==>0x0018

(Flag)
==>
EnableDisable
PIC18PIC16Fxxx
TLS2118
Slide
96
TMR0IF
Core Interrupts
TMR0IE
Other Core
Interrupts
TMR1IF
TMR1IE
Wakeup
to CPU
Peripheral
Interrupts
Interrupt
to CPU
Vector to 0x0008
Other
Peripheral
Interrupts
GIE
PEIE
TLS2118
Slide
97
IP
IE
IF
INT0IF
INT0IE
GIEH
Vector to 0x0008
High Priority
Interrupt to CPU
Wakeup to CPU
Low Priority
Interrupt to CPU
IP
IE
IF
Vector to 0x0018
GIEL
TLS2118
Slide
98
Shadow
z
z
18F4520Shadow Register
z
z
WBSRSTATUS /Shadow Register

retfie FAST
WBSRSTATUS /
retfie 0
C18
: C
TLS2118
Slide
99

z #pragma code
- 0x0008
goto
z #pragma interrupt
()
retfie FAST
#pragma interrupt func-name save=symbol list
func-name :
save= symbol list :

(: save= FSR0, PRODL)
TLS2118
Slide
100
ISR
#pragma code hi_vector=0x0008
//
void isr_high_code(void)
{
_asm
(isr_high)
goto
isr_high
_endasm
}
#pragma code
//************************************************
//* Function: isr_high(void)
*
//*
- Received a serial data from RS-232
*
//*
- Save the received data to Rec_Data
*
//************************************************
#pragma interrupt isr_high
void isr_high(void)
{
(isr_high)
Rec_Data=ReadUSART();
PORTD=Rec_Data;
}
#pragma code
TLS2118
Slide
101
(USART)
1. :
RCONbits.IPEN=1;
2. USART: IPR1bits.RCIP=1;
3. enable USART:
PIE1bits.RCIE=1;
4. :
INTCONbits.GIEH=1;
TLS2118
Slide
102

z #pragma code
- 0x0008
goto
z #pragma interruptlow
retfie
#pragma interruptlow func-name save=symbol list
func-name :
save= symbol list : (

: save= FSR0, PRODL)
TLS2118
Slide
103
(ISR)
z
z
z
z
z
volatile
Local
ISR
Flag
tmpdata ISR
() save
tmpdata
C18 tempdata
TLS2118
Slide
104
tmpdata vs.
z
z
z
tmpdata
C18 tmpdata
tmpdata
tmpdata
#pragma interrupt isr nosave=section(".tmpdata")
void isr (void)
{
...
}
TLS2118
Slide
105
PIC18 Family
Timers
PIC18 :
Timer0
z
z
Timer0 8-Bits 16-Bits

16-bit mode TMR0H TMR0L
Timer0
8-bit Data Bus 16-bit Timer
FFh to 00h (FFFFh to 0000h)
TLS2118
Slide
107
PIC18
Timer1 and Timer3
z
16-bit
/ 8-bit
1 24or 8

( )
( System Clock )
FFFFh to 0000h
TLS2118
Slide
108
PIC18
Timer1 and Timer3 (continued)
Data Bus<7:0>
TMR1H
Latch
Latch
TMR1H
TMR1H
8
8
CCP Special Even Trigger
CLR
TMR1H
High Byte
TMR1L
TMRON
on/off
T1OSC
T13CLI/
T1OSO
T1OSI
T1SYNC
1
T1OSCEN
Enable
Oscillator(1)
Fosc/4
0
Internal
Clock
TMR1CS
Prescaler
1, 2, 4, 8
Synchronize
det
SLEEP input
T1CKPS1:T1CKPS0
TLS2118
Slide
109
Timer1
T1OSI
T1
OSC
T1OS0
prescaler
synchronize
Fosc/4
T1CKI
pin
TMR1H
TMR1L
Enable
Timer1 Control Register (T1CON)

RD16
T1RUN
TMR1ON
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
T1CKPS1
T1CKPS0
scale
1:8
LP Oscillator Enable
1:4
1:2
1 = T1OSC selected
0 = T1CKI can be used
1:1
Timer1 On
TLS2118
1 = Enable Timer1
Clock Source Select

1 = External (T1CKI)
0 = Internal (FOSC/4)
Slide
110
PIC18
Timer2
z
8-bit
PWM
TMR2
TMR2
MSSP (SPI)
TLS2118
Slide
111
Timer2
TMR2
Fosc/4
1:1, 1:4, 1:16
TMR2
1 1 1 1 0
1 1
0 0
1 1
0
1:1 1:16
PR2
1 1 1 1 1 0 0 0
PIR1
1
TMR2IF
Timer2 T2CON
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
TLS2118
Slide
112
Lab Exercise 3
Timer1
C18 Timers
Lab Exercise 3
Timer Interrupt
MPLAB C18
Timer
TLS2118
Slide
114
Lab Exercise 3
Timer Interrupt
Lab Exercise 3
z
C18 Library Timer1
Timer1 1 ms CPU
MPLAB SIM Timer1
HH:MM:SS
LCD
TLS2118
Slide
115
Lab Exercise 3
Timer1
Timer1
z
Timer1
Timer #include <timers.h>

WriteTimer1(TIMER1_1ms_VALUE);
//
OpenTimer1( TIMER_INT_ON & T1_16BIT_RW &\
T1_SOURCE_INT & T1_PS_1_1 & \
T1_OSC1EN_OFF & T1_SYNC_EXT_OFF ) ;
1mS
#define
TIMER1_1ms_VALUE 65536-(1000*2) // @8MHz

Tosc = 8MHz Fcy = 2MHz
1:1 1mS 2MHz / 1000 Hz = 2000

Timer1 1mS 2000 Timer1 (65536 2000)
TLS2118
Slide
116
Lab Exercise 3
Timer1
Timer1
z
Temp Data
#pragma interrupt HighISR nosave=section(".tmpdata")
Timer1
TIMER1_1ms_VALUE 65536-(1000*2)
MPLAB SIM
:
TIMER1_1ms_VALUE
65536-(1000*2) + 156
TLS2118
Slide
117
PIC18 Family
10-Bit Analog-to-Digital Converter
PIC18F4520 10-bit A/D
SAR ( TAD )
12 10 bits
2.4 S (<10K)
11 ~ 12 TAD
8.4 S (12 TAD , TAD 0.7uS)
10-bit
VREF+ & VREF-
TLS2118
Slide
119
PIC18F4520 ADC
TLS2118
Slide
120
PIC18F4520 ADC
TLS2118
Slide
121
ADC
z
ADCON0
ADCON0
CHS3
CHS1
CHS2
CHSx
GO/DONE
ADON
CHS0
GO/DONE
ADON
1 = A/D
0 = A/D
ADC
TLS2118
Slide
122
ADC
ADCON1
---
---
VCFG1 VCFG0 PCFG3 PCFG2
VCFG1
VCFG0
PCFGx
PCFG1
PCFG0
1 = Vref- 0 = Vss
1 = Vref+ 0 = Vdd
AD
AN0 ~ AN12
TLS2118
Slide
123
ADC
ADCON2
ADFM
---
ACQ2
ACQ1
ACQ0
ADFM
ACQx
ADCx
ADCS2
ADCS1
ADCS0
AD
1 = 0 =
AD
0 TAD 20 TAD
AD
AN0 ~ AN12
( )
TLS2118
Slide
124
ADFM
z
z
ADC
ADRESH ADRESL
10-bit ADC
LSB
MSB
10-bit
LSB
MSB
10-bit
TLS2118
Slide
125
PCFGx
z
ADC
TLS2118
Slide
126
C18
z
(p18f4520.lib)
C:\Program Files\Microchip\mplabc18\v3.38\doc\
PIC18F Peripheral Library Help Document.chm
(clib.lib)
Software Peripheral Library
z
Software IC Functions, Software UART Functions,
General Software Library

z
Math Libraries
z
32-bit
..\mplabc18\v3.38\doc\hlpC18lib.chm
TLS2118
Slide
127
ADC
z
z
C18 PIC18F4520
ADC :
(void) OpenADC ( unsigned char config,

unsigned char config2,
unsigned char portconfig)
(void) SetChanADC (unsigned char channel)
(void) SelChanConvADC (unsigned char channel)
(void) ConvertADC (void)
(void) BusyADC (void)
Int ReadADC (void)
(void) CloseADC (void)
#include adc.h
TLS2118
Slide
128
A/D
MCU
A/D
No
PIC18F4520
ADCON2
?
Yes
A/D
MCU2101
Slide
129
Lab Exercise 4
10-Bit Analog-to-Digital
MPLAB C18 ADC
Lab Exercise 4
10-Bit ADC MPLAB C18 Library
MPLAB C18
MCU2101
Slide
131
Lab Exercise 4
Lab Exercise 4
z
ADC module ()
MPLAB C18 ADC Library ADC module
3 1ms Timer1
100ms Time Event
100ms Time Event , ADC APP001

VR1 ()
ADC LCD
TLS2118
Slide
132
Lab Exercise 4
ADC
OpenADC ( ADC_FOSC_16 & ADC_RIGHT_JUST & ADC_4_TAD ,
ADC_CH0 & ADC_INT_OFF & ADC_REF_VDD_VSS ,
ADC_1ANA);
z
ADC :
ADC_FOSC_16 : Tad Fosc/16

ADC_RIGHT_JUST : AD
ADC_4_TAD : AD 4 Tad
ADC_CH0 : Channel 0 AD
ADC_INT_OFF : AD
ADC_REF_VDD_VSS : VDD & VSS ADC
ADC_1ANA : AN0
TLS2118
Slide
133
Lab Exercise 4
ADC
z
AD
SelChanConvADC(ADC_CH0) ;
while(BusyADC()) ;
Update_ADC(ReadADC()) ;
ADC :
SelChanConvADC(ADC_CH0) : Channel 0
AD
while(BusyADC( )) : AD
Update_ADC(ReadADC()) : AD Update_ADC
TLS2118
Slide
134

MPLAB C18 Runtime environment
Memory Models
How to Override the Default Characteristics of Variables and Functions

PIC18F Family
PIC18 Family
z
PIC18F ( RISC )
PIC :
Harvard Architecture
Instruction Pipelining
Large Register File
Single Cycle Instructions
Single Word Instructions
Long Word Instructions
Reduced Instruction Set
Orthogonal Instruction Set
TLS2118
Slide
137
PICmicro
Von Neumann (MCU)
Program
Data
Memory
C PU
8-Bits
Harvard (PIC Micro)
CPU
MCU
8-Bits
12/14/16-Bits
Program
Memory
Data
Memory
TLS2118
Slide
138
PIC18F4520 ()
TLS2118
Slide
139
PIC18F4520 ()
TLS2118
Slide
140
PIC18 Family
z
2MB ( 1 MW ) ,
21-bit Program Counter
Reset Vector
000000h
High Priority Interrupt Vector
000008h
Low Priority Interrupt Vector
000018h
On-chip
On-chip Program
Program Memory
Memory
Stack
Stack Level
Level 11
007FFEh
Stack
Stack Level
Level 22
008000h
Stack
Stack Level
Level 30
30
Stack
Stack Level
Level 31
31
Unimplemented
Unimplemented
Program
Program Memory
Memory
(Read
(Read as
as 0)
0)
31 Level Stack
1FFFFEh
TLS2118
Slide
141
Register File
Data Memory
(Register File)
w
data memory
data memory
data
memory
07h
ALU
08h
Data Bus
Bus
Data
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
WREG
WREG
Decoded Instruction
Opcode
from Program Memory: Opcode
Arithmetic/Logic
Function to be Performed
d
d a
a
Result
Destination
Address
Address
Address of Second
Source Operand
TLS2118
Slide
142
Data Memory Organization

z
Data Memory
4k bytes
( movff fs,fd )
bank 256
byte bank4KB
RAM 16 banks
bank 0 128 Bytes
bank 15 128 Bytes
bank
(Access Bank)
Access
Bank BSR
Access bank !
000h
07Fh
Access
Access RAM
RAM
080h
0FFh
Bank
Bank 00 GPR
GPR
PIC18F4520
Register File Map
100h
Bank
Bank 11
GPR
GPR
1FFh
200h
Bank
Bank 22
GPR
GPR
Access Bank
2FFh
D00h
Bank
Bank 13
13
GPR
GPR
Access
Access RAM
RAM
00h
7Fh
Access
Access SFR
SFR
80h
FFh
256 Bytes
DFFh
E00h
Bank
Bank 14
14
GPR
GPR
EFFh
F00h
F7Fh
Bank
Bank 15
15 GPR
GPR
F80h
FFFh
Access
Access SFR
SFR
TLS2118
Slide
143
movlw 0x05
1 MAIN movlw
2
movwf
3
rcall
4
addwf
0x05
REG1
SUB1
REG2
T0
Fetch
51 SUB1 movf
PORTB,w
52
return
53 SUB2 movf
PORTC,w
54
return
TLS2118
Slide
144
movwf REG1
movlw 0x05
1 MAIN movlw
2
movwf
3
rcall
4
addwf
0x05
REG1
SUB1
REG2
T0
T1
Fetch Execute
Fetch
51 SUB1 movf
PORTB,w
52
return
53 SUB2 movf
PORTC,w
54
return
TLS2118
Slide
145
rcall SUB1
movwf REG1
1 MAIN movlw
2
movwf
3
rcall
4
addwf
0x05
REG1
SUB1
REG2
T0
T1
T2
Fetch Execute
Fetch Execute
Fetch
51 SUB1 movf
PORTB,w
52
return
53 SUB2 movf
PORTC,w
54
return
TLS2118
Slide
146
addwf REG2
rcall SUB1
1 MAIN movlw
2
movwf
3
rcall
4
addwf
0x05
REG1
SUB1
REG2
T0
T1
T2
T3
Fetch Execute
Fetch Execute
Fetch Execute
Fetch
51 SUB1 movf
PORTB,w
52
return
53 SUB2 movf
PORTC,w
54
return
TLS2118
Slide
147
movf PORTB,w
rcall SUB1
1 MAIN movlw
2
movwf
3
rcall
4
addwf
0x05
REG1
SUB1
REG2
T0
T1
T2
T4
Fetch Execute
Fetch Execute
Fetch Execute
Fetch
Flush
PC
call

Fetch
51 SUB1 movf
PORTB,w
52
return
53 SUB2 movf
PORTC,w
54
return
T3
TLS2118
Slide
148
return
movf PORTB,w
1 MAIN movlw
2
movwf
3
rcall
4
addwf
0x05
REG1
SUB1
REG2
T0
T1
T2
T4
T5
Fetch Execute
Fetch Execute
Fetch Execute
Fetch
Flush
Fetch Execute
51 SUB1 movf
PORTB,w
52
return
53 SUB2 movf
PORTC,w
54
return
T3
Fetch
TLS2118
Slide
149
movf PORTC,w
return
1 MAIN movlw
2
movwf
3
rcall
4
addwf
0x05
REG1
SUB1
REG2
T0
T1
T2
T4
T5
T6
Fetch Execute
Fetch Execute
Fetch Execute
Fetch
Flush
Fetch Execute
51 SUB1 movf
PORTB,w
52
return
53 SUB2 movf
PORTC,w
54
return
T3
Fetch Execute
Fetch
TLS2118
Slide
150
addwf REG2
return
1 MAIN movlw
2
movwf
3
rcall
4
addwf
0x05
REG1
SUB1
REG2
T0
T1
T2
T4
T5
T6
T7
Fetch Execute
Fetch Execute
Fetch Execute
Fetch
Flush
Fetch
Fetch Execute
51 SUB1 movf
PORTB,w
52
return
53 SUB2 movf
PORTC,w
54
return
T3
Fetch Execute
Fetch
TLS2118
Flush
Slide
151
PIC18 Family
Long Word Instruction
SISC 8-bit
Example: Freescale Load Accumulator A:
2 Program Memory Locations
2 Instruction Cycles to Execute
ldaa #k
1
1 0
0 0
0 0
0 0
0 1
1 1
1 0
0
k
k k
k k
k k
k k
k k
k k
k k
k
z
z
Limits Bandwidth
Increases Memory
Size Requirements
PIC18 8-bit MCU 16-bit

Example: Move Literal to Working Register
1 Program Memory Location
1 Instruction Cycle to Execute
movlw k
0
0 1
0 0
1 1
0 0
0 0
1 1
1 0
0 k
k k
k k
k k
k k
k k
k k
k k
k
z
z
Separate busses allow different widths

2k x 16 is roughly equivalent to 4k x 8
TLS2118
Slide
152
PIC18 Family
Byte
Byte Oriented
Oriented Operations
Operations
addwf
addwf f,d,a
f,d,a Add
Add WREG
WREG and
and ff
addwfc
addwfc f,d,a
f,d,a Add
Add WREG
WREG and
and Carry
Carry bit
bit to
to ff
andwf
andwf f,d,a
f,d,a AND
AND WREG
WREG with
with ff
clrf
f,a
Clear
clrf
f,a
Clear ff
comf
f,d,a
comf
f,d,a Complement
Complement ff
cpfseq
Compare
cpfseq f,a
f,a
Compare ff with
with WREG,
WREG, skip
skip ==
cpfsgt
Compare
cpfsgt f,a
f,a
Compare ff with
with WREG,
WREG, skip
skip >>
cpfslt
f,a
Compare
cpfslt
f,a
Compare ff with
with WREG,
WREG, skip
skip <<
decf
f,d,a
decf
f,d,a Decrement
Decrement ff
decfsz
decfsz f,d,a
f,d,a Decrement
Decrement f,f, Skip
Skip ifif 00
dcfsnz
dcfsnz f,d,a
f,d,a Decrement
Decrement f,f, Skip
Skip ifif Not
Not 00
incf
f,d,a
incf
f,d,a Increment
Increment ff
incfsz
incfsz f,d,a
f,d,a Increment
Increment f,f, Skip
Skip ifif 00
infsnz
infsnz f,d,a
f,d,a Increment
Increment f,f, Skip
Skip ifif Not
Not 00
iorwf
f,d,a
iorwf
f,d,a Inclusive
Inclusive OR
OR WREG
WREG with
with ff
movf
f,d,a
movf
f,d,a Move
Move ff
movff
Move
(src) to
to ffdd (dst)
(dst)
movff ffss,f,fdd
Move ffss (src)
movwf
Move
movwf f,a
f,a
Move WREG
WREG to
to ff
mulwf
Multiply
mulwf f,a
f,a
Multiply WREG
WREG with
with ff
TLS2118
negf
negf
rlcf
rlcf
rlncf
rlncf
rrcf
rrcf
rrncf
rrncf
setf
setf
subfwb
subfwb
subwf
subwf
subwfb
subwfb
swapf
swapf
tstfsz
tstfsz
xorwf
xorwf
f,a
f,a
f,d,a
f,d,a
f,d,a
f,d,a
f,d,a
f,d,a
f,d,a
f,d,a
f,a
f,a
f,d,a
f,d,a
f,d,a
f,d,a
f,d,a
f,d,a
f,d,a
f,d,a
f,a
f,a
f,d,a
f,d,a
Negate
Negate ff
Rotate
Rotate Left
Left ff through
through Carry
Carry
Rotate
Rotate Left
Left ff (No
(No Carry)
Carry)
Rotate
Rotate Right
Right ff through
through Carry
Carry
Rotate
Rotate Right
Right ff (No
(No Carry)
Carry)
Set
Set ff
Subtract
Subtract ff from
from WREG
WREG with
with borrow
borrow
Subtract
Subtract WREG
WREG from
from ff
Subtract
Subtract WREG
WREG from
from ff with
with borrow
borrow
Swap
Swap nibbles
nibbles in
in ff
Test
Test f,f, skip
skip ifif 00
Exclusive
Exclusive OR
OR WREG
WREG with
with ff
bcf
bcf
bsf
bsf
btfsc
btfsc
btfss
btfss
btg
btg
Bit
Bit Oriented
Oriented Operations
Operations
f,b,a
f,b,a Bit
Bit Clear
Clear ff
f,b,a
f,b,a Bit
Bit Set
Set ff
f,b,a
f,b,a Bit
Bit Test
Test f,f, Skip
Skip ifif Clear
Clear
f,b,a
f,b,a Bit
Bit Test
Test f,f, Skip
Skip ifif Set
Set
f,b,a
f,b,a Bit
Bit Toggle
Toggle ff
Slide
153
PIC18 Family
bc
bc
bn
bn
bnc
bnc
bnn
bnn
bnov
bnov
bnz
bnz
bov
bov
bra
bra
bz
bz
call
call
clrwdt
clrwdt
daw
daw
goto
goto
nop
nop
pop
pop
push
push
rcall
rcall
reset
reset
retfie
retfie
return
return
sleep
sleep
nn
nn
nn
nn
nn
nn
nn
nn
nn
n,s
n,s
nn
nn
ss
ss
Control
Control Operations
Operations
Branch
Branch ifif Carry
Carry
Branch
Branch ifif Negative
Negative
Branch
Branch ifif Not
Not Carry
Carry
Branch
Branch ifif Not
Not Negative
Negative
Branch
Branch ifif Not
Not Overflow
Overflow
Branch
Branch ifif Not
Not Zero
Zero
Branch
Branch ifif Overflow
Overflow
Branch
Branch Always
Always
Branch
Branch ifif Zero
Zero
Call
Call subroutine
subroutine
Clear
Clear Watchdog
Watchdog Timer
Timer
Decimal
Decimal Adjust
Adjust WREG
WREG
Go
Go to
to address
address
No
No Operation
Operation
Pop
Pop top
top of
of return
return stack
stack (TOS)
(TOS)
Push
Push top
top of
of return
return stack
stack (TOS)
(TOS)
Relative
Relative Call
Call
Software
Software device
device RESET
RESET
Return
Return from
from interrupt
interrupt
Return
Return from
from subroutine
subroutine
Go
Go into
into standby
standby mode
mode
addlw
addlw
andlw
andlw
iorlw
iorlw
lfsr
lfsr
movlb
movlb
movlw
movlw
mullw
mullw
retlw
retlw
sublw
sublw
xorlw
xorlw
kk
kk
kk
f,k
f,k
kk
kk
kk
kk
kk
kk
Literal
Literal Operations
Operations
Add
Add literal
literal and
and WREG
WREG
AND
AND literal
literal with
with WREG
WREG
Inclusive
Inclusive OR
OR literal
literal with
with WREG
WREG
Move
Move 12-bit
12-bit literal
literal to
to FSR
FSR
Move
Move literal
literal to
to BSR<3:0>
BSR<3:0>
Move
Move literal
literal to
to WREG
WREG
Multiply
Multiply literal
literal with
with WREG
WREG
Return
Return with
with literal
literal in
in WREG
WREG
Subtract
Subtract WREG
WREG from
from literal
literal
Exclusive
Exclusive OR
OR literal
literal with
with WREG
WREG
Data
Data Memory
Memory
Program
Program Memory
Memory Operations
Operations
tblrd*
Table
tblrd*
Table Read
Read
tblrd*+
Table
tblrd*+
Table Read
Read with
with post-increment
post-increment
tblrd*Table
tblrd*Table Read
Read with
with post-decrement
post-decrement
tblrd+*
Table
tblrd+*
Table Read
Read with
with pre-increment
pre-increment
tblwt*
Table
tblwt*
Table Write
Write
tblwt*+
Table
tblwt*+
Table Write
Write with
with post-increment
post-increment
tblwt*Table
tblwt*Table Write
Write with
with post-decrement
post-decrement
tblwt+*
Table
tblwt+*
Table Write
Write with
with pre-increment
pre-increment
TLS2118
Slide
154
PIC18 Family
Byte Oriented Operations
15
Opcode
OR
Opcode
d a
File Register Address

Destination (W or F)
ADDWF
Access Bank
0x25, W, A
File Register Address
Use Access Bank

Destination (Optional)
TLS2118
Slide
155
PIC18 Family
15
15
11
11
99
88
77
00
File
File Register
Register Address
Address
Bit
Bit Position
Position (0-7)
(0-7)
BSF 0x25, 3, A
File
File Register
Register Address
Address
Bit
Bit Position
Position
TLS2118
Access
Access Bank
Bank
(Optional)
(Optional)
Slide
156
PIC18 Family
Literal and Control Operations
15
Opcode
Literal Value
OR
Opcode
MOVLW
0x25
Literal Value
TLS2118
Slide
157
PIC18 Family
Byte to Byte Move Operations(2 Words)
15
12
Opcode
Opcode
11
Source Register Address
fs fs fs fs fs fs fs fs fs fs fs fs
fd fd fd fd fd fd fd fd fd fd fd fd
Destination Register Address
MOVFF
0x125, 0x140
Source Address
TLS2118
Destination Address
Slide
158
PIC18 Family
Call and Goto Operations (2 Words)
15
11
Opcode
Opcode n20 n19
n8 n7 n6 n5 n4 n3 n2 n1
n18 n17 n16 n15 n14 n13 n12 n11 n10 n9
CALL
0x1125
Subroutine Address
TLS2118
Slide
159
PIC18 Family
Data Memory Access
Mode
Example Syntax
Direct
movf <reg> , <dst>
Indirect
clrf
Auto Pre-Increment Indirect
movff PREINCn , <dst>
Auto Post-Increment Indirect
movff POSTINCn , <dst>
Auto Post-Decrement Indirect
movff POSTDECn, <dst>
Index Indirect
movff PLUSWn, <dst>
Immediate (Literal)
movlw <const>
TLS2118
INDFn, <dst>
Slide
160
Banked
a Bit from
Instruction
BSR
f Operand
4-bits from BSR Register
8-bits Encoded in Instruction
0 0 1 0
12-bit Effective Address

(Use this when coding)
0 1 1 1 1 1 1 0
0x27E
Banked
Access
RAM
Bank0
Bank1
Bank2
Bank13
Bank14
Bank15
00
01
02
03
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
7D
7E
7F
80
81
82
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FC
FD
FE
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
TLS2118
Slide
161
Banked
a Bit from
Instruction
BSR
f Operand
1 1 0 1

0 1 1 1 1 1 1 0
0xD7E
banked
Access
RAM
Bank0
Bank1
Bank2
Bank13
Bank14
Bank15
00
01
02
03
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
7D
7E
7F
80
81
82
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FC
FD
FE
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
TLS2118
Slide
162
Access Bank
a Bit from
Instruction
BSR
f Operand
XXXX

0 0 0 0 0 0 1 1
0x003
Access Bank
Access
RAM
Bank0
Bank1
Bank2
Bank13
Bank14
Bank15
00
01
02
03
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
7D
7E
7F
80
81
82
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FC
FD
FE
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
TLS2118
Slide
163
Access Bank
a Bit from
Instruction
BSR
f Operand
XXXX

1 0 0 0 0 0 1 0
0xF82
Access Bank
Access
RAM
Bank0
Bank1
Bank2
Bank13
Bank14
Bank15
00
01
02
03
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
7D
7E
7F
80
81
82
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FC
FD
FE
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
TLS2118
Slide
164

4-bits from FSR0H
8-bits from FSR0L
1 1 1 1 + 1 1 1 1 1 1 0 1
FSR0H
bank FSR
RAM
FSRH:FSRL : LFSR
12-bit
12-bit
0xFFD
FSR0L
Data Memory
000h
001h
002h
003h
004h
005h
FF
FF
FF
FF
FFAh
FFBh
FFCh
FFDh
FFEh
FFFh
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FSR ( 12-bits )
: FSR0, FSR1 & FSR2
FF
FF
Register File
Address Bus
FF
FF
FF
FF
TLS2118
Slide
165

4-bits from FSR0H
8-bits from FSR0L
0 0 0 0 + 0 0 0 0 0 0 1 0
FSR0H
bank FSR
RAM
FSRH:FSRL : LFSR
12-bit
12-bit
0x002
FSR0L
Data Memory
000h
001h
002h
003h
004h
005h
FF
FF
FF
FF
FF
FF
FF
FF
Register File
Address Bus
FF
FF
FSR ( 12-bits )
: FSR0, FSR1 & FSR2
FFAh
FFBh
FFCh
FFDh
FFEh
FFFh
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
TLS2118
Slide
166
PIC18 Family Indirect

Addressing , :
Indirect - no change in FSRn
Auto Post-decrement FSRn (FSRn--)
Auto Post-increment FSRn (FSRn++)
Auto Pre-increment FSRn (++FSRn)
Index Indirect (Address = FSRn + W)
TLS2118
Slide
167
PIC18 Family
Program Memory Access
(Absolute)
(Relative)
Table Read / Write
goto <addr>
bra <addr>
tblrd*
tblwt*
Table Read / Write

Post Increment
tblrd*+
tblwt*+
Table Read / Write

Post Decrement
tblrd*-
tblwt*-
Table Read / Write

Pre Increment
tblrd+*
tblwt+*
TLS2118
Slide
168
Program Memory is Byte

Addressable
z
z
: Low byte high byte
Word
Word Address
High Byte Address
Low Byte Address
0x000001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000000
0x000003 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000002
0x000005 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000004
0x000007 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000006
0x000009 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000008
0x00000B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00000A
0x00000D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00000C
0x00000F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00000E
TLS2118
Slide
169
Table Reads/Writes
z
Table Read/Write

Table Read / Write Addressing Modes:
No Change
tblrd *
tblwt *
Post Increment
tblrd *+
tblwt *+
Post Decrement
tblrd *-
tblwt *-
Pre Increment
tblrd +*
tblwt +*
Table Read/Write
TLS2118
Slide
170
Table Reads
Program Memory
Space
PIC18F :

z
z
0x01FFFF
8 Modifiable Bytes
Unimplemented Memory
0x200000
Device Settings, Code Protects,

etc.
Part and Revision Signature
(PC) 1MB User

Memory (PC is 21-bits wide)
Table Pointer
(TBLPTR is 22-bits wide)
User
User IDs
IDs
0x200007
Device IDs
z
User
User Flash
Flash
Configuration Memory
z
1 MB
IDs
z
Up to 128kB Internal
Up to 2MB External
0x000000
TLS2118
0x300000
Configuration
Configuration
0x30000D
0x3FFFFE
Device
Device IDs
IDs
0x3FFFFF
Slide
171
Table Read
TBLPTRU
TBLPTRH
TBLPTRL
00
00
00
00
09
09
Data Memory (RAM)
Program Memory (Flash)
0x000
22-bit Address
0x001
0x002
0x003
0x004
0x005
0x000001
0x000000
0x000003
0x000002
0x000005
0x000004
0x000007
0x000006
0x000009
TABLAT
2C
2C
2C
2C
0x000008
0x00000B
0x00000A
8-bit Data
0xFFA
0x1FFFF5
0x1FFFF4
0xFFB
0x1FFFF7
0x1FFFF6
0xFFC
0x1FFFF9
0x1FFFF8
0xFFD
0x1FFFFB
0x1FFFFA
0xFFE
0x1FFFFD
0x1FFFFC
0xFFF
0x1FFFFF
0x1FFFFE
High Byte
(Odd Addr)
TLS2118
Low Byte
(Even Addr)
Slide
172
LCD
ASCII
:
Program Memory
Address
Contents
6FFC
FF FF
6FFE
7000
FF FF
69 4D
7002
72 63
7004
63 6F
7006
7008
69 68
00 70
700A
FF FF
700C
FF FF
i @ 0x7001
M @ 0x7000
i @ 7001h
M @ 7000h
org 0x7000
MyStringTable
db Microchip\0
\0 (NUL) @ 0x7009
TLS2118
Slide
173
PIC18
Top of Stack Register

TOSU
TOSH
TOSL
Current value on the

Top Of Stack
31
23
STKPTR Register
SP4:SP0
STKOVF
0 0
1 X
1
7
STKUNF
STKPTR [SP4:SP0]
Register
PC
PC
PC
UnderFlow
FlowError
Error
Over
01
call
return
RETFIE
Interrupt
TLS2118
Slide
174
Memory Models
Object Allocation Schemes
Memory Models
Overview
Option
Small
-ms
Large
-ml
Description
For programs < 64KB
Pointers to Data Space:
Pointers to Program Space:
For programs > 64KB
Pointers to Data Space:
Pointers to Program Space:
16-bits
16-bits
For data < 128B

All data resides in the
Access bank
16-bits
24-bits
For data > 128B

Data may reside in any
bank
May override on a case by case basis with

the near and far qualifiers
The General Purpose RAM portion of the Access bank is not 128 bytes on all devices. It
may be smaller for devices with more than 128 bytes of Special Function Registers (e.g.
PIC18F8720: 0xF60-0xFFF vs PIC18F4520: 0xF80-0xFFF).
TLS2118
Slide
176
Memory Models
Small Data
Data Memory (RAM)
NEAR
ACCESS GPR
Bank 0
Bank 1
z
z
FAR
z
Bank 14
All data fits in ACCESS

bank (usually 128B)
No bank switching
required
Fastest data access
Smallest code to
access data
Causes warnings when
using libraries
Bank 15
NEAR
ACCESS SFR
TLS2118
Slide
177
Memory Models
Large Data
Data Memory (RAM)
NEAR
ACCESS GPR
Bank 0
Bank 1
z
FAR
Bank 14
All data cannot fit in

ACCESS bank
Data can reside
anywhere
Bank switching
required
Data treated as if it
were in far space
Libraries are built using
this memory model
Bank 15
NEAR
ACCESS SFR
TLS2118
Slide
178
Memory Models
Small Code
0x000000
64kB
z
Default Model
Program fits within
64kB
ROM pointers (data
and function) are 16bits (same as RAM)
0x7FFFFF
TLS2118
Slide
179
Memory Models
Large Code
0x000000
Program cannot fit

within 64kB
ROM pointers (data
and function) are 24bits
0x7FFFFF
TLS2118
Slide
180
Memory Models
How to Select the Memory Model
Open Project Build Options
From the menu bar, select:
Project f Build Options f Project
TLS2118
Slide
181
Memory Models
Go to Memory Models
Select the MPLAB C18 tab
Select the Memory Model category
TLS2118
Slide
182
Memory Models
Select Desired Models
TLS2118
Slide
183
Memory Models
Tips & Tricks
z
Inappropriate model for your program can

cause compile or link errors
As your program grows, you may need to
change the memory model
If desired, you have full control over
where objects are placed in memory
Use small model, but force some objects into
far memory
Compile different modules with different models
TLS2118
Slide
184
Memory Models
Tips & Tricks
z
Compiler can often generate more compact code if

variables in the Access bank
Option
Tips for Optimal Memory Use

Use if all variables for the application can fit in Access bank
Small Data
Large Data
If all data doesnt fit in near space, define some variables

with the far qualifier so others have space to fit in near
data.
1. Compile some individual modules using Small Data.
Then include their compiled object modules in the Large
Data project.
2. Define individual variables with the near qualifier
Following the use of a far data pointer in a small memory

model program, the TBLPTRU byte must be cleared by the
user. MPLAB C18 does not clear this byte.
TLS2118
Slide
185
Memory Models
Tips & Tricks
z
Functions that are near (in first 64kB) may call each
other more efficiently
Option
Tips for Optimal Memory Use
Small Code
1. Use if all functions are within first 64kB.

2. Compile some modules using Small Code and include their
object files in a Large Code project.
3. If not all functions are in first 64kB, define some functions
with the far qualifier.
Large Code
1. Define some functions with the near qualifier. An error will

be generated if the function cannot be reached by one of its
callers using the more efficient form of the function call.
Following the use of a far function pointer in a small

memory model program, the PCLATU byte must be cleared
by the user. MPLAB C18 does not clear this byte.
TLS2118
Slide
186
Mixing Memory Models

Small Code application with Large Code libraries
z
0x000000
near
Small
Code
Model
64kB
z
(*fp)();
0x00FFFF
fn();
z
far
Large
Code
Model
Project built with

small code model for
efficiency
Libraries built with
large code model for
flexibility
Function pointers
may be used to call
far code library from
small code
application
0x7FFFFF
TLS2118
Slide
187

Function in library built with large code model
void LCDPutStr(rom char *str);
Application built with small code model

Declare a function pointer and initialize it to point to the library function
far rom void (*fp)(far rom char *s)=(far rom void *)LCDPutStr;
Give function pointer and
pointer to parameter ability to
address beyond 64k
Typecast from pointer to void function to

a pointer to far rom void function
(Eliminates suspicious pointer conversion
warning)
TLS2118
Slide
188

Function in library built with large code model
void LCDPutStr(rom char *str);
Application built with small code model

Call the library function via the pointer
fp((far rom char *) "Hello, world!");
Typecast from pointer to rom char to a pointer to far rom char
(Eliminates suspicious pointer conversion warning)
TLS2118
Slide
189
How to Override the

Default Characteristics of
Variables and Functions
Using type qualifiers and #pragma
Locating Variables and Code

Section Types
General Syntax
#pragma sectiontype sectionname=address

z
Section types define the overall region of memory where

an object is to be located
Section Name
Memory Region
Usage
udata
RAM
Static Uninitialized Data (e.g. char x;)
idata
udata access
idata access
romdata
code
RAM
ACCESS RAM
ACCESS RAM
Program/Flash
Program/Flash
Static Initialized Data (e.g. char x = 55;)

Static Uninitialized Data in Access RAM
Static Initialized Data in Access RAM
Variables and Constants
Executable Code
TLS2118
Slide
191
Locating Variables
How to place a variable in the Access Bank
Syntax
#pragma sectiontype access sectionname

near type identifier;
z
z
The #pragma tells linker to place the

following variable(s) in the access bank
near tells the compiler not to generate bank
switching instructions
Can be accessed more efficiently
Example
#pragma udata access mySection

near int x;
near char a[10];
TLS2118
Slide
192
Locating Variables
Manually Optimizing Data Memory Use
Data Memory (RAM)
z
NEAR
ACCESS GPR
Bank 0
Bank 1
Use large data model

Define frequently
accessed variables
with near qualifier
FAR
Bank 14
Bank 15
NEAR
ACCESS SFR
TLS2118
Slide
193
Locating Variables
Variable Allocation Example
near Variables with the Large Data Model
#include <p18f4520.h>
char a[124];
#pragma idata access myData
near char x = 0xAA;
Variables are far by

default (banked)
int main(void)
{
...
}
To create near variables

with the large data
model:
TLS2118
a[] may be located

anywhere
Declare a new access

section and give it some
name
Define variables with the
near qualifier
Slide
194
Locating Variables
How to place a variable in far memory
Syntax
far type identifier;
z
z
Specifies that a variable may be located in

far memory (non-Access RAM)
Generates bank switching instructions to set
the BSR before accessing the variable
Example
far int x;
far char a[10];
TLS2118
Slide
195
Locating Variables
Manually Optimizing Data Memory Use
Data Memory (RAM)
z
NEAR
ACCESS GPR
Bank 0
Bank 1
z
FAR
Use small data model

Let linker place most
variables in the
Access bank
Define infrequently
accessed variables
with far qualifier
Makes room in access
bank for frequently
accessed variables
Bank 14
Bank 15
NEAR
ACCESS SFR
TLS2118
Slide
196
Locating Variables
far Variables with the Small Data Model
char a[124];
#pragma idata myData

far char x = 0xAA;
int main(void)
{
...
}
Variables are near and

in Access Bank by
default
To create far variables

with the small data
model:
TLS2118
a[] fills Access bank

along with 4 bytes claimed
by tempdata and
MATH_DATA
Declare a new section and

give it some name
far qualifier
Slide
197
Locating Variables
How to place a variable in Flash
Syntax
rom type identifier;
z
z
z
Specifies that a variable should be located in

program memory
Uses TBLRD to read variable
Effectively becomes const though writes
may be done with extra code using TBLWT
Example
rom int x = 320;

rom char a[10] = "abcedfghi";
TLS2118
Slide
198
Locating Variables
How to place a variable in Flash
z near and far also
0x000000
near
Small
Code
Model
64kB
apply to rom variables

near rom:
Variable in first 64kB
ROM Pointers are 16bit
0x00FFFF
far rom:
Variable anywhere
ROM Pointers are 24bit
far
Large
Code
Model
0x7FFFFF
TLS2118
Slide
199
Locating Variables
far Variables in Flash with the Small Code Model
#pragma romdata myNear

rom int a = 0x5555;
#pragma romdata myFar=0x10000

far rom int x = 0xAAAA;
int main(void)
{
...
}
Variables are near and

in first 64kB by default
To create far variables
with the small code
model:
TLS2118

give it some name
far rom qualifier
Slide
200
Locating Variables
near Variables in Flash with the Large Code Model
#pragma romdata myFar

rom int a = 0x5555;
z
#pragma romdata myNear=0x100

near rom int x = 0xAAAA;
int main(void)
{
...
}
Variables are far and

located anywhere by
default
To create near variables
with the large code
model:
TLS2118

give it some name
near rom qualifier
Slide
201
Locating Variables
Allocating Variables in Different Regions of Memory (large model)
#pragma udata access myUAccess
Place uninitialized variables in Access bank
near char w;
Don't generate bank switching instructions
near char a[5];
#pragma idata access myIAccess
near char x=0xAA;
near char b[] = "Microchip";
#pragma udata
char y;
char c[5];
Place initialized variables in Access bank

Don't generate bank switching instructions
Place uninitialized variables anywhere
#pragma idata
Place initialized variables anywhere
char z = 0x55;
char d[] = "PIC MCUs";
rom char e[] = "Hello, world!";
Place variable in program memory
TLS2118
Slide
202
Locating Variables
How to place a variable in EEPROM data memory
Syntax
#pragma romdata eedata_scn = 0xF00000

rom identifier = value;
z
z
z
Specifies that a variable should be located in

EEPROM data memory
May be used to initialize EEPROM data
EEPROM variables may not be read/written
like ordinary variables
Example

rom char eedata_values[4] = {0x01, 0x02, 0x03, 0x04};
rom int xee = 0x1234;
TLS2118
Slide
203
Locating Variables
Reading variables stored in EEPROM data memory
rom char xee = 0xAA;
#pragma udata
char x;
int main(void)
{
EECON1bits.EEPGD = 0;
EEADR = (int)&xee;
EECON1bits.RD = 1;
x = EEDATA;
}
//
//
//
//
Access EEPROM data memory

Load address of data to read
Start read operation
Result in EEDATA register
TLS2118
Slide
204
Locating Variables
Writing variables stored in EEPROM data memory
rom char xee;
int main(void)
{
EECON1bits.EEPGD = 0; // Access EEPROM data memory
EECON1bits.WREN = 1;
// Enable writes
EEADR = (int)&xee;
// Load address to write to
EEDATA = 0x99;
// Data to write in EEDATA
EECON2 = 0x55;
// Unlock sequence
EECON2 = 0xAA;
Interrupts must be disabled for unlock sequence
EECON1bits.WR = 1;
// Start write operation
while (!PIR2bits.EEIF) // Wait for write complete
;
// before next write
PIR2bits.EEIF = 0;
// Clear EEIF flag
}
TLS2118
Slide
205
Locating Variables
How to put related variables in the same bank
Hand Optimization of Variable Allocation
Global Variable Declarations in Program
Section Name
#pragma udata MyBigArray

unsigned char MyVar3[256];
.udata
8-bit Data Memory
Bank
MyVar1
MyVar2
MyVar4
MyVar5
BANK n
#pragma udata MyRelatedVars

unsigned char MyVar1;
MyRelatedVars
MyBigArray
BANK n+1
#pragma udata
MyVar3[256]
#pragma code
//Function Prototypes and
//Function Definitions
//Go Here
TLS2118
Slide
206
Locating Variables
How to place a variable at a specific address
Syntax
#pragma sectiontype sectionname = address
z
z
Specifies the address where a variable

should be located
Use sparingly program will be harder to
optimize by linker
Won't work if sectiontype is wrong
Example
#pragma udata xSection = 0x100

far int x;
TLS2118
Slide
207
Locating Code
How to place code at a specific address
Syntax
#pragma code sectionname = address
Specifies the address where code should be

located
Use sparingly program will be harder to
optimize by linker
Example
#pragma code myCode = 0x2000

int foo(void) { }
TLS2118
Slide
208
Resources
Microchip PIC18 material
z
PICmicro 18C MCU Family Reference Manual
(DS39500A)
PIC18F4520 Data Sheet
(DS39631E)
PICDEM2 Plus Users Guide
(DS51275D)
More than 100 App notes, design guides and other reference
material!
www.microchip.com
TLS2118
Slide
209
Resources
Books Compiler Specific
z
Current Edition (PDF)

Microchip Technology
DS51288J
http://www.microchip.com
MPLAB C18
Compiler
Users Guide
z
MPASM
MPLINK
MPLIB
Users Guide
MPLAB C18 C Compiler User's Guide
MPASM MPLINK and MPLIB User's Guide

Current Edition (PDF)
Microchip Technology
DS33014K
http://www.microchip.com
The older books on C are much more relevant to embedded C

programming since they were written back when PCs and other computers
had limited resources and programmers had to manage them carefully.
TLS2118
Slide
210
Reference Books
Books on PIC18
z
Programming and Customizing PIC Microcontrollers

3rd Edition (September 27, 2007)
Myke Predko
ISBN-10: 0071472876
ISBN-13: 987-0071472876
Embedded Design with the PIC18F452 Microcontroller

1th Edition (August 15, 2002)
John B. Peatman
ISBN-10: 0130462138
ISBN-13: 978-0130462138
PIC microcontrollers and Embedded Systems

4th Edition (October 19, 2006)
Muhammad Ali Mazidi , Rolin McKinlay, Danny Causey
ISBN-10: 0131194045
ISBN-13: 978-0131194045
TLS2118
Slide
211
Thank You
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC, KeeLoq, KeeLoq logo,
MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered
trademarks of Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB,
SEEVAL and The Embedded Control Solutions Company are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HITIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation,
PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode,
Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their respective
companies.
2010, Microchip Technology Incorporated, All Rights Reserved.
TLS2118
Slide
213

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Microchip PIC18 MCU

2011 Microchip Technology Incorporated. All Rights Reserved.

MPLAB IDE v8.70 ()

MPLAB C18 Compiler Users Guide & Library

2011 Microchip Technology Incorporated. All Rights Reserved.

2011 Microchip Technology Incorporated. All Rights Reserved.

Integrated Development Environment

2011 Microchip Technology Incorporated. All Rights Reserved.

Full-speed real-time emulation with run/halt, step

2011 Microchip Technology Incorporated. All Rights Reserved.

Full PIC portfolio support

Can provide limited target power (100mA)

Completely USB powered

Validate interface and connection integrity

2011 Microchip Technology Incorporated. All Rights Reserved.

MPLAB REAL ICE Probe Kit

MPLAB IDE compatible

Standard Driver Board

Real Time Data Watchpoints

USB High Speed Connection

MPLAB REAL ICE List $499.98

2011 Microchip Technology Incorporated. All Rights Reserved.

High and Full

High and Full

External power supply required

Programmable VPP Range

VPP Current Supplied

VDD Current Supplied

VDD drain from target

Over voltage Protection

Over current Protection

2011 Microchip Technology Incorporated. All Rights Reserved.

Selection criteria / Recomm. tool

Faster daily debug / programming

Need Vpp = 8.5V

PIC18 std (non J, non K)

Need Vpp = 8.5V

PIC18 fast programming

max 15s up to 128KB

16 bits fast programming

max 15s up to 256KB

32 bits fast programming

max 15s up to 512KB

Real-Time variables watch

PIC18J, 16/32 bits except dsPIC30

Real-Time measurement of program

PIC18, 16/32 bits except dsPIC30

PIC18, 16/32 bits except dsPIC30

Real-Time Data Monitoring (RTDM)

TRACE (Ports / SPI)

PIC18, 16 bits (not PIC32)

External breakpoint Trigger

For all PICs

2011 Microchip Technology Incorporated. All Rights Reserved.

2011 Microchip Technology Incorporated. All Rights Reserved.

2011 Microchip Technology Incorporated. All Rights Reserved.

Debug & Prog.

I2C & SPI

2011 Microchip Technology Incorporated. All Rights Reserved.

SW3 & SW2

2011 Microchip Technology Incorporated. All Rights Reserved.

Assembly Source Files