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IV CYCLE PROGRAMS

// relay//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity relay is
Port ( p : in std_logic;
m : out std_logic);
end realy;
architecture Behavioral of relay is
begin
process(p)
begin
if (p='1')then
m<='1';
else
m<='0';
end if;
end process;
end Behavioral;

// rw_dac //
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rw_dac is
Port ( clk,rst : in std_logic;
op : out std_logic_vector(7 downto 0));
end rw_dac;
architecture Behavioral of rw_dac is
signal q: std_logic_vector(7 downto 0);
begin
process(clk,rst)
begin
if(rst='0') then q<=(others=>'0');
elsif (clk'event and clk='1') then
q<= q+1;

----for step q<=q+8

end if;

end process;

op<=q;
end Behavioral;

// tri_ dac//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tri_dac is
Port ( clk,rst : in std_logic;
op : out std_logic_vector(7 downto 0));
end tri_dac;
architecture Behavioral of tri_dac is
signal q: std_logic_vector(7 downto 0);
signal ud:std_logic:='0';
begin
process(clk,rst)
begin
if(rst='0') then q<=(others=>'0');
elsif (clk'event and clk='1') then
if (ud='0')then q<=q+1;
elsif (ud='1')then q<=q-1;
end if;
end if;
end process;
op<=q;
process (clk)
begin
if (clk'event and clk='1')then
if(q="11111110")then ud<='1';
elsif(q="00000001")then ud<='0';
end if;
end if;
end process;
end Behavioral;

// DC MOTOR //
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TKBDCM is
Port ( psw : in std_logic_vector(2 downto 0);
pdcm : out std_logic;
p100k : in std_logic );
end TKBDCM;
architecture behavioral of TKBDCM is
signal sclkdiv : std_logic_vector(11 downto 0);
begin
-- count upto 3000
process(p100k)
begin--+
if( rising_edge(p100k)) then
sclkdiv <= sclkdiv+1;
end if;
if(sclkdiv = "101110111000") then
sclkdiv <= "000000000000";
end if;
end process;
process(psw,sclkdiv)
variable vdcm : bit;
begin
if(sclkdiv = "000000000000") then
vdcm := '1';
end if;
-- 1f4, 320, 44c, 578, 6a4, 7d0, 8fc, 9c4
if(psw
elsif(psw
elsif(psw
elsif(psw
elsif(psw
elsif(psw
elsif(psw
elsif(psw
end if;

=
=
=
=
=
=
=
=

"000"
"001"
"010"
"011"
"100"
"101"
"110"
"111"

and
and
and
and
and
and
and
and

sclkdiv
sclkdiv
sclkdiv
sclkdiv
sclkdiv
sclkdiv
sclkdiv
sclkdiv

=
=
=
=
=
=
=
=

"000111110100")
"001100100000")
"010001001100")
"010101111000")
"011010100100")
"011111010000")
"100011111100")
"100111000100")

if(vdcm = '1') then pdcm <= '1';


else pdcm <= '0';
end if;
end process;

then
then
then
then
then
then
then
then

vdcm
vdcm
vdcm
vdcm
vdcm
vdcm
vdcm
vdcm

:=
:=
:=
:=
:=
:=
:=
:=

'0';
'0';
'0';
'0';
'0';
'0';
'0';
'0';

end behavioral;

// V CYCLE PROGRAMS
//HEXKEYPAD
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TKBHKY is
Port ( pkeyret : in std_logic_vector(3 downto 0);
pkeyscn : out std_logic_vector(3 downto 0);
pdspseg : out std_logic_vector (6 downto 0);
pdspmux : out std_logic_vector (3 downto 0);
pclk100K : in std_logic
);
end TKBHKY;
architecture behavioral of TKBHKY is
signal skeyval : integer range 0 to 15;
signal skeyhit : std_logic;
signal skeyscn : std_logic_vector(3 downto 0);
signal sclkdiv : std_logic_vector(7 downto 0);
signal skeyclk : std_logic;
begin
-------- process clk divider
process(pclk100k)
begin
if( rising_edge(pclk100k)) then
sclkdiv <= sclkdiv+1;
end if;
skeyclk <= sclkdiv(6);
end process;
-------- process for key scan clkscan
process(skeyclk)
begin
if(rising_edge(skeyclk)) then
if skeyscn = "1110"
then
elsif skeyscn = "1101" then
elsif skeyscn = "1011" then
elsif skeyscn = "0111" then
else skeyscn <= "1110";
end if;
end if;
pkeyscn <= skeyscn;
end process;
--------- process keypress
process(pkeyret)
begin

skeyscn
skeyscn
skeyscn
skeyscn

<=
<=
<=
<=

"1101";
"1011";
"0111";
"1110";

case pkeyret is
when "1110"
when "1101"
when "1011"
when "0111"
when others
end case;
end process;

=>
=>
=>
=>
=>

skeyhit
skeyhit
skeyhit
skeyhit
skeyhit

<=
<=
<=
<=
<=

'1';
'1';
'1';
'1';
'0';

--------- process keyval


process(skeyhit)
begin
if( rising_edge(skeyhit)) then
if(skeyscn = "1110" and pkeyret = "1110")
then skeyval <= 0;
elsif(skeyscn = "1110" and pkeyret = "1101")
then skeyval <= 1;
elsif(skeyscn = "1110" and pkeyret = "1011")
then skeyval <= 2;
elsif(skeyscn = "1110" and pkeyret = "0111")
then skeyval <= 3;
elsif(skeyscn = "1101" and pkeyret = "1110")
then skeyval <= 4;
elsif(skeyscn = "1101" and pkeyret = "1101")
then skeyval <= 5;
elsif(skeyscn = "1101" and pkeyret = "1011")
then skeyval <= 6;
elsif(skeyscn = "1101" and pkeyret = "0111")
then skeyval <= 7;
elsif(skeyscn = "1011" and pkeyret = "1110")
then skeyval <= 8;
elsif(skeyscn = "1011" and pkeyret = "1101")
then skeyval <= 9;
elsif(skeyscn = "1011" and pkeyret = "1011")
then skeyval <= 10;
elsif(skeyscn = "1011" and pkeyret = "0111")
then skeyval <= 11;
elsif(skeyscn = "0111" and pkeyret = "1110")
then skeyval <= 12;
elsif(skeyscn = "0111" and pkeyret = "1101")
then skeyval <= 13;
elsif(skeyscn = "0111" and pkeyret = "1011")
then skeyval <= 14;
elsif(skeyscn = "0111" and pkeyret = "0111")
then skeyval <= 15;
end if;
end if;
end process;
-------- process display 7seg
process(skeyval)
type tseg7 is array(0 to 15) of std_logic_vector (6 downto 0);
constant segval : tseg7 :=
("0111111","0000110","1011011","1001111","1100110","1101101","1111101",
"0000111","1111111","1101111","1110111","1111100","1011000","1011110","
1111001","1110001");
begin
pdspseg <= segval(skeyval);

pdspmux <= "1101";


end process;
end behavioral;
#PINLOCK_BEGIN HEXKEYPAD
#Mon Apr 26 15:30:27 2010
NET "pclk100K"

LOC =

"S:PIN55";

NET
NET
NET
NET

"pkeyret<0>"
"pkeyret<1>"
"pkeyret<2>"
"pkeyret<3>"

LOC
LOC
LOC
LOC

=
=
=
=

"S:PIN1";
"S:PIN2";
"S:PIN3";
"S:PIN4";

NET
NET
NET
NET

"pkeyscn<0>"
"pkeyscn<1>"
"pkeyscn<2>"
"pkeyscn<3>"

LOC
LOC
LOC
LOC

=
=
=
=

"S:PIN5";
"S:PIN6";
"S:PIN7";
"S:PIN9";

NET
NET
NET
NET

"pdspmux<0>"
"pdspmux<1>"
"pdspmux<2>"
"pdspmux<3>"

LOC
LOC
LOC
LOC

=
=
=
=

"S:PIN14";
"S:PIN15";
"S:PIN17";
"S:PIN18";

NET
NET
NET
NET
NET
NET
NET

"pdspseg<0>"
"pdspseg<1>"
"pdspseg<2>"
"pdspseg<3>"
"pdspseg<4>"
"pdspseg<5>"
"pdspseg<6>"

LOC
LOC
LOC
LOC
LOC
LOC
LOC

=
=
=
=
=
=
=

"S:PIN31";
"S:PIN32";
"S:PIN33";
"S:PIN34";
"S:PIN35";
"S:PIN36";
"S:PIN37";

#PINLOCK_END

//ELEVATOR
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TKBELE is
Port ( pkeyret : in std_logic_vector(3 downto 0);
pkeyscn : out std_logic_vector(3 downto 0);
pdspseg : out std_logic_vector (6 downto 0);
pdspmux : out std_logic_vector (3 downto 0);
pclk100K : in std_logic
);
end TKBELE;
architecture behavioral of TKBELE is
signal
signal
signal
signal
signal

scurflr,snxtflr,skeyflr : integer range 0 to 15;


sdir, skeyhit : std_logic;
skeyscn : std_logic_vector(3 downto 0);
sclkdiv : std_logic_vector(15 downto 0);
sflrclk,skeyclk : std_logic;

begin
------- process clk divider
-process(pclk100k)
begin
if( rising_edge(pclk100k)) then
sclkdiv <= sclkdiv+1;
end if;
skeyclk <= sclkdiv(6);
sflrclk <= sclkdiv(15);
end process;
-------- process for key scan clkscan
process(skeyclk)
begin
if(rising_edge(skeyclk)) then
if skeyscn = "1110"
then
elsif skeyscn = "1101" then
elsif skeyscn = "1011" then
elsif skeyscn = "0111" then
else skeyscn <= "1110";
end if;
end if;
pkeyscn <= skeyscn;
end process;
-------- process keypress
process(pkeyret)
begin

skeyscn
skeyscn
skeyscn
skeyscn

<=
<=
<=
<=

"1101";
"1011";
"0111";
"1110";

case pkeyret is
when "1110"
when "1101"
when "1011"
when "0111"
when others
end case;
end process;

=>
=>
=>
=>
=>

skeyhit
skeyhit
skeyhit
skeyhit
skeyhit

<=
<=
<=
<=
<=

'1';
'1';
'1';
'1';
'0';

--------- process keyval


process(skeyhit)
begin
if( rising_edge(skeyhit)) then
if(skeyscn = "1110" and pkeyret = "1110")
then skeyflr <= 0;
elsif(skeyscn = "1110" and pkeyret = "1101")
then skeyflr <= 1;
elsif(skeyscn = "1110" and pkeyret = "1011")
then skeyflr <= 2;
elsif(skeyscn = "1110" and pkeyret = "0111")
then skeyflr <= 3;
elsif(skeyscn = "1101" and pkeyret = "1110")
then skeyflr <= 4;
elsif(skeyscn = "1101" and pkeyret = "1101")
then skeyflr <= 5;
elsif(skeyscn = "1101" and pkeyret = "1011")
then skeyflr <= 6;
elsif(skeyscn = "1101" and pkeyret = "0111")
then skeyflr <= 7;
elsif(skeyscn = "1011" and pkeyret = "1110")
then skeyflr <= 8;
elsif(skeyscn = "1011" and pkeyret = "1101")
then skeyflr <= 9;
elsif(skeyscn = "1011" and pkeyret = "1011")
then skeyflr <= 10;
elsif(skeyscn = "1011" and pkeyret = "0111")
then skeyflr <= 11;
elsif(skeyscn = "0111" and pkeyret = "1110")
then skeyflr <= 12;
elsif(skeyscn = "0111" and pkeyret = "1101")
then skeyflr <= 13;
elsif(skeyscn = "0111" and pkeyret = "1011")
then skeyflr <= 14;
elsif(skeyscn = "0111" and pkeyret = "0111")
then skeyflr <= 15;
end if;
end if;
end process;

-------- process floor motion


process(sflrclk)
begin
if(rising_edge(sflrclk)) then
if(not (skeyflr = scurflr) ) then
if(skeyflr > scurflr) then scurflr <= scurflr+1;
else scurflr <= scurflr-1;

end if;
end if;
end if;
end process;
-------- process display 7seg
process(scurflr)
type tseg7 is array(0 to 15) of std_logic_vector (6 downto 0);
constant segval : tseg7 :=
("0111111","0000110","1011011","1001111","1100110","1101101","1111101",
"0000111","1111111","1101111","1110111","1111100","1011000","1011110","
1111001","1110001");
begin
pdspseg <= segval(scurflr);
pdspmux <= "1110";
end process;
end behavioral;
#pin2ucf #The following constraints were newly added
NET "pclk100K" LOC = P55;
NET
NET
NET
NET

"pkeyscn<0>"
"pkeyscn<1>"
"pkeyscn<2>"
"pkeyscn<3>"

LOC
LOC
LOC
LOC

=
=
=
=

P5;
P6;
P7;
P9;

NET
NET
NET
NET

"pkeyret<0>"
"pkeyret<1>"
"pkeyret<2>"
"pkeyret<3>"

LOC
LOC
LOC
LOC

=
=
=
=

P1;
P2;
P3;
P4;

NET
NET
NET
NET

"pdspmux<0>"
"pdspmux<1>"
"pdspmux<2>"
"pdspmux<3>"

LOC
LOC
LOC
LOC

=
=
=
=

P14;
P15;
P17;
P18;

NET
NET
NET
NET
NET
NET
NET

"pdspseg<0>"
"pdspseg<1>"
"pdspseg<2>"
"pdspseg<3>"
"pdspseg<4>"
"pdspseg<5>"
"pdspseg<6>"

LOC
LOC
LOC
LOC
LOC
LOC
LOC

=
=
=
=
=
=
=

P31;
P32;
P33;
P34;
P35;
P36;
P37;

ELEVATOR

--------------------------------------------------------------------------------- STEPPER MOTOR


-- Company:
-- Engineer:
--- Create Date:
14:05:57 03/30/2010
-- Design Name:
-- Module Name:
stp_motor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TKBSTP is
Port ( pkeycol : in std_logic_vector (3 downto 0);
pkeyrow : out std_logic_vector (3 downto 0);
pstpsig : out std_logic_vector(3 downto 0);
pclk100K : in std_logic );
end TKBSTP;
architecture behavioral of TKBSTP is
signal sclkdiv : std_logic_vector(20 downto 0);
signal sstpcnt : std_logic_vector(1 downto 0);
signal sstpclk,skeyhit : std_logic;
signal skeysts :std_logic_vector (3 downto 0);
begin
------- clkdivider
process(pclk100k)
begin
if( rising_edge(pclk100k)) then
sclkdiv <= sclkdiv+1;
end if;
sstpclk <= sclkdiv(15);
end process;

-------- key process


-------- out key row = 0 check key col
pkeyrow <= "0000";
process(pkeycol)
begin
if(pkeycol(0) = '0' or
pkeycol(1) = '0' or
pkeycol(2) = '0' or
pkeycol(3) = '0' ) then skeyhit <= '0';
else skeyhit <= '1';
end if;
end process;
-------- latch key press
process(skeyhit)
begin
if( falling_edge(skeyhit)) then
skeysts <= pkeycol;
end if;
end process;
-------- 4 step counter
process(sstpclk)
begin
if(rising_edge(sstpclk)) then
if(skeysts(0) = '0') then
sstpcnt <= sstpcnt+1;
elsif(skeysts(1) = '0') then
sstpcnt <= sstpcnt-1;
end if;
end if;
end process;
------ outputs signal pstpsig = D, C, B & A for stepper motor
------ TKBase from ucf file
= 14,13,12, 11
------ als stepper controller = 4, 6, 3 & 5
process(sstpcnt)
begin
if
(sstpcnt
elsif(sstpcnt
elsif(sstpcnt
elsif(sstpcnt
end if;
end process;
end behavioral;

=
=
=
=

"00")
"01")
"10")
"11")

then
then
then
then

pstpsig
pstpsig
pstpsig
pstpsig

<=
<=
<=
<=

"0001";
"0111";
"1110";
"1000";

#pin2ucf #The following constraints were newly added STEPPER MOTOR


NET "pclk100K" LOC = P20;
NET
NET
NET
NET

"pstpsig<0>"
"pstpsig<1>"
"pstpsig<2>"
"pstpsig<3>"

LOC
LOC
LOC
LOC

=
=
=
=

P14;
P15;
P17;
P18;

NET
NET
NET
NET

"pkeycol<0>"
"pkeycol<1>"
"pkeycol<2>"
"pkeycol<3>"

LOC
LOC
LOC
LOC

=
=
=
=

P1;
P2;
P3;
P4;

NET
NET
NET
NET

"pkeyrow<0>"
"pkeyrow<1>"
"pkeyrow<2>"
"pkeyrow<3>"

LOC
LOC
LOC
LOC

=
=
=
=

P5;
P6;
P7;
P9;

---------------------------------------------------------------------------------- Company:
-- Engineer:
--- Create Date:
16:02:33 04/21/2010
-- Design Name:
-- Module Name:
movdsp - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity movdsp is
Port ( pdspseg : out
pdspmux : out
pclk100k : in
end movdsp;

STD_LOGIC_VECTOR (6 downto 0);


STD_LOGIC_VECTOR (3 downto 0);
STD_LOGIC);

architecture Behavioral of movdsp is


signal
signal
signal
signal
signal

sclkdiv : std_logic_vector(15 downto 0);


sdspnum : integer range 0 to 15;
sdspseq : std_logic_vector(2 downto 0);
sdspmux : std_logic_vector(3 downto 0);
smuxclk,sdspstp : std_logic;

begin
-------- process clk divider
process(pclk100k)
begin
if( rising_edge(pclk100k)) then
sclkdiv <= sclkdiv+1;
end if;

smuxclk <=
sdspseq(0)
sdspseq(1)
sdspseq(2)
sdspstp <=
end process;

sclkdiv(0);
<= sclkdiv(1);
<= sclkdiv(2);
<= sclkdiv(3);
sclkdiv(15);

------ process pdspmux


process(sdspseq)
begin
if(sdspseq = "000") then sdspmux <=
elsif(sdspseq = "010") then sdspmux
elsif(sdspseq = "100") then sdspmux
elsif(sdspseq = "110") then sdspmux
else sdspmux <= "1111";
end if;
pdspmux <= sdspmux;
end process;

"1110";
<= "1101";
<= "1011";
<= "0111";

------ process muxdisp


process(sdspmux)
type tseg7 is array(0 to 15) of std_logic_vector (6 downto 0);
constant segval : tseg7 :=
("0000000","0000000","0000000","0000000",
"1111100","0000110","1111000","1000000",
"0110000","1011011","1001111","1100110",
"0000000","0000000","0000000","0000000");
begin
if(sdspmux = "1110") then pdspseg <= segval(sdspnum);
elsif(sdspmux = "1101") then pdspseg <=
segval(sdspnum+1);
elsif(sdspmux = "1011") then pdspseg <=
segval(sdspnum+2);
elsif(sdspmux = "0111") then pdspseg <=
segval(sdspnum+3);
else pdspseg <= "0000000";
end if;
end process;
------ process dspno
process(sdspstp)
begin
if(rising_edge(sdspstp)) then
sdspnum <= sdspnum+1;
end if;
end process;

end Behavioral;

#pin2ucf - Wed
#The following constraints were newly added moving dsp
NET
NET
NET
NET

"pdspmux<0>"
"pdspmux<1>"
"pdspmux<2>"
"pdspmux<3>"

LOC
LOC
LOC
LOC

=
=
=
=

P14;
P15;
P17;
P18;

NET "pclk100k"

LOC = P52;

NET
NET
NET
NET
NET
NET
NET

LOC
LOC
LOC
LOC
LOC
LOC
LOC

"pdspseg<0>"
"pdspseg<1>"
"pdspseg<2>"
"pdspseg<3>"
"pdspseg<4>"
"pdspseg<5>"
"pdspseg<6>"

=
=
=
=
=
=
=

P31;
P32;
P33;
P34;
P35;
P36;
P37;

DAC
FPGA/DAC

MOV DISPLAY
CPLD/MUX/SEG

2------CLK

2------MUX1

3------RST

3-----MUX2

4------21

4-----MUX3

5------22

5-----MUX4

7------19

31----A

9------20

32----B

10----17

33----C

11----18

34----D

12----15

35----E

13----16

36----F

26 PIN OF DAC
TO GND
OF FPGA

37----G
52---- CLK(100)

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