--------------------------------------------------------------------------------- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.

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Vendor: Xilinx
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Version : 12.1
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Application : sch2hdl
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Filename : main.vhf
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Timestamp : 01/05/2016 09:13:43
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-- \___\/\___\
---Command: sch2hdl -sympath C:/Users/Waseem/Desktop/hilbert/ipcore_dir -intstyle
ise -family virtex6 -flat -suppress -vhdl C:/Users/Waseem/Desktop/hilbert/main.
vhf -w C:/Users/Waseem/Desktop/hilbert/main.sch
--Design Name: main
--Device: virtex6
--Purpose:
-This vhdl netlist is translated from an ECS schematic. It can be
-synthesized and simulated, but it should not be modified.
-library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity main is
port ( clk
fwd_inv
fwd_invwe
fwd_inv1
img_in
real_in
receprocal
unload
blk_exp
blk_exp1
bzy
bzy1
done
done1
edone
edone1
in_exp
in_exp1
out_exp
out_exp1
phase
rfd
rfd1
end main;

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in
in
in
in
in
in
in
in
out
out
out
out
out
out
out
out
out
out
out
out
out
out
out

std_logic;
std_logic;
std_logic;
std_logic;
std_logic_vector
std_logic_vector
std_logic_vector
std_logic;
std_logic_vector
std_logic_vector
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic_vector
std_logic_vector
std_logic_vector
std_logic_vector
std_logic_vector
std_logic;
std_logic);

(31 downto 0);

(31 downto 0);
(1 downto 0);
(4 downto 0);
(4 downto 0);

(13
(13
(13
(13
(33

downto
downto
downto
downto
downto

0);
0);
0);
0);
0);

architecture BEHAVIORAL of main is

signal XLXN_18
: std_logic;
signal XLXN_28
: std_logic_vector (31 downto 0);
signal XLXN_29
: std_logic_vector (31 downto 0);
signal XLXN_30
: std_logic;

signal XLXN_34
: std_logic;
signal XLXN_39
: std_logic_vector (33 downto 0);
signal XLXN_40
: std_logic_vector (33 downto 0);
signal XLXN_41
: std_logic_vector (31 downto 0);
signal XLXN_49
: std_logic_vector (33 downto 0);
signal XLXN_50
: std_logic_vector (33 downto 0);
signal XLXN_84
: std_logic_vector (33 downto 0);
signal XLXN_85
: std_logic_vector (33 downto 0);
signal XLXN_86
: std_logic;
signal XLXN_87
: std_logic;
signal XLXN_89
: std_logic;
signal XLXN_90
: std_logic;
signal XLXN_91
: std_logic_vector (33 downto 0);
signal XLXN_93
: std_logic;
signal XLXN_96
: std_logic_vector (33 downto 0);
signal XLXN_99
: std_logic_vector (31 downto 0);
signal XLXN_100
: std_logic_vector (31 downto 0);
signal XLXN_101
: std_logic_vector (47 downto 0);
signal XLXN_103
: std_logic_vector (1 downto 0);
signal XLXN_104
: std_logic_vector (31 downto 0);
signal XLXN_105
: std_logic_vector (1 downto 0);
signal XLXN_106
: std_logic_vector (31 downto 0);
signal XLXN_107
: std_logic_vector (33 downto 0);
signal XLXN_108
: std_logic_vector (33 downto 0);
signal XLXN_109
: std_logic_vector (31 downto 0);
signal XLXN_110
: std_logic_vector (31 downto 0);
signal receprocal_DUMMY : std_logic_vector (1 downto 0);
signal real_in_DUMMY
: std_logic_vector (31 downto 0);
component fft
port ( xn_re
: in
std_logic_vector (31 downto 0);
xn_im
: in
std_logic_vector (31 downto 0);
start
: in
std_logic;
unload
: in
std_logic;
fwd_inv
: in
std_logic;
fwd_inv_we : in
std_logic;
clk
: in
std_logic;
xk_re
: out std_logic_vector (31 downto 0);
xk_im
: out std_logic_vector (31 downto 0);
xn_index : out std_logic_vector (13 downto 0);
xk_index : out std_logic_vector (13 downto 0);
rfd
: out std_logic;
busy
: out std_logic;
dv
: out std_logic;
edone
: out std_logic;
done
: out std_logic;
blk_exp
: out std_logic_vector (4 downto 0));
end component;
component ifft
port ( xn_re
xn_im
start
unload
fwd_inv
fwd_inv_we
clk
xk_re
xk_im
xn_index
xk_index

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in
in
in
in
in
in
in
out
out
out
out

std_logic_vector
std_logic_vector
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic_vector
std_logic_vector
std_logic_vector
std_logic_vector

(33 downto 0);

(33 downto 0);

(33
(33
(13
(13

downto
downto
downto
downto

0);
0);
0);
0);

rfd
busy
dv
edone
done
blk_exp
end component;
component output
port ( start :
clk :
r_in :
i_in :
r_out :
i_out :
end component;

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out
out
out
out
out
out

in
in
in
in
out
out

component half_fft
port ( clk
start
fft_in_real
fft_in_img
data_valid
fft_out_real
fft_out_img
end component;

std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic_vector (4 downto 0));

std_logic;
std_logic;
std_logic_vector
std_logic_vector
std_logic_vector
std_logic_vector

:
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in
in
in
in
out
out
out

(33
(33
(33
(33

downto
downto
downto
downto

std_logic;
std_logic;
std_logic_vector
std_logic_vector
std_logic;
std_logic_vector
std_logic_vector

0);
0);
0);
0));

(31 downto 0);

(31 downto 0);
(31 downto 0);
(31 downto 0));

component multiply_by_2
port ( a : in std_logic_vector (31 downto 0);
p : out std_logic_vector (33 downto 0));
end component;
component dc_removal
port ( clk
: in
in1
: in
start : out
out_dc : out
end component;

std_logic;
std_logic_vector (47 downto 0);
std_logic;
std_logic_vector (31 downto 0));

component Acumulator
port ( b : in std_logic_vector (31 downto 0);
clk : in
std_logic;
q : out std_logic_vector (47 downto 0));
end component;
component Fixed_point_32
port ( clk
:
P_34
:
hilbert_img_34 :
x_sign
:
y_sign
:
x
:
y
:
end component;

in
in
in
out
out
out
out

std_logic;
std_logic_vector
std_logic_vector
std_logic;
std_logic;
std_logic_vector
std_logic_vector

(33 downto 0);

(33 downto 0);
(31 downto 0);
(31 downto 0));

component Divider_reciprocal
port ( clk
: in
std_logic;
dividend : in std_logic_vector (1 downto 0);
divisor
: in std_logic_vector (31 downto 0);
rfd
: out std_logic;

quotient : out
fractional : out
end component;

std_logic_vector (1 downto 0);

std_logic_vector (31 downto 0));

component combine_quot_and_fraction
port ( clk
: in
std_logic;
quot
: in
std_logic_vector (1 downto 0);
fraction
: in
std_logic_vector (31 downto 0);
receprocal_result : out std_logic_vector (33 downto 0));
end component;
component atan_block
port ( x_in
:
y_in
:
clk
:
phase_out :
end component;

in
in
in
out

std_logic_vector (33 downto 0);

std_logic_vector (33 downto 0);
std_logic;
std_logic_vector (33 downto 0));

component shift_register
port ( x : in
std_logic;
y : in
std_logic;
clk : in
std_logic;
r : out std_logic;
i : out std_logic);
end component;
component atan_to_atan2
port ( real_sign : in
img_sign
: in
clk
: in
phase_atan : in
phase_atan2 : out
end component;
component Derivative
port ( clk
: in
phase_in : in
phase_out : out
end component;

std_logic;
std_logic;
std_logic;
std_logic_vector (33 downto 0);
std_logic_vector (33 downto 0));

std_logic;
std_logic_vector (33 downto 0);
std_logic_vector (33 downto 0));

begin
receprocal_DUMMY(1 downto 0) <= receprocal(1 downto 0);
real_in_DUMMY(31 downto 0) <= real_in(31 downto 0);
XLXI_1 : fft
port map (clk=>clk,
fwd_inv=>fwd_inv,
fwd_inv_we=>fwd_invwe,
start=>XLXN_93,
unload=>unload,
xn_im(31 downto 0)=>img_in(31 downto 0),
xn_re(31 downto 0)=>XLXN_41(31 downto 0),
blk_exp(4 downto 0)=>blk_exp(4 downto 0),
busy=>bzy,
done=>done,
dv=>XLXN_30,
edone=>edone,
rfd=>rfd,
xk_im(31 downto 0)=>XLXN_29(31 downto 0),
xk_index(13 downto 0)=>out_exp(13 downto 0),
xk_re(31 downto 0)=>XLXN_28(31 downto 0),

xn_index(13 downto 0)=>in_exp(13 downto 0));

XLXI_3 : ifft
port map (clk=>clk,
fwd_inv=>fwd_inv1,
fwd_inv_we=>fwd_invwe,
start=>XLXN_34,
unload=>unload,
xn_im(33 downto 0)=>XLXN_108(33 downto 0),
xn_re(33 downto 0)=>XLXN_107(33 downto 0),
blk_exp(4 downto 0)=>blk_exp1(4 downto 0),
busy=>bzy1,
done=>done1,
dv=>XLXN_18,
edone=>edone1,
rfd=>rfd1,
xk_im(33 downto 0)=>XLXN_40(33 downto 0),
xk_index(13 downto 0)=>out_exp1(13 downto 0),
xk_re(33 downto 0)=>XLXN_39(33 downto 0),
xn_index(13 downto 0)=>in_exp1(13 downto 0));
XLXI_4 : output
port map (clk=>clk,
i_in(33 downto 0)=>XLXN_40(33 downto 0),
r_in(33 downto 0)=>XLXN_39(33 downto 0),
start=>XLXN_18,
i_out(33 downto 0)=>XLXN_49(33 downto 0),
r_out(33 downto 0)=>XLXN_50(33 downto 0));
XLXI_6 : half_fft
port map (clk=>clk,
fft_in_img(31 downto 0)=>XLXN_29(31 downto 0),
fft_in_real(31 downto 0)=>XLXN_28(31 downto 0),
start=>XLXN_30,
data_valid=>XLXN_34,
fft_out_img(31 downto 0)=>XLXN_100(31 downto 0),
fft_out_real(31 downto 0)=>XLXN_99(31 downto 0));
XLXI_7 : multiply_by_2
port map (a(31 downto 0)=>XLXN_99(31 downto 0),
p(33 downto 0)=>XLXN_107(33 downto 0));
XLXI_8 : multiply_by_2
port map (a(31 downto 0)=>XLXN_100(31 downto 0),
p(33 downto 0)=>XLXN_108(33 downto 0));
XLXI_9 : dc_removal
port map (clk=>clk,
in1(47 downto 0)=>XLXN_101(47 downto 0),
out_dc(31 downto 0)=>XLXN_41(31 downto 0),
start=>XLXN_93);
XLXI_10 : Acumulator
port map (clk=>clk,
b(31 downto 0)=>real_in_DUMMY(31 downto 0),
q(47 downto 0)=>XLXN_101(47 downto 0));
XLXI_11 : Fixed_point_32
port map (clk=>clk,
hilbert_img_34(33 downto 0)=>XLXN_49(33 downto 0),

P_34(33 downto 0)=>XLXN_50(33 downto 0),

x(31 downto 0)=>XLXN_109(31 downto 0),
x_sign=>XLXN_86,
y(31 downto 0)=>XLXN_110(31 downto 0),
y_sign=>XLXN_87);
XLXI_12 : Divider_reciprocal
port map (clk=>clk,
dividend(1 downto 0)=>receprocal_DUMMY(1 downto 0),
divisor(31 downto 0)=>XLXN_109(31 downto 0),
fractional(31 downto 0)=>XLXN_104(31 downto 0),
quotient(1 downto 0)=>XLXN_103(1 downto 0),
rfd=>open);
XLXI_13 : Divider_reciprocal
port map (clk=>clk,
dividend(1 downto 0)=>receprocal_DUMMY(1 downto 0),
divisor(31 downto 0)=>XLXN_110(31 downto 0),
fractional(31 downto 0)=>XLXN_106(31 downto 0),
quotient(1 downto 0)=>XLXN_105(1 downto 0),
rfd=>open);
XLXI_14 : combine_quot_and_fraction
port map (clk=>clk,
fraction(31 downto 0)=>XLXN_104(31 downto 0),
quot(1 downto 0)=>XLXN_103(1 downto 0),
receprocal_result(33 downto 0)=>XLXN_84(33 downto 0));
XLXI_15 : combine_quot_and_fraction
port map (clk=>clk,
fraction(31 downto 0)=>XLXN_106(31 downto 0),
quot(1 downto 0)=>XLXN_105(1 downto 0),
receprocal_result(33 downto 0)=>XLXN_85(33 downto 0));
XLXI_16 : atan_block
port map (clk=>clk,
x_in(33 downto 0)=>XLXN_85(33 downto 0),
y_in(33 downto 0)=>XLXN_84(33 downto 0),
phase_out(33 downto 0)=>XLXN_91(33 downto 0));
XLXI_17 : shift_register
port map (clk=>clk,
x=>XLXN_86,
y=>XLXN_87,
i=>XLXN_90,
r=>XLXN_89);
XLXI_18 : atan_to_atan2
port map (clk=>clk,
img_sign=>XLXN_90,
phase_atan(33 downto 0)=>XLXN_91(33 downto 0),
real_sign=>XLXN_89,
phase_atan2(33 downto 0)=>XLXN_96(33 downto 0));
XLXI_19 : Derivative
port map (clk=>clk,
phase_in(33 downto 0)=>XLXN_96(33 downto 0),
phase_out(33 downto 0)=>phase(33 downto 0));
end BEHAVIORAL;