PWM (full voltage on and off) through low pass filter, we get smaller voltage!!!

!
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Kp -> reduces the rise time of the close lopp system responses. It also reduces
the steady state error (but it doesn't elliminate the steady state error).
Ki -> it elliminates the steady state error for constant or step input (note not
ramp, or parabolla). But it makes the transient erresponse slower.
Kd -> it increases the stability of the syste,, reduces the overshoot and impro
ves the transient response.
effect of PID gains on responses:
=========================================
Kp -> decreases the rise time, increases the overshoot, changes the setlling tim
e by very little and reduces the steady state error.
Ki -> decreases the rise time, increases the overshhot, increases the settling t
ime, eliminates the steady state error.
Kd -> have small chage in rise time, decreases the overshhot, decreases the setl
ling time, no effect of steady state error.
** effect of one gain is depended on other. So they cant be thought as independe
nt.
controller making procedure:
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1)
2)
3)
4)
5)

Obtain an open loop response and determine what needs to be improved.

add proportional control to improve the rise time.
Add a derivative control to improve the overshoot.
Add an integral control to eliminate the steady-state error.
Adjust each of Kp, Ki, and Kd until you obtain a desired overall response.

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-> higher bandwidth (0 dB crossover of the open-loop) results in a faster rise t
ime.
-> higher phase margin reduces the overshoot and improves the system stability.
=========================================================
-> root locus is a plot of location off possible closed loop poles with proporti
onal ain k and unity feedback
-> dominent pole has the biggest effect on the performance of any system.
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-> The gain margin is defined as the change in open-loop gain required to make t
he system unstable.
-> The phase margin is defined as the change in open-loop phase shift required t
o make a closed-loop
system unstable.
-> Systems with greater gain margins can withstand greater changes in system par
ameters before becoming
unstable in closed-loop.

-> The phase margin also measures the system's tolerance to time delay.
If there is a time delay greater than 180/Wpc in the loop the system will become
unstable in closed-loop.
Wpc is the frequency where phase shift is 180 degree.