Chapter-7

Multiprocessor Architectures
Advanced Computer Architecture

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 Introduction
• Key attributes of “multiprocessors”:-
– Single computer that includes multiple processors
– Processors may communicate at various levels
• Message passing or shared memory
• Multiprocessor and Multicomputer systems
– Similar goal, to achieve concurrency
– Multiple computer system consist of several autonomous computers
– Multiprocessor system is controlled by single operating system which
provides mechanism for interactions among processors
• Architectural models
– Tightly coupled multiprocessor
– Loosely coupled multiprocessor

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 Loosely coupled multiprocessor
• Each processor has its own set of I/O devices and memory
where it accesses most of its instructions and data
• Computer Module: Processor, I/O interface and memory
Input/Output
Local memory (I/O)
Processor (LM)
(P)

Channel and
Arbiter Switch
(CAS)

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 Loosely coupled multiprocessor contd.
• Inter-process communicate over different module happens by
exchange of messages, using message transfer system (MTS)
• Distributed system, degree of coupling is loose
• Degree of memory conflicts is less
LM I/O LM I/O

P P

CAS CAS
Computer Module 0 ………….. Computer Module N-1

Message Transfer System (MTS)

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Loosely coupled multiprocessor contd.
• Inter module communication
– Channel arbiter and switch (CAS)
– Arbiter decide when requests from two or more computer
module collide in accessing a physical segment of MTS
• Message Transfer System (MTS)
– Time based or shared memory
– Important factor that determines performance

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 Tightly coupled multiprocessor
• TCS are used when high speed or real time
processing is desired
• Models:-
– Without private cache
– With private cache

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 Tightly coupled multiprocessor contd.
Interrupt signal
Interconnection network
(ISIN) Input Output
channels
d-1
p-1 . . disks
Processors .. Input/Output . .
.. . .
.. Interconnection network . .
0 (IOPIN) . .
0

Mapped ...... Unmapped Local Memory

Local Memory

Processor Memory
Interconnection network
(PMIN)

Shared Memory Modules

0 ......... l-1 7
Tightly coupled multiprocessor contd.
• Processor Memory Interconnection networks (PMIN)
– Switch which can connect every processor to every memory module
– Typically it is p X l crossbar switch
• Each memory module can process a request from single
processor in one memory cycle
• If two or more processors tries to access same module, then a
conflict occurs which is to be resolved by PMIN
• Methods (to reduce conflicts):-
– Keep l as large as p
– Provide a reserve storage area (Unmapped Local Memory, ULM) for
each processor, reduces inter-PE communication and thereby,
reducing conflicts
• Drawback:-
– Delays in memory reference since it passed through PMIN
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 Tightly coupled multiprocessor contd.
Interrupt signal
Interconnection network
(ISIN) Input Output
channels
d-1
p-1 . . disks
Processors .. Input/Output . .
.. . .
.. Interconnection network . .
0 (IOPIN) . .
Mapped
Local Memory 0
......
Unmapped Local Memory
Private
Caches

Processor Memory
Interconnection network
(PMIN)

Shared Memory Modules

0 ......... l-1 9
Tightly coupled multiprocessor contd.
• Private Caches (PC)
– Helps in reducing delays since memory need not be
accessed if requesting memory word is found in cache
– Traffic through crossbar gets reduced
• Problem: Cache coherence issues
• Memory Map (MM)

– Directs memory references to either ULM or Local Private

Cache

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Tightly coupled multiprocessor contd.
• Processor types
– Homogeneous, if all processors perform same
function
– Heterogeneous, if processors perform different
functions
Note: Two functionally same processor may differ
along other parameters like I/O, memory size,

etc, i.e. they are asymmetric

• Input/Output asymmetry
– An I/O device is NOT connected to all processors
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