Introduction to

CMOS VLSI
Design


CMOS Transistor Theory
CMOS VLSI Design MOS devices Slide 2
Outline
Introduction
MOS Capacitor
nMOS I-V Characteristics
pMOS I-V Characteristics
Gate and Diffusion Capacitance
Pass Transistors
RC Delay Models
CMOS VLSI Design MOS devices Slide 3
Introduction
So far, we have treated transistors as ideal switches
An ON transistor passes a finite amount of current
Depends on terminal voltages
Derive current-voltage (I-V) relationships
Transistor gate, source, drain all have capacitance
I = C (AV/At) -> At = (C/I) AV
Capacitance and current determine speed
Also explore what a degraded level really means
CMOS VLSI Design MOS devices Slide 4
MOS Capacitor
Gate and body form MOS capacitor
Operating modes
Accumulation
Depletion
Inversion
polysilicon gate
(a)
silicon dioxide insulator
p-type body
+
-
V
g
< 0
(b)
+
-
0 < V
g
< V
t
depletion region
(c)
+
-
V
g
> V
t
depletion region
inversion region
CMOS VLSI Design MOS devices Slide 5
Terminal Voltages
Mode of operation depends on V
g
, V
d
, V
s

V
gs
= V
g
V
s
V
gd
= V
g
V
d
V
ds
= V
d
V
s
= V
gs
- V
gd
Source and drain are symmetric diffusion terminals
By convention, source is terminal at lower voltage
Hence V
ds
> 0
nMOS body is grounded. First assume source is 0 too.
Three regions of operation
Cutoff
Linear
Saturation
V
g
V
s
V
d
V
gd
V
gs
V
ds
+
-
+
-
+
-
CMOS VLSI Design MOS devices Slide 6
nMOS Cutoff
No channel
I
ds
= 0
+
-
V
gs
= 0
n+ n+
+
-
V
gd
p-type body
b
g
s
d
CMOS VLSI Design MOS devices Slide 7
nMOS Linear
Channel forms
Current flows from d to s
e
-
from s to d
I
ds
increases with V
ds
Similar to linear resistor
+
-
V
gs
> V
t
n+ n+
+
-
V
gd
= V
gs
+
-
V
gs
> V
t
n+ n+
+
-
V
gs
> V
gd
> V
t
V
ds
= 0
0 < V
ds
< V
gs
-V
t
p-type body
p-type body
b
g
s
d
b
g
s
d
I
ds
CMOS VLSI Design MOS devices Slide 8
nMOS Saturation
Channel pinches off
I
ds
independent of V
ds
We say current saturates
Similar to current source
+
-
V
gs
> V
t
n+ n+
+
-
V
gd
< V
t
V
ds
> V
gs
-V
t
p-type body
b
g
s
d
I
ds
CMOS VLSI Design MOS devices Slide 9
I-V Characteristics
In Linear region, I
ds
depends on
How much charge is in the channel?
How fast is the charge moving?
CMOS VLSI Design MOS devices Slide 10
Channel Charge
MOS structure looks like parallel plate capacitor
while operating in inversion
Gate oxide channel
Q
channel
=

n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator, c
ox
= 3.9)
polysilicon
gate
CMOS VLSI Design MOS devices Slide 11
Channel Charge
MOS structure looks like parallel plate capacitor
while operating in inversion
Gate oxide channel
Q
channel
= CV
C =

n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator, c
ox
= 3.9)
polysilicon
gate
CMOS VLSI Design MOS devices Slide 12
Channel Charge
MOS structure looks like parallel plate capacitor
while operating in inversion
Gate oxide channel
Q
channel
= CV
C = C
g
= c
ox
WL/t
ox
= C
ox
WL
V =

n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator, c
ox
= 3.9)
polysilicon
gate
C
ox
= c
ox
/ t
ox
CMOS VLSI Design MOS devices Slide 13
Channel Charge
MOS structure looks like parallel plate capacitor
while operating in inversion
Gate oxide channel
Q
channel
= CV
C = C
g
= c
ox
WL/t
ox
= C
ox
WL
V = V
gc
V
t
= (V
gs
V
ds
/2) V
t
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator, c
ox
= 3.9)
polysilicon
gate
C
ox
= c
ox
/ t
ox
CMOS VLSI Design MOS devices Slide 14
Carrier velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-field
between source and drain
v =
CMOS VLSI Design MOS devices Slide 15
Carrier velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-field
between source and drain
v = E called mobility
E =
CMOS VLSI Design MOS devices Slide 16
Carrier velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-field
between source and drain
v = E called mobility
E = V
ds
/L
Time for carrier to cross channel:
t =
CMOS VLSI Design MOS devices Slide 17
Carrier velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-field
between source and drain
v = E called mobility
E = V
ds
/L
Time for carrier to cross channel:
t = L / v
CMOS VLSI Design MOS devices Slide 18
nMOS Linear I-V
Now we know
How much charge Q
channel
is in the channel
How much time t each carrier takes to cross
ds
I =
CMOS VLSI Design MOS devices Slide 19
nMOS Linear I-V
Now we know
How much charge Q
channel
is in the channel
How much time t each carrier takes to cross
channel
ds
Q
I
t
=
=
CMOS VLSI Design MOS devices Slide 20
nMOS Linear I-V
Now we know
How much charge Q
channel
is in the channel
How much time t each carrier takes to cross
channel
ox
2
2
ds
ds
gs t ds
ds
gs t ds
Q
I
t
W
V
C V V V
L
V
V V V

|
=
| |
=
|
\ .
| |
=
|
\ .
ox
=
W
C
L
|
CMOS VLSI Design MOS devices Slide 21
nMOS Saturation I-V
If V
gd
< V
t
, channel pinches off near drain
When V
ds
> V
dsat
= V
gs
V
t
Now drain voltage no longer increases current
ds
I =
CMOS VLSI Design MOS devices Slide 22
nMOS Saturation I-V
If V
gd
< V
t
, channel pinches off near drain
When V
ds
> V
dsat
= V
gs
V
t
Now drain voltage no longer increases current
2
dsat
ds gs t dsat
V
I V V V |
| |
=
|
\ .
CMOS VLSI Design MOS devices Slide 23
nMOS Saturation I-V
If V
gd
< V
t
, channel pinches off near drain
When V
ds
> V
dsat
= V
gs
V
t
Now drain voltage no longer increases current
( )
2
2
2
dsat
ds gs t dsat
gs t
V
I V V V
V V
|
|
| |
=
|
\ .
=
CMOS VLSI Design MOS devices Slide 24
nMOS I-V Summary
( )
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V
|
|

<

| |
= <
|
\ .

>

Shockley 1
st
order transistor models
CMOS VLSI Design MOS devices Slide 25
Example
Example: a 0.6 m process from AMI semiconductor
t
ox
= 100
= 350 cm
2
/V*s
V
t
= 0.7 V
Plot I
ds
vs. V
ds
V
gs
= 0, 1, 2, 3, 4, 5
Use W/L = 4/2
( )
14
2
8
3.9 8.85 10
350 120 /
100 10
ox
W W W
C A V
L L L
|

| | -
| |
= = =
| |

\ .
\ .
0 1 2 3 4 5
0
0.5
1
1.5
2
2.5
V
ds
I
d
s

(
m
A
)
V
gs
= 5
V
gs
= 4
V
gs
= 3
V
gs
= 2
V
gs
= 1
CMOS VLSI Design MOS devices Slide 26
pMOS I-V
All dopings and voltages are inverted for pMOS
Mobility
p
is determined by holes
Typically 2-3x lower than that of electrons
n
120 cm
2
/V*s in AMI 0.6 m process
Thus pMOS must be wider to provide same current
In this class, assume
n
/
p
= 2

CMOS VLSI Design MOS devices Slide 27
Capacitance
Any two conductors separated by an insulator have
capacitance
Gate to channel capacitor is very important
Creates channel charge necessary for operation
Source and drain have capacitance to body
Across reverse-biased diodes
Called diffusion capacitance because it is
associated with source/drain diffusion
CMOS VLSI Design MOS devices Slide 28
Gate Capacitance
Approximate channel as connected to source
C
gs
= c
ox
WL/t
ox
= C
ox
WL = C
permicron
W
C
permicron
is typically about 2 fF/m
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator, c
ox
= 3.9c
0
)
polysilicon
gate
CMOS VLSI Design MOS devices Slide 29
Diffusion Capacitance
C
sb
, C
db
Undesirable, called parasitic capacitance
Capacitance depends on area and perimeter
Use small diffusion nodes
Comparable to C
g

for contacted diff
C
g
for uncontacted
Varies with process
CMOS VLSI Design MOS devices Slide 30
Pass Transistors
We have assumed source is grounded
What if source > 0?
e.g. pass transistor passing V
DD
V
DD
V
DD
CMOS VLSI Design MOS devices Slide 31
Pass Transistors
We have assumed source is grounded
What if source > 0?
e.g. pass transistor passing V
DD
V
g
= V
DD
If V
s
> V
DD
-V
t
, V
gs
< V
t
Hence transistor would turn itself off
nMOS pass transistors pull no higher than V
DD
-V
tn
Called a degraded 1
Approach degraded value slowly (low I
ds
)
pMOS pass transistors pull no lower than V
tp
V
DD
V
DD
CMOS VLSI Design MOS devices Slide 32
Pass Transistor Ckts
V
DD
V
DD
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
CMOS VLSI Design MOS devices Slide 33
Pass Transistor Ckts
V
DD
V
DD
V
s
= V
DD
-V
tn
V
SS
V
s
= |V
tp
|
V
DD
V
DD
-V
tn
V
DD
-V
tn
V
DD
-V
tn
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
-V
tn
V
DD
-2V
tn
CMOS VLSI Design MOS devices Slide 34
Effective Resistance
Shockley models have limited value
Not accurate enough for modern transistors
Too complicated for much hand analysis
Simplification: treat transistor as resistor
Replace I
ds
(V
ds
, V
gs
) with effective resistance R
I
ds
= V
ds
/R
R averaged across switching of digital gate
Too inaccurate to predict current at any given time
But good enough to predict RC delay
CMOS VLSI Design MOS devices Slide 35
RC Delay Model
Use equivalent circuits for MOS transistors
Ideal switch + capacitance and ON resistance
Unit nMOS has resistance R, capacitance C
Unit pMOS has resistance 2R, capacitance C
Capacitance proportional to width
Resistance inversely proportional to width
k g
s
d
g
s
d
kC
kC
kC
R/k
k g
s
d
g
s
d
kC
kC
kC
2R/k
CMOS VLSI Design MOS devices Slide 36
RC Values
Capacitance
C = C
g
= C
s
= C
d
= 2 fF/m of gate width
Values similar across many processes
Resistance
R ~ 6 KO*m in 0.6um process
Improves with shorter channel lengths
Unit transistors
May refer to minimum contacted device (4/2 )
Or maybe 1 m wide device
Doesnt matter as long as you are consistent
CMOS VLSI Design MOS devices Slide 37
Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter
2
1
A
Y
2
1
CMOS VLSI Design MOS devices Slide 38
Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter
C
C
R
2C
2C
R
2
1
A
Y
C
2C
Y
2
1
CMOS VLSI Design MOS devices Slide 39
Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter
C
C
R
2C
2C
R
2
1
A
Y
C
2C
C
2C
C
2C
R
Y
2
1
CMOS VLSI Design MOS devices Slide 40
Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter
C
C
R
2C
2C
R
2
1
A
Y
C
2C
C
2C
C
2C
R
Y
2
1
d = 6RC