TABLE OF CONTENTS

ACKNOWLEDGEMENTS.............................................................................................II
TABLE OF CONTENTS..............................................................................................III
LIST OF TABLES.....................................................................................................IV
LIST OF FIGURES....................................................................................................V
ABSTRACT............................................................................................................VI

CHAPTER ONE: INTRODUCTION & BACKGROUND

1 INTRODUCTION..........................................................................................14
1.1 PRE -ALIGNMENT............................................................................................15
1.1.1 POLARIZATION PRE-ALIGNMENT.......................................................................15
1.1.2 AZIMUTH PRE-ALIGNMENT...............................................................................16
1.1.3 ELEVATION (TILT) PRE-ALIGNMENT...................................................................17
1.2 ANTENNA FINAL ADJUSTMENTS...........................................................................19
1.3 CONCLUSION.................................................................................................25

CHAPTER TWO: PROJECT OVERVIEW

2.1 BLOCK DIAGRAM..............................................................................................27
2.2 DESCRIPTION OF PROJECT..................................................................................28
2.3 SUMMARIZE OVERVIEW......................................................................................29
2.3.1 FPGA KIT....................................................................................................29
2.3.2 RF TRANSCEIVERS........................................................................................29
2.2.3 IR SENSORS.................................................................................................29
2.2.4 SERVO MOTORS...........................................................................................30
2.2.5 SERIAL PORTS.............................................................................................30
2.3 CONCLUSION.................................................................................................31

CHAPTER 3 SYSTEM METHODOLOGY

3.1 INTRODUCTION ................................................................................................33
3.2 DESIGN PHASE........................................................................................34
3.3 IMPLEMENTATION PHASE ...................................................................................34
3.4 TESTING PHASE ...................................................................................35

CHAPTER 4: SYSTEM PROCESS FLOW

4.1 INTRODUCTION.................................................................................................38
4.2 PROJECT FLOW................................................................................................38
4.3 EXPLANATION OF PROCESS FLOW..........................................................................40
4.3.1 PHASE ONE.................................................................................................48
4.3.2 PHASE

TWO................................................................................................40

4.3.3 PHASE THREE..............................................................................................40

4.3.4 PHASE FOUR................................................................................................41
4.3.5 PHASE FIVE.................................................................................................41
4.4 CONCLUSION..................................................................................................42
CHAPTER 5: ALTERA MAX II MICRO FPGA KIT
5.1 INTRODUCTION TO FIELD-PROGRAMMABLE GATE.....................................................44
5.2 HISTORY........................................................................................................45
5.3 MODERN DEVELOPMENT................................................................................46
5.4 MAJOR MANUFACTURERS...................................................................................47
5.5 GATES..........................................................................................................47
5.6 MARKET SIZE..................................................................................................48
5.7 APPLICATIONS.........................................................................................48
5.8 ARCHITECTURE................................................................................................49
5.9 FPGA DESIGN AND PROGRAMMING......................................................................52
5.10 ALTERA MAX II MICRO BOARD............................................................................53
5.11 LAYOUT AND COMPONENTS OF MAX II BOARD.........................................................54
5.12 BLOCK DIAGRAM OF THE MAX II MICRO BOARD ...................................................55
5.12.1 MAX II 2210 FPGA................................................................................56
5.12.2 USB BLASTER CIRCUIT......................................................................56
5.12.3 PUSHBUTTON SWITCHES.................................................................56
5.12.4 CLOCK INPUTS....................................................................................56
5.12.5 PROTOTYPING AREAS.......................................................................56
5.13 SCHEMATIC OF THE MAX II MICRO BOARD........................................57
5.13.1 6BLEDS,SWITCHES,AND CLOCK INPUTS.........................................57
5.13.2 EXPANSION PORT AND PROTOTYPING AREA................................59
5.14 POWER-UP THE MAX II MICRO BOARD...............................................61
5.15 METHODS TO CONFIGURE THE MAX II MICRO BOARD...................61
5.15.1 CONFIGURE THE MAX II MICRO BOARD IN JTAG MODE................62
5.15.2 USE MAX II MICRO AS A USB BLASTER CABLE...............................62
5.15.3 MAX II CPLD POWER OFF MODE.......................................................63

5.16 MAX II MICRO BOARD CONTOL PANEL..............................................64

5.17 USING THE CONTROL PANEL..............................................................67
5.17.1 LIGHT UP THE LEDS...........................................................................68
5.17.2 DETECTION OF THE ACTION OF THE PUSHBUTTONS.....................68
5.17.3 CONFIGURETHE GPIOS IN THE PROTOTYPING AREA...................68

TABLE OF FIGURES
CHAPTER1
Figure 1.1 -Antenna, top-down perspective.16
Figure 1.2 -Use of level to establish vertical plumb17
Figure 1.3 -Calculating required tilt angle.18
Figure 1.4 -Antenna tilt adjustment19
Figure 1.5 - Sample RSL Chart .20
Figure 1.6 - Side lobe pattern.23
Figure 1.7 - Using side lobes to combat interference.24
CHAPTER 2
Figure 2.1-System Block Diagram.27
CHAPTER3
Figure- 3.1 Circuit design of FPGA based Automatic Microwave Dish Alignment system38
CHAPTER 4
Figure 4.1: Process Flow Diagram39
CHAPTER 5
Figure 5.1 - The Programmable Marketplace..47
Figure 5.2 -Generic FPGA architecture49
Figure 5.3 - Structure of configurable logic blocks (CLB)..50
Figure 5.4 - Switch boxtopology.51
Figure 5.5 - The MAX II Micro board.53
Figure 5.6 - Block diagram of the MAX II Micro board...55
Figure 5.7 - Switch debouncing....57
Figure 5.8 - Schematic diagrams of the LEDs, push buttons, and clock circuit..58

Figure 5.9 - Schematic of the prototyping area...59

Figure 5.10 - Schematic of the prototyping area.60
Figure 5.11 - The detailed I/O map of prototyping area A and B..60
Figure 5.12 - Set Switch1 to UP position and Switch2to DOWN
Position in normal operation (JTAG mode)......................................................62
Figure 5.13 - Solder a 10-pin header onto the MAX II Micro board.....62
Figure 5.14 set both switches to UP position to set up
the MAX II Micro board as a USB Blaster63
Figure 5.15 Use MAX II Micro as a USB Blaster cable and
Connect to another Altera board (NIOS II Kit in this case)..63
Figure 5.16 -Set Switch1 to DOWN position to
Turn off the power supply to MAX II CPLD.64
Figure 5.17 - Quartus II Programmer window.66
Figure 5.19 -The MAX II Micro Control Panel concepts....66

LIST OF TABLES

Table 5.1 - Pin assignments for the LEDs, Buttons, and Clock inputs.