ACER - Aspire - 5500 - Compal - EFL50 - LS-2766P - SCHEMA

5
Digitally signed by
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DN: cn=fdsf, o=fsdfsd,
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email=fdfsd@fsdff,
c=US
Date: 2010.02.15
18:47:35 +07'00'
Mini (EFL50) ATI VGA/B M52-P
www.kythuatvitinh.com
Revision 1.0
Compal Secret Data
Security Classification
Issued Date
2005/12/22
Deciphered Date
2006/12/22
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
Title
Compal Electronics, Inc.

Cover Sheet
Size
Document Number
Rev
1.0
EFL50 LS-2766P
Date:
12/23/05 14:40:19
Sheet
1
of
13
M54P/M52P BLOCK DIAGRAM

GDDR1
D
DDRA
8M*32
M54P/M52P
MDA[0:63]
DQ[0:31]
NMAA[0:13]
MAA[0:13]
K4D553235F-GC2A
A[0:11]
Samsung
PCIE
Connector
DQA[0:63]
PCIE_TX[0:15]P, PCIE_TX[0:15]N
PCIE_RX[0:15]P, PCIE_RX[0:15]N
PCIE_REFCLKP, PCIE_REFCLKN
PWRGD
CLK/CLK#
NMCLKA0/A0#
NMCLKA1/A1#
PAGE 8
VGA_OUT
DDRB
DQ[0:31]
K4D553235F-GC2A
Samsung
VGA_CRT_R, VGA_CRT_G, VGA_CRT_B, DACA_HSYNC, DACA_VSYNC

VGA_DDC_CLK, VGA_DDC_DAT
MDB[0:63]
NMAB[0:13]
NMAB[0:13]
A[0:11]
PLTRST_VGA#
VGA_TV_LUMA,VGA_TV_CRMA
DDC1_I2C
MDB[0:63]
CLK_PCIE_VGA#
DVI_TXD[0:2](+,-); DVI_TXC+(-)
TV_OUT
8M*32
PCIE_GT_MRX_P[0:15], PCIE_GTX_MRX_N[0:15]
CLK_PCIE_VGA
DVI
CLKA[0:1]
CLKA[0:1]#
PCIE_MTX_C_GRX_P[0:15], PCIE_MTX_C_GRX_N[0:15]
LVDS Bus
I2CC_SCL
I2CC_SDA
DVPDATA[18:19]
CLK/CLK#
NMCLKB0/B0#
NMCLKB1/B1#
CLKB[0:1]
CLKB[0:1]#
PAGE 9
27MHz
SPREAD
CLOCK
DIGON
VGA_ENVDD
BLON
VGA_ENBKL
OSC_IN
PCIE_VDDR
PCIE_PVDD
OSC_SPREAD
+1.2VS
+1.2VS
+1.5VS
APW7057KC-TR
PAGE 11
+1.5VS
+5VS
+5VS
B+
ASM3P1819N-SR
PAGE 4
+3VS
+1.8VS
+2.5VS
THERMAL
SENSOR
MAX6649MUA
ACES 88069-1600A
PAGE 3
D+/DVDDC
THERM_SDA, THERM_SCL
GPIO5
THER_ALERT
+VDD_CORE
+VDD_CORE
POWER_SEL
B+
SL6225BCA-T
PAGE 11
GPIO_AUXWIN
PAGE 4
VDDR3
VDDR4
VDDR5
VDDR1
VDD25, LVDDR,
TXVDDR, AVDD,
A2VDD
+3.3VS
+1.8VS
+2.5VS
A
PAGE 4,5,6,7
Compal Secret Data
Issued Date
2005/12/22
Deciphered Date
2006/12/22
5
Title

Block Diagram
Size
Document Number
Rev
1.0
EFL50 LS-2766P
Date:
12/23/05 14:40:19
Sheet
1
of
13
PCIE_GTX_MRX_P[0:15]
PCIE_GTX_MRX_P[0:15] <4>
PCIE_GTX_MRX_N[0:15]
PCIE_GTX_MRX_N[0:15] <4>
PCIE_MTX_C_GRX_P[0:15]
PCIE_MTX_C_GRX_P[0:15] <4>
PCIE_MTX_C_GRX_N[0:15]
<4> VGA_CRT_R
<4> VGA_CRT_G
<4> VGA_CRT_B
<4> CRT_VSYNC
<4> CRT_HSYNC
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
CRT_VSYNC
CRT_HSYNC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
G1
161
PCIE_MTX_C_GRX_N[0:15] <4>
JP1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
B+
VGA_TV_Y
VGA_TV_C
VGA_TV_COMP
VGA_TV_Y <4>
VGA_TV_C <4>
VGA_TV_COMP <4>
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
C2
C3
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
PCIE_GTX_MRX_P0
PCIE_GTX_MRX_N0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1
C4
C5
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
PCIE_GTX_MRX_P1
PCIE_GTX_MRX_N1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
C6
C7
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
PCIE_GTX_MRX_P2
PCIE_GTX_MRX_N2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
C8
C9
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
C10
C11
1
2
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
PCIE_GTX_MRX_P3
PCIE_GTX_MRX_N3
1
1
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
PCIE_GTX_MRX_P4
PCIE_GTX_MRX_N4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
C12
C13
1
1
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
PCIE_GTX_MRX_P5
PCIE_GTX_MRX_N5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
C14
C15
1
1
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
PCIE_GTX_MRX_P6
PCIE_GTX_MRX_N6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
C16
C17
1
1
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
PCIE_GTX_MRX_P7
PCIE_GTX_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
C18
C19
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
PCIE_GTX_MRX_P8
PCIE_GTX_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
C20
C21
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
PCIE_GTX_MRX_P9
PCIE_GTX_MRX_N9
PCIE_GTX_C_MRX_P10 C22
PCIE_GTX_C_MRX_N10 C23
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
PCIE_GTX_MRX_P10
PCIE_GTX_MRX_N10
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
PCIE_GTX_MRX_P11
PCIE_GTX_MRX_N11
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
PCIE_GTX_MRX_P12
PCIE_GTX_MRX_N12
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
PCIE_GTX_MRX_P13
PCIE_GTX_MRX_N13
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
PCIE_GTX_MRX_P14
PCIE_GTX_MRX_N14
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
PCIE_GTX_MRX_P15
PCIE_GTX_MRX_N15
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15
<4> VGA_CRT_CLK
<4> VGA_CRT_DAT
VGA_CRT_CLK
VGA_CRT_DAT
<5>
<5>
<5>
<5>
DVI_TXC+
DVI_TXCDVI_TX0+
DVI_TX0-
<5>
<5>
<5>
<5>
DVI_TX1+
DVI_TX1DVI_TX2+
DVI_TX2-
<4> CLK_PCIE_VGA
<4> CLK_PCIE_VGA#
+5VALW
+2.5VS
+1.8VS_D
ACES_88396-1G41
VGA_DVI_CLK
VGA_DVI_DAT
DAC_BRIG
DISPOFF#
INVT_PWM
PCIE_RST#
VGA_ENBKL
LCD_ID#
VGA_DVI_DET <5>
VGA_DVI_CLK <5>
VGA_DVI_DAT <5>
DAC_BRIG <10>
DISPOFF# <10>
INVT_PWM <10>
PCIE_RST# <4>
susp# <10,11>
VGA_ENBKL <4>
LCD_ID# <10>
TP7
+1.5VS
+3VS_D
+1.8VS_D
162
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
G2
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
Compal Secret Data
2005/12/22
Issued Date
Deciphered Date
2006/12/22
5
Title
VGA Connector
Size Document Number
Custom
Date:
12/23/05 14:40:19
PCIE Connector
Rev
1.0
EFL50 LS-2766P
Sheet
1
of
13
U2A
<3> PCIE_GTX_MRX_N[0:15]
<3> CLK_PCIE_VGA
<3> CLK_PCIE_VGA#
PCIE_MTX_C_GRX_P[0:15]
<3> PCIE_MTX_C_GRX_P[0:15]
PCIE_MTX_C_GRX_N[0:15]
<3> PCIE_MTX_C_GRX_N[0:15]
+3VS
AL28
AK28
PCIE_REFCLKP
PCIE_REFCLKN
PCIE_GTX_MRX_P0
PCIE_GTX_MRX_N0
PCIE_GTX_MRX_P1
PCIE_GTX_MRX_N1
PCIE_GTX_MRX_P2
PCIE_GTX_MRX_N2
PCIE_GTX_MRX_P3
PCIE_GTX_MRX_N3
PCIE_GTX_MRX_P4
PCIE_GTX_MRX_N4
PCIE_GTX_MRX_P5
PCIE_GTX_MRX_N5
PCIE_GTX_MRX_P6
PCIE_GTX_MRX_N6
PCIE_GTX_MRX_P7
PCIE_GTX_MRX_N7
PCIE_GTX_MRX_P8
PCIE_GTX_MRX_N8
PCIE_GTX_MRX_P9
PCIE_GTX_MRX_N9
PCIE_GTX_MRX_P10
PCIE_GTX_MRX_N10
PCIE_GTX_MRX_P11
PCIE_GTX_MRX_N11
PCIE_GTX_MRX_P12
PCIE_GTX_MRX_N12
PCIE_GTX_MRX_P13
PCIE_GTX_MRX_N13
PCIE_GTX_MRX_P14
PCIE_GTX_MRX_N14
PCIE_GTX_MRX_P15
PCIE_GTX_MRX_N15
AK27
AJ27
AJ25
AH25
AH28
AG28
AG27
AF27
AF25
AE25
AE28
AD28
AD27
AC27
AC25
AB25
AB28
AA28
AA27
Y27
Y25
W25
W28
V28
V27
U27
U25
T25
T28
R28
R27
P27
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13P
PCIE_TX13N
PCIE_TX14P
PCIE_TX14N
PCIE_TX15P
PCIE_TX15N
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15
AJ31
AH31
AH30
AG30
AG32
AF32
AF31
AE31
AE30
AD30
AD32
AC32
AC31
AB31
AB30
AA30
AA32
Y32
Y31
W31
W30
V30
V32
U32
U31
T31
T30
R30
R32
P32
P31
N31
PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX12P
PCIE_RX12N
PCIE_RX13P
PCIE_RX13N
PCIE_RX14P
PCIE_RX14N
PCIE_RX15P
PCIE_RX15N
U7
VDD
SCLK
THERM_SCL
D+
SDATA
THERM_SDA
D-
ALERT#
1
R48
THM@
R50
2.2K_0402_5%
D+
D-
C121
1
2
2200P_0402_50V7K
THM@
OVERT#
GND
2
0_0402_5%
THM@
THER_ALERT#
MAX6649MUA_8UMAX
THM@
+1.2VS
R26 1
R2 1
R3 1
R1
<3> PCIE_RST#
AE24
2 2K_0402_1%
2 562_0402_1% AD24
2 1.47K_0402_1% AB24
AC8
NC_DVOVMODE_0
NC_DVOVMODE_1
AK4
AL4
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23
AF2
AF1
AF3
AG1
AG2
AG3
AH2
AH3
AJ2
AJ1
AK2
AK1
AK3
AL2
AL3
AM3
AE6
AF4
AF5
AG4
AJ3
AH4
AJ4
AG5
AH5
AF6
AE7
AG6
R63
R14
1
1
2 @ 10K_0402_5%
10K_0402_5%
2
R13
R80
1
1
2 @ 10K_0402_5%
10K_0402_5%
2
Straps: (Internal pull down)
VGA_ENBKL
2 10K_0402_5%
R16 1
GPIO9
Transmitter power
saving enable
GPIO[0]
0: 50% TX output swing

1: Full TX output swing
Transmitter
de-emphasis enable
GPIO[1]
0: TX de-emphasis disable
1: TX de-emphasis enable
Debug Access
GPIO[4]
0: OFF
1: ON
GPIO[5] GPIO5 = 1
VGA_ENBKL <3>
Current bias for
the PCI Express PHY PLL
TP4
GPIO11
GPIO12
GPIO13
(must be pulled to 3.3V at reset using)
POWER_SEL
OSC_SPREAD
THER_ALERT#
For No External ROM:

GPIO[13,12] is for MEM_AP_SIZE[1,0]
(Internal
GPIO[11] don't care
Pull-down)
POWER_SEL <11>
1 499_0402_1%
+3VS
2 499_0402_1%
C130 1
2
0.1U_0402_16V4Z
R53 2
R54 1
GPIO[9, GPIO[9]=1 External ROM Attached

13:11] GPIO[9]=0 No External ROM
ROM ID Config
VIP_DEVICE
VSYNC
0: Slave VIP host device present

1: No slave VIP host device present
* The readback of this strap is the
inverted with respect to the value
on the pin
Low -> VDDC=1.0V+-5% Performance Mode for M52

High -> VDDC=0.95V+-5% Battery Mode for M52
POWER_SEL
+3VS
2 10K_0402_5%
R97 1
GPIO9
GPIO11
R78
R79
1
1
2 @ 10K_0402_5%
2 @ 10K_0402_5%
GPIO12
GPIO13
R76
R77
1
1
2 R256@10K_0402_5%
2 R64@ 10K_0402_5%
C
GPIO12
0
0
1
1
AG24
PERST#
AA24
AF24
PCIE_TEST
PERST#_MASK
DPLUS
D-
AH12
DMINUS
AE12
AF12
DDC3DATA
DDC3CLK
SSC@
0_0603_5%
2
GPIO13
0
1
0
1
SIZE
128MB
64MB
256MB
Reserve
+SSVDD
VDD
REF
XINMODOUT
NC
PD#
XOUT
1
R17
2 OSC_SPREAD
22_0402_5%
SSC@
4.7K_0402_5%
2
2
4.7K_0402_5%
OSC_IN 1
R25
AL26
XTALIN
THERM_SDA
THERM_SCL
2
121_0402_1%
1
R6 1
R7 1
VSS
1
1K_0402_5%
2
R34
1
2
C50
0.1U_0402_16V4Z
X1
4 VDD
OUT
1
OE
GND
27MHZ_15P
R11
R9
R8
AK24
AM24
AL24
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
For DDRII
Vedio Memory Config. (VGA Internal PD)
AJ23
AJ22
CRT_HSYNC
CRT_VSYNC
0
0
1
1
VGA_CRT_R <3>
VGA_CRT_G <3>
VGA_CRT_B <3>
CRT_HSYNC <3>
CRT_VSYNC <3>
2 4.7K_0402_5%
2 4.7K_0402_5%
GENERICA
GENERICB
R28
1K_0402_5%
RSET
AL22
R33
499_0402_1%
0
0
0
0
0
1
0
1
Size
64MB
Size
(Speed)
Vender Chips
16M16 (300MHz)
Samsung
128MB 16M16 (300MHz)
Samsung
64MB
16M16 (300MHz)
Hynix
128MB 16M16 (300MHz)
Hynix
+3VS
VGA_CRT_DAT
VGA_CRT_CLK
AK22
AF23
R2
G2
B2
Memory Aperture Size Select
I2C_DAT <10>
I2C_CLK <10>
+3VS
MEMID[2:0]
AH22
AH23
H2SYNC
V2SYNC
VGA_CRT_DAT <3>
VGA_CRT_CLK <3>
Internal SS, Programmed via register-GENERICA = NC

GENERICB = GND.
AK15
AM15
AL15
Close to VGA Cbip
AF15
AG15
Y
C
COMP
VGA_TV_Y
AJ15
VGA_TV_C
AJ13
AH15 VGA_TV_COMP
R2SET
AK14
ROMCS#
AC7
PLLTEST
TESTEN
AG14
AG22
VGA_TV_Y <3>
VGA_TV_C <3>
VGA_TV_COMP <3>
R35 2
R39
XTAL
1
1
1
DDC1DATA
DDC1CLK
R31 1
1 150_0402_1%
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
R56
R30
R29
2
2
2
1 @ 150_0402_1%
1 @ 150_0402_1%
1 @ 150_0402_1%
VGA_TV_Y
VGA_TV_C
R36
R45
2
2
1 @ 150_0402_1%
1 @ 150_0402_1%
715_0402_1%
2 10K_0402_5%
XTALOUT
M52-P
71.5_0402_1%
Compal Secret Data
3
MEMID0
MEMID1
MEMID2
TP1
2 4.7K_0402_5%
2 4.7K_0402_5%
I2C_DAT
I2C_CLK
2 10K_0402_5% R128@
2 10K_0402_5% X76@
10K_0402_5%
HYN@
2
R23
ASM3P1819N-SR_SO8
SSC@
Minimize distance from X1 pin3 to U3 pin1
+3VS
AM26
R12 1
R10 1
C38
+3VS
U6
TV
AG12
+3VS
TP6
TP3
R32 1
R27 1
PCIE_CALRN
PCIE_CALRP
PCIE_CALI
D+
R
G
B
HSYNC
VSYNC
2 10K_0402_5%
R22
Spread spectrum
CRT
2 0_0402_5%
R24 1
+3VS
SSC@
0.1U_0402_16V4Z
VREFG
GPIO
THERMAL
+3VS
R51
2.2K_0402_5%
THM@
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7_BLON
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
NC
AD4
AD2
AD1
AD3
AC1
AC2
AC3
AB2
AC6
AC5
AC4
AB3
AB4
AB5
AD5
AB8
AA8
AB7
AB6
Thermal sensor
PCI-Express Data Bus Lane Reversal and Polarity Inversion
+3VS
CLK_PCIE_VGA
CLK_PCIE_VGA#
PCI EXPRESS
PCIE_GTX_MRX_N[0:15]
VIP HOST/ EXTERNAL TMDS
PCIE_GTX_MRX_P[0:15]
<3> PCIE_GTX_MRX_P[0:15]
OSC_IN
Issued Date
Keep away from other signal at last 25mils

4
2005/12/22
Deciphered Date
2006/12/22
3
Title

M52-P Main

Custom
EFL50 LS-2766P
Date:
12/23/05 14:40:18
Rev
1.0
Sheet
1
of
13
U2F
U2G
C81
VARY_BL
DIGON
GENERICD
INTERGRATED TMDS
C66
VDD25
VDD25
VDD25
VGA_LVDSAC- <10>
VGA_LVDSAC+ <10>
VGA_LVDSA0+ <10>
VGA_LVDSA0- <10>
VGA_LVDSA1+ <10>
VGA_LVDSA1- <10>
VGA_LVDSA2+ <10>
VGA_LVDSA2- <10>
AD12 R44 1
AE11
AD23
2 10K_0402_5%
VGA_ENVDD
R52 1
2 180_0402_5%
R49 1
2 180_0402_5%
VGA_ENVDD <10>
DVI_TXCDVI_TXC+
TXCM
TXCP
AL9
AM9
TX0M
TX0P
AK10
AL10
TX1M
TX1P
AL11
AM11
TX2M
TX2P
AL12
AM12
TX3M
TX3P
AK9
AJ9
TX4M
TX4P
AK11
AJ11
TX5M
TX5P
AK12
AJ12
DDC2DATA
DDC2CLK
AH13
AG13
VGA_DVI_DAT
VGA_DVI_CLK
HPD1
AF11
VGA_DVI_DET
DVI_TX0DVI_TX0+
R46 1
2 180_0402_5%
R43 1
2 180_0402_5%
DVI_TX1DVI_TX1+
DVI_TX2DVI_TX2+
DVI_TXC- <3>
DVI_TXC+ <3>
DVI_TX0- <3>
DVI_TX0+ <3>
DVI_TX1- <3>
DVI_TX1+ <3>
DVI_TX2- <3>
DVI_TX2+ <3>
CRT GND
VGA_LVDSACVGA_LVDSAC+
VGA_LVDSA0+
VGA_LVDSA0VGA_LVDSA1+
VGA_LVDSA2-
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
TV GND
BBP
BBP
BBP
BBP
TXCLK_LN
TXCLK_LP
TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N
AL18
AM18
AL19
AK19
AM20
AL20
AM21
AL21
AJ18
AK18
AH27
AC23
AL27
R23
P25
R25
T26
U26
Y26
AB26
AC26
AD25
AE26
AF26
AD26
AG25
AH26
AC28
Y28
U28
P28
AH29
AF28
V29
AC29
W27
AB27
V26
AJ26
AJ32
AK29
P26
P29
R29
T29
U29
W29
Y29
AA29
AB29
AD29
AE29
AF29
AG29
AJ29
AK26
AK30
AG26
N30
R31
AF30
AC30
V31
P30
AA31
U30
AD31
AK32
AJ28
Y30
AJ30
AK31
VGA_LVDSBC+ <10>
VGA_LVDSBC- <10>
VGA_LVDSB0+ <10>
VGA_LVDSB0- <10>
VGA_LVDSB1+ <10>
VGA_LVDSB1- <10>
VGA_LVDSB2+ <10>
VGA_LVDSB2- <10>
TXVSSR
TXVSSR
TXVSSR
TXVSSR
TXVSSR
TPVSS
AVSSQ
AVSSN
AVSSN
AJ7
AK7
AL7
AM7
AK8
AL8
AK23
AK25
AJ24
VSS1DI
AL23
A2VSSQ
A2VSSN
A2VSSN
AK13
AM17
AL17
VSS2DI
AJ17
PVSS
PLL GND
AC14
M23
V10
K18
VGA_LVDSBC+
VGA_LVDSBCVGA_LVDSB0+
VGA_LVDSB0VGA_LVDSB1+
VGA_LVDSB2-
PCIE GND
BBN
BBN
BBN
BBN
AJ21
AK21
AG18
AH18
AK20
AJ20
AG20
AH20
AH21
AG21
LVDS PLL&I/O GND
GENERICC
Y23
K15
R10
AC17
TXCLK_UP
TXCLK_UN
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N
EXPAND GPIO
LVDS
AE23
L10
K22
AA10
+VDD25
C
GPIO_18
GPIO_19
GPIO_20
GPIO_21
GPIO_22
GPIO_23
GPIO_24
GPIO_25
GPIO_26
GPIO_27
GPIO_28
GPIO_29
GPIO_30
GPIO_31
GPIO_32
GPIO_33
GPIO_34
FOREARD
COMPATIBILITY
AE13
AF13
AF9
AG7
AE10
AE9
AF7
AF8
AH6
AF10
AG10
AH9
AJ8
AH8
AG9
AH7
AG8
TMDS GND
U2B
MPVSS
Use 15mils trace

connect to GND
AH14
A5
LPVSS
AE18
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
AK17
AJ19
AF18
AH17
AG17
AG19
AH19
AF22
AF17
AF21
PCIE_PVSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
W23
AB23
P24
R24
T24
U24
V24
W24
Y24
AC24
AH24
V25
AA25
R26
AA26
T27
AE27
AG31
W26
N24
AA23
B1
H1
L1
P1
U1
Y1
AD7
AE8
AL1
A2
AM2
AD10
E8
H5
K10
M8
T10
E12
AC9
AF14
AD8
C5
F10
J3
L6
M6
P6
AA4
AG11
V3
AG16
R3
C6
C9
F6
H7
J6
AD16
AA6
P7
P5
M3
M9
L7
M7
AD17
AH11
A8
U7
C10
E9
F3
J9
N7
N3
Y5
AM13
AC10
Y6
U6
E5
AL13
A11
U8
U9
U10
R6
AD6
V6
AD14
AD13
D11
J12
K12
A13
F13
E13
F15
K16
W18
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CORE
GND
C27
E32
H28
J30
K17
K27
M32
A22
C20
E19
H20
J24
M28
J28
J16
F30
L29
A31
B32
E30
AE15
AG23
AD9
AF16
AH10
AJ10
AD15
AH16
K23
U18
AE16
AE17
A19
H32
F19
G19
N8
Y7
T19
V19
G21
C21
F21
AE14
AK16
U5
F22
F18
K30
C24
F24
M24
A25
D30
E25
G25
G20
G22
F27
E28
H21
J21
H16
T15
V17
C15
C4
U14
P15
A16
E16
G13
G16
P17
R16
R14
W16
C18
F16
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VGA_DVI_DAT <3>
VGA_DVI_CLK <3>
VGA_DVI_DET <3>
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R114
100K_0402_5%
M52-P
if no DVI , dvi_det pull low
M52-P
B
M52-P
Compal Secret Data
Issued Date
2005/12/22
Deciphered Date
2006/12/22
5
Title

M52-P LVD,DVI,GND,Screw

Custom
EFL50 LS-2766P
Date:
12/23/05 14:40:18
Rev
1.0
Sheet
1
of
13
U2D
U2C
MDA[0..63]
<8,9> MDA[0..63]
+1.8VS
R19
100_0402_1%
QSA_0
QSA_1
QSA_2
QSA_3
QSA_4
QSA_5
QSA_6
QSA_7
J31
K29
K25
F23
D20
B16
D16
H15
QSA_0#
QSA_1#
QSA_2#
QSA_3#
QSA_4#
QSA_5#
QSA_6#
QSA_7#
K31
K28
K26
G24
D21
C16
D15
J15
ODTA0
ODTA1
F29
D24
CLKA0
CLKA0#
D31
E31
<8,9> DQSA#[0..7]
DQMA#[0..7]
<8,9> DQMA#[0..7]
MAA[0..12]
<8,9> MAA[0..12]
A_BA[0..1]
<8,9> A_BA[0..1]
+1.8VS
R61
100_0402_1%
+MVREFD_1
(15mils)
MVREFD_0
MVREFS_0
C39
RASA0#
CASA0#
C29
WEA0#
B31
CSA0#_0
CSA0#_1
B29
C28
CLKA1
CLKA1#
B20
C19
1
2
0.1U_0402_16V4Z
B30
B28
+1.8VS
B12
C12
B11
C11
C8
B7
C7
B6
F12
D12
E11
F11
F9
D8
D7
F7
G12
G11
H12
H11
H9
E7
F8
G8
G6
G7
H8
J8
K8
L8
K9
L9
K5
L4
K4
L5
N5
N6
P4
R4
P2
R2
T3
T2
W3
W2
Y3
Y2
T4
R5
T5
T6
V5
W5
W6
Y4
R8
T8
R7
T7
V7
W7
W8
W9
R57
100_0402_1%
+MVREFD_1
+MVREFS_1
(15mils)
C31
C30
CKEA0
2
+MVREFD_0 (15mils)
+MVREFS_0 (15mils)
R62
100_0402_1%
C145
R20
100_0402_1%
CKEA1
C22
RASA1#
B24
CASA1#
B22
WEA1#
B21
CSA1#_0
CSA1#_1
B23
C23
B3
C3
(15mils)
C147
1
2
R18
100_0402_1%
R21
100_0402_1%
0.1U_0402_16V4Z
+1.8VS
0.1U_0402_16V4Z
H31
J29
J26
G23
E21
B15
D14
J17
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
DQSA#[0..7]
DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_13
DQB_14
DQB_15
DQB_16
DQB_17
DQB_18
DQB_19
DQB_20
DQB_21
DQB_22
DQB_23
DQB_24
DQB_25
DQB_26
DQB_27
DQB_28
DQB_29
DQB_30
DQB_31
DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63
MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8
MAB_9
MAB_10
MAB_11
MAB_12
MAB_13
MAB_14
MAB_15
G4
E6
E4
H4
J5
G5
F4
H6
G3
G2
D4
F2
H2
H3
F5
D5
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
A_BA0
A_BA1
MAA12
DQMB#_0
DQMB#_1
DQMB#_2
DQMB#_3
DQMB#_4
DQMB#_5
DQMB#_6
DQMB#_7
B8
D9
G9
K7
M5
V2
W4
T9
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
QSB_0
QSB_1
QSB_2
QSB_3
QSB_4
QSB_5
QSB_6
QSB_7
B9
D10
H10
K6
N4
U2
U4
V8
DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7
QSB_0#
QSB_1#
QSB_2#
QSB_3#
QSB_4#
QSB_5#
QSB_6#
QSB_7#
B10
E10
G10
J7
M4
U3
V4
V9
DQSA#0
DQSA#1
DQSA#2
DQSA#3
DQSA#4
DQSA#5
DQSA#6
DQSA#7
ODTB0
ODTB1
D6
J4
CLKB0
CLKB0#
B4
B5
MCLKA0
MCLKA0#
MEMORY B
1
C40
+MVREFD_0
(15mils)
DQMA#_0
DQMA#_1
DQMA#_2
DQMA#_3
DQMA#_4
DQMA#_5
DQMA#_6
DQMA#_7
MEMORY A
<8,9> DQSA[0..7]
0.1U_0402_16V4Z
MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13
MAA_14
MAA_15
DQSA[0..7]
DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63
D26
F28
D28
D25
E24
E26
D27
F25
C26
B26
D29
B27
B25
C25
E27
E29
M31
M30
L31
L30
H30
G31
G30
F31
M27
M29
L28
L27
J27
H29
G29
G27
M26
L26
M25
L25
J25
G28
H27
H26
F26
G26
H25
H24
H23
H22
J23
J22
E23
D22
D23
E22
E20
F20
D19
D18
B19
B18
C17
B17
C14
B14
C13
B13
D17
E18
E17
F17
E15
E14
F14
D13
H18
H17
G18
G17
G15
G14
H14
J14
R59
100_0402_1%
R58 1
4.7K_0402_5%
R55 1
4.7K_0402_5%
R60 1
4.7K_0402_5%
R15 1
243_0603_1%
MEM_RST AA3
AA5
AA2
MEMTEST AA7
2
(15mil)
MVREFD_1
MVREFS_1
ODTA0 <8>
ODTA1 <9>
CKEB0
C2
MCKEA0
RASB0#
E2
MRASA0#
CASB0#
D3
MCASA0#
WEB0#
B2
MWEA0#
CSB0#_0
CSB0#_1
D2
E3
MCSA0#0
CLKB1
CLKB1#
N2
P3
MCLKA1
MCLKA1#
MCKEA1
CKEB1
L3
DRAM_RST
RASB1#
J2
MRASA1#
TEST_MCLK
CASB1#
L2
MCASA1#
WEB1#
M2
MWEA1#
CSB1#_0
CSB1#_1
K2
K3
MCSA1#0
TEST_YCLK
MEMTEST
MCLKA0 <8>
MCLKA0# <8>
MCKEA0 <8>
MRASA0# <8>
MCASA0# <8>
MWEA0# <8>
MCSA0#0 <8>
MCLKA1 <9>
MCLKA1# <9>
MCKEA1 <9>
MRASA1# <9>
MCASA1# <9>
MWEA1# <9>
MCSA1#0 <9>
M52-P
M52-P
GDDR2
Compal Secret Data
Issued Date
2005/12/22
Deciphered Date
2006/12/22
5
Title

M52-P Memory Interface

Custom
EFL50 LS-2766P
Date:
12/23/05 14:40:18
Rev
1.0
Sheet
1
of
13
+PCIE_PVDD12
0.1U_0402_16V4Z
22U_0805_6.3V6M
C54
C67
C62
0.1U_0402_16V4Z
0.1U_0402_16V4Z
22U_0805_6.3V6M
C149
1
C71
C148
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C117
1
C60
C112
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C107
1
C86
C74
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C131
1
C82
C124
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C122
1
C98
C120
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C36
C126
1
C123
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C103
1
C128
1
C116
1
0.1U_0402_16V4Z
AJ5
AM5
AL5
AK5
VDDR4
VDDR4
VDDR4
VDDR4
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
N29 2000mA 22U_0805_6.3V6M

N28
2
2
N27
C59
C193
N26
1U_0603_10V6K
N25
1
1
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
AL31
AM31
AM30
AL32
AL30
AM28
AL29
AM29
AM27
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
AC11
AC12
P14
U15
W14
W15
R17
R15
V15
V16
T16
U16
T17
U17
V14
R18
T18
V18
P18
P19
R19
W19
AD11
+3VS
C156
1
C47
+PCIE_VDDR12B
L14
1
2
BLM18PG121SN1D_0603
Close to U2.N26
22U_0805_6.3V6M
2
C51
1U_0402_6.3V4Z
C34
Close to U2.AL29
+VGA_CORE
C61
1
1
1U_0603_10V6K
VDDC+VDDCI=18A
C72
1
+VGA_CORE
C70
1
+PCIE_VDDR12A
L15
1
2
BLM18PG121SN1D_0603
2
C42
1U_0402_6.3V4Z
+VGA_CORE
C87
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C56
C89
C94
C97
22U_0805_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C113
1
C104
1
C119
1
C44
+1.2VS
C45
1U_0402_6.3V4Z
22U_0805_6.3V6M
+1.2VS
D
2
C194
+1.2VS
C53
1U_0603_10V6K
22U_0805_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C115
1
C83
C69
330U_D2E_2.5VM_R9
C
22U_0805_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C68
C102
1
C99
0.1U_0402_16V4Z
C63
+VDDRH
22U_0805_6.3V6M
C146
1
50mA
L10
C154
C153
1
0.1U_0402_16V4Z
BLM15AG102SN1D_0402
L5
1
2
+2.5VS
1
C268 +
@ 330U_V_6.3VM_R25
+2.5VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C64
C139
1
50mA
0.1U_0402_16V4Z
AE2
AE3
AE4
AE5
VDDR5
VDDR5
VDDR5
VDDR5
C272
1
0.1U_0402_16V4Z
AC13 50mA
AC16
AC18
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VDDPLL
AC15 20mA
+VDDRH0
+VDDRH
400mA A27
F1
A28
E1
+AVDD
VDDRH0
VDDRH1
VSSRH0
VSSRH1
22U_0805_6.3V6M
2
2
+VDDPLL
L2
LPVDD/VDDL0
AE19
LVDDR/VDDL0
LVDDR/VDDL0
LVDDR/VDDL0
AF20
AE20
AF19
LVDDR/VDDL1
LVDDR/VDDL1
LVDDR/VDDL1
AC21
AC22
AD22
LVDDR/VDDL2
LVDDR/VDDL2
LVDDR/VDDL2
AE21
AD21
AE22
C129
1
1
0.1U_0402_16V4Z
+A2VDD
L9
1
2
BLM15AG102SN1D_0402
C269 +
@ 330U_V_6.3VM_R25
65mA AL25
L6
AM25
+VDDID
BLM15AG102SN1D_0402
20mA AM23
1
2
+2.5VS
2
1
C132
0.1U_0402_16V4Z
130mAAM16
22U_0805_6.3V6M
AL16
2
2
AL14
C144
C143
20mA AJ16
+VDDID
1
1
2
0.1U_0402_16V4Z
C142
0.1U_0402_16V4Z
AVDD
AVDD
VDD1DI
TPVDD
TXVDDR
TXVDDR
TXVDDR
TXVDDR
A2VDD
A2VDD
1
1
0.1U_0402_16V4Z
PVDD
NC_A2VDDQ
VDD2DI
MPVDD
C267
1
1
22U_0805_6.3V6M
+LPVDD
20mA
C88
C135 2
C105
C75
1
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
200mA
0.1U_0402_16V4Z
2
2
C85
0.1U_0402_16V4Z
2
2
C65
1
1
1
22U_0805_6.3V6M 0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
C58
+2.5VS
2
C57
C73
0.1U_0402_16V4Z
1
1
0.1U_0402_16V4Z
AM8 20mA
C155
AJ14 100mA
+2.5VS
2
C134
0.1U_0402_16V4Z
C133
L3
C137
0.1U_0402_16V4Z
C96
1
22U_0805_6.3V6M
C100
0.1U_0402_16V4Z
Compal Secret Data
Issued Date
2005/12/22
Deciphered Date
2006/12/22
4
1
2
+2.5VS
2 BLM15AG102SN1D_0402
1
2
+VGA_CORE
2 BLM15AG102SN1D_0402
+2.5VS
+PVDD
L8
1
22U_0805_6.3V6M
L7
1
2
BLM15AG102SN1D_0402
C141
0.1U_0402_16V4Z
1
1
0.1U_0402_16V4Z
+MPVDD
20mA
C138
22U_0805_6.3V6M
2
2
AJ6 150mA
AK6
AL6
AM6
+VGA_CORE
C95
2
M52-P
+2.5VS
C93
0.1U_0402_16V4Z
+VDDCI
L4
0.1U_0402_16V4Z
1
2
2
2 BLM18PG121SN1D_0603
0.1U_0402_16V4Z
2
2
C55
A6
L1
1
2
CHB1608U301_0603
C101
1U_0402_6.3V4Z
C108
+LPVDD
22U_0805_6.3V6M
2
2
C80
1
2
+1.2VS
2 BLM15AG102SN1D_0402
W10 500mA
T14
W17
P16
T23
K14
U19
2
50mA
0.1U_0402_16V4Z
C125
TM DS
0.1U_0402_16V4Z
VDD25
VDD25
VDD25
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
PLL
22U_0805_6.3V6M
C271
C136
1
+VDDRH0
L16
0.1U_0402_16V4Z
1
2
BLM18PG121SN1D_0603
2
2
2
C270
C127
1
MEM I/O
CLOCK
C159
0.1U_0402_16V4Z
C RT
22U_0805_6.3V6M
0.1U_0402_16V4Z
TV
1
2
BLM18PG121SN1D_0603
0.1U_0402_16V4Z
2
2
+VDD25
I/O
0.1U_0402_16V4Z
+1.8VS
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
C46
1U_0402_6.3V4Z
PCIE_PVDD_12
PCIE_PVDD_12
PCIE_PVDD_12
I/O INTERNAL
0.1U_0402_16V4Z
LVDS PLL, I/O
+3VS
C84
C140
1
AB9
AB10
AA9
AC19
AD18
AC20
AD19
AD20
C35
22U_0805_6.3V6M
V23 100mA
N23
P23
U23
L13
1
2
BLM18PG121SN1D_0603
0.1U_0402_16V4Z
+1.8VS
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
POWERPCIE_PVDD_12
1U_0402_6.3V4Z
2
0.1U_0402_16V4Z
1
C
C1
J1
M1
R1
V1
AA1
A3
P9
J10
N9
P10
A9
Y10
P8
R9
Y9
J11
A21
M10
N10
Y8
J18
J19
K21
A12
H13
A15
J20
J13
K11
K19
A18
L23
K20
K24
L24
H19
A24
K13
J32
A30
C32
F32
L32
P CI EXPRESS
0.1U_0402_16V4Z
U2E
+1.8VS
MEMORY I/O
C37
1000mA for GDDR1

2400mA for GDDR3
C106
1
2
CO RE
+1.8VS
C118
1
Title

M52-P Power

Custom
EFL50 LS-2766P
Date:
12/23/05 14:40:19
Rev
1.0
Sheet
1
of
13
MCLKA0#
<6,9> DQSA[0..7]
DQSA#[0..7]
DQMA#[0..7]
Default VRAM chip is SAM: SA00000YC00.
A_BA[0..1]
<6,9> A_BA[0..1]
U8
1
C92
470P_0402_50V7K
@
<6> MCLKA0#
<6> MCLKA0
A_BA0
A_BA1
L2
L3
MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
MCLKA0#
MCLKA0
K8
J8
CK
CK
MCKEA0
<6> MCKEA0
<6> MCSA0#0
<6> MWEA0#
U9
BA0
BA1
K2
CKE
MCSA0#0
L8
CS
MWEA0#
K3
WE
MRASA0#
K7
RAS
MCASA0#
L7
CAS
DQMA#0
DQMA#1
F3
B3
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
VDD1
VDD2
VDD3
VDD4
VDD5
A1
E1
J9
M9
R1
VDDL
VSSDL
J1
J7
MDA8
MDA9
MDA11
MDA10
MDA12
MDA13
MDA14
MDA15
MDA2
MDA1
MDA0
MDA3
MDA5
MDA7
MDA6
MDA4
+1.8VS
A_BA0
A_BA1
L2
L3
MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
MCLKA0#
MCLKA0
K8
J8
CK
CK
K2
CKE
MCSA0#0
L8
CS
MWEA0#
K3
WE
MRASA0#
K7
RAS
MCASA0#
L7
CAS
DQMA#2
DQMA#3
F3
B3
LDM
UDM
ODTA0
K9
ODT
DQSA2
DQSA#2
F7
E8
LDQS
LDQS
DQSA3
DQSA#3
B7
A8
UDQS
UDQS
J2
VREF
+1.8VS
MCKEA0
R108
0_0402_5%
64@
BA0
BA1
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
VDD1
VDD2
VDD3
VDD4
VDD5
A1
E1
J9
M9
R1
VDDL
VSSDL
J1
J7
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
VSS1
VSS2
VSS3
VSS4
VSS5
A3
E3
J3
N1
P9
MDA29
MDA28
MDA31
MDA30
MDA27
MDA24
MDA26
MDA25
MDA19
MDA18
MDA17
MDA16
MDA20
MDA23
MDA22
MDA21
+1.8VS
+1.8VS
MAA[0..12]
<6,9> MAA[0..12]
<6,9> DQMA#[0..7]
R38
56_0402_1%
@
DQSA[0..7]
<6,9> DQSA#[0..7]
R37
56_0402_1%
@
MDA[0..63]
<6,9> MDA[0..63]
MCLKA0
R109
0_0402_5%
64@
<6> MCASA0#
LDM
UDM
+1.8VS
<6> ODTA0
ODTA0
K9
ODT
DQSA0
DQSA#0
F7
E8
LDQS
LDQS
DQSA1
DQSA#1
B7
A8
UDQS
UDQS
J2
VREF
A2
E2
L1
R3
R7
R8
C114
0.1U_0402_16V4Z
2 64@
SAM64@
NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8
C234
C235
0.1U_0402_16V4Z
64@ 1U_0603_10V6K
1
64@
R100
64@ 1K_0402_1%
64@
10U_0805_10V4Z
1
C49
64@
0.1U_0402_16V4Z
1
C48
10U_0805_10V4Z
64@
C90
64@
0.1U_0402_16V4Z
C77
2
0.1U_0402_16V4Z
64@
C78
+VR_VREF_1
A2
E2
L1
R3
R7
R8
C231
0.1U_0402_16V4Z
64@
K4N56163QF-ZC33_FBGA84
C111
2
0.1U_0402_16V4Z
64@
C76
64@
0.1U_0402_16V4Z
NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8
C110
C109
0.1U_0402_16V4Z
64@
64@
0.1U_0402_16V4Z
64@ 10U_0805_10V4Z
C91
1
C167
10U_0805_10V4Z
64@
0.1U_0402_16V4Z
64@
1
C166
Issued Date
C151
2
0.1U_0402_16V4Z
64@
C161
C163
2
0.1U_0402_16V4Z
64@
2005/12/22
Deciphered Date
2006/12/22
4
64@
0.1U_0402_16V4Z
64@
0.1U_0402_16V4Z
C162
C152
Title
C164
0.1U_0402_16V4Z
64@
Compal Secret Data
C236
C237
0.1U_0402_16V4Z
64@ 1U_0603_10V6K
1
64@
+1.8VS
64@
0.1U_0402_16V4Z
SAM64@ K4N56163QF-ZC33_FBGA84
As close as ppossible to related pin
+1.8VS
2
R99
10K_0402_5%
64@
R101
64@ 1K_0402_1%
+VDDL1
VSS1
VSS2
VSS3
VSS4
VSS5
A3
E3
J3
N1
P9
+1.8VS
+VR_VREF_0
(25mil)
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
R42
64@ 1K_0402_1%
2
R98
10K_0402_5%
64@
+VDDL0
R47
64@ 1K_0402_1%
<6> MRASA0#
64@
0.1U_0402_16V4Z
C158
C157
0.1U_0402_16V4Z
64@
C150
2
0.1U_0402_16V4Z
64@

External GDDR2 A0

Custom
EFL50 LS-2766P
Date:
12/23/05 14:40:19
Rev
1.0
Sheet
1
of
13
MCLKA1#
MDA[0..63]
<6,8> MDA[0..63]
MCLKA1
DQSA[0..7]
<6,8> DQSA[0..7]
DQSA#[0..7]
R112
@ 56_0402_1%
DQMA#[0..7]
<6,8> DQMA#[0..7]
<6,8> DQSA#[0..7]
R113
@ 56_0402_1%
MAA[0..12]
<6,8> MAA[0..12]
A_BA[0..1]
Default VRAM chip is SAM: SA00000YC00.
<6,8> A_BA[0..1]
1
U10
A_BA0
A_BA1
R1151
R1161
2128@ 0_0402_5% B1_A_BA0

2128@ 0_0402_5% B1_A_BA1
MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0
R1171
R1181
R1191
R1201
R1211
R1221
R1231
R1241
R1251
R1261
R1271
R1281
R1291
2128@
2128@
2128@
2128@
2128@
2128@
2128@
2128@
2128@
2128@
2128@
2128@
2128@
0_0402_5% B1_MAA12
0_0402_5% B1_MAA11
0_0402_5% B1_MAA10
0_0402_5% B1_MAA9
0_0402_5% B1_MAA8
0_0402_5% B1_MAA7
0_0402_5% B1_MAA6
0_0402_5% B1_MAA5
0_0402_5% B1_MAA4
0_0402_5% B1_MAA3
0_0402_5% B1_MAA2
0_0402_5% B1_MAA1
0_0402_5% B1_MAA0
U11
B1_A_BA0
B1_A_BA1
L2
L3
B1_MAA12
B1_MAA11
B1_MAA10
B1_MAA9
B1_MAA8
B1_MAA7
B1_MAA6
B1_MAA5
B1_MAA4
B1_MAA3
B1_MAA2
B1_MAA1
B1_MAA0
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
K8
J8
CK
CK
MCLKA1#
MCLKA1
<6> MCLKA1#
<6> MCLKA1
<6> MCKEA1
MCKEA1
K2
CKE
MCSA1#0
L8
CS
MWEA1#
K3
WE
MRASA1#
K7
RAS
MCASA1#
L7
CAS
DQMA#5
DQMA#4
F3
B3
LDM
UDM
ODTA1
K9
ODT
<6> MCSA1#0
MDA38
MDA32
MDA39
MDA34
MDA35
MDA36
MDA33
MDA37
MDA45
MDA41
MDA46
MDA40
MDA43
MDA44
MDA42
MDA47
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
VDD1
VDD2
VDD3
VDD4
VDD5
A1
E1
J9
M9
R1
VDDL
VSSDL
J1
J7
BA0
BA1
B1_A_BA0
B1_A_BA1
L2
L3
B1_MAA12
B1_MAA11
B1_MAA10
B1_MAA9
B1_MAA8
B1_MAA7
B1_MAA6
B1_MAA5
B1_MAA4
B1_MAA3
B1_MAA2
B1_MAA1
B1_MAA0
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
MCLKA1#
MCLKA1
+1.8VS
+1.8VS
R110
128@ 0_0402_5%
BA0
BA1
K8
J8
CK
CK
MCKEA1
K2
CKE
MCSA1#0
L8
CS
MWEA1#
K3
WE
MRASA1#
K7
RAS
MCASA1#
L7
CAS
DQMA#6
DQMA#7
F3
B3
LDM
UDM
ODTA1
K9
ODT
DQSA6
DQSA#6
F7
E8
LDQS
LDQS
DQSA7
DQSA#7
B7
A8
UDQS
UDQS
J2
VREF
MDA57
MDA59
MDA56
MDA58
MDA61
MDA62
MDA60
MDA63
MDA53
MDA50
MDA55
MDA49
MDA51
MDA52
MDA48
MDA54
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
VDD1
VDD2
VDD3
VDD4
VDD5
A1
E1
J9
M9
R1
VDDL
VSSDL
J1
J7
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
VSS1
VSS2
VSS3
VSS4
VSS5
A3
E3
J3
N1
P9
+1.8VS
+1.8VS
C
C266
@ 470P_0402_50V7K
R111
128@
0_0402_5%
2
R102
128@ 10K_0402_5%
DQSA5
DQSA#5
F7
E8
LDQS
LDQS
DQSA4
DQSA#4
B7
A8
UDQS
UDQS
J2
VREF
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
(25mil)
+VR_VREF_2
R104
128@ 1K_0402_1%
R106
128@ 1K_0402_1%
A2
E2
L1
R3
R7
R8
1
C232
128@ 0.1U_0402_16V4Z
NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8
VSS1
VSS2
VSS3
VSS4
VSS5
+1.8VS
C238
C239
128@ 0.1U_0402_16V4Z 128@
2
1 1U_0603_10V6K
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
2
R103
128@ 10K_0402_5%
<6> ODTA1
R105
128@ 1K_0402_1%
+1.8VS
+VDDL2
+VR_VREF_3
<6> MCASA1#
A3
E3
J3
N1
P9
A2
E2
L1
R3
R7
R8
R107
128@ 1K_0402_1%
C233
128@ 0.1U_0402_16V4Z
2
128@ 10U_0805_10V4Z
1
C242
2
A
128@ 0.1U_0402_16V4Z
1
C243
C244
128@ 10U_0805_10V4Z
0.1U_0402_16V4Z
128@
C245
128@ 0.1U_0402_16V4Z
C246
2
0.1U_0402_16V4Z
128@
C247
128@ 0.1U_0402_16V4Z
C248
2
0.1U_0402_16V4Z
128@
C249
C250
C251
128@ 0.1U_0402_16V4Z
128@ 10U_0805_10V4Z
C252
128@ 0.1U_0402_16V4Z
1
C253
128@ 0.1U_0402_16V4Z
1
C254
128@ 10U_0805_10V4Z
C240
128@
2 0.1U_0402_16V4Z
C241
128@
1 1U_0603_10V6K
C255
2
0.1U_0402_16V4Z
128@
2005/12/22
Deciphered Date
C256
C257
2
0.1U_0402_16V4Z
128@
2006/12/22
3
128@
0.1U_0402_16V4Z
128@ 0.1U_0402_16V4Z
C258
C259
Title
C260
0.1U_0402_16V4Z
128@
Compal Secret Data
Issued Date
+1.8VS
128@ 0.1U_0402_16V4Z
+VDDL3
As close as ppossible to related pin
+1.8VS
NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8
<6> MRASA1#
<6> MWEA1#
128@
0.1U_0402_16V4Z
C261
C262
128@ 0.1U_0402_16V4Z
C263
2
0.1U_0402_16V4Z
128@

External GDDR2 A0

Custom
EFL50 LS-2766P
Date:
12/23/05 14:40:19
Rev
1.0
Sheet
1
of
13
+5VALW
+LCDVDD
+3VS
LCD/PANEL BD. CONN.
CHB2012U121_0805
L11
1
2
R81
R82
100K_0402_5%
300_0402_5%
R83
2
G
10K_0402_5%
2N7002_SOT23
VGA_ENVDD 2
G
Q4
S
2N7002_SOT23
<5> VGA_ENVDD
0.01U_0402_16V7K
R84
VGA_LVDSB1+
VGA_LVDSB1-
<5> VGA_LVDSB1+
<5> VGA_LVDSB1-
C228
C229
4.7U_0805_10V4Z
VGA_LVDSB2+
VGA_LVDSB2-
<5> VGA_LVDSB2+
<5> VGA_LVDSB2-
C230
VGA_LVDSBCVGA_LVDSBC+
<5> VGA_LVDSBC<5> VGA_LVDSBC+
0.1U_0402_16V4Z
LCD_ID#
<3> LCD_ID#
10K_0402_5%
<5> VGA_LVDSB0<5> VGA_LVDSB0+
AOS3401_SOT23
+LCDVDD
JP2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
I2C_CLK
I2C_DAT
<4> I2C_CLK
<4> I2C_DAT
L12
1
2
CHB2012U121_0805
+3VS
Q2
Q3
B+
4.7U_0805_10V4Z
C227
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
DAC_BRIG
INVT_PWM
DISPOFF#
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
DAC_BRIG <3>
INVT_PWM <3>
DISPOFF# <3>
+LCDVDD
AT LEAST 60 MIL
VGA_LVDSA0- <5>
VGA_LVDSA0+ <5>
VGA_LVDSA1- <5>
VGA_LVDSA1+ <5>
VGA_LVDSA2+
VGA_LVDSA2-
VGA_LVDSA2+ <5>
VGA_LVDSA2- <5>
VGA_LVDSACVGA_LVDSAC+
VGA_LVDSAC- <5>
VGA_LVDSAC+ <5>
ACES_88326-4000
+3VS Delay
+3VS_D
+3VS
H1
H4
@ H_C236B276D157 @ H_C315D157
D
D
D
D
1
2
3
4
S
S
S
G
H6
@ H_C315D122
H7
@ H_C315D122
C226
@ 10U_0805_10V4Z
R130
3VS_DELAY
SI4800DY_SO8
H3
@ H_C315D122
U12
8
7
6
5
H2
@ H_C315D122
C225
@ 22U_0805_6.3V6M
H5
@ H_C315D157
JUMP_43X79
C273
C274
@ 10U_1206_16V4Z
B+
@ 1K_0402_5%
Those are at button side
PJ6
@ 0.1U_0402_25V4K
Q5
@ BSS84_SOT23-3
susp#
CF2
CF3
@ SMD40M80 @ SMD40M80
susp# <3,11>
+1.8VS Delay
+1.8VS_D
+1.8VS
PJ7
JUMP_43X79
U13
@ 10U_1206_16V4Z
FD1
@ FIDUCAL
FD2
@ FIDUCAL
FD3
@ FIDUCAL
FD4
@ FIDUCAL
FD5
@ FIDUCAL
FD6
@ FIDUCAL
C275
C276
B+
R131
@ 1K_0402_5%
1
2
SI4800DY_SO8
1.8VS_DELAY
1
2
3
4
S
S
S
G
For IC FIXED
D
D
D
D
8
7
6
5
@ 0.1U_0402_25V4K
For Board FIXED

2
susp#
Q6
@ BSS84_SOT23-3
Compal Secret Data
2005/12/22
Issued Date
Deciphered Date
2006/12/22
5
Title
LVDS Conn/ Screw Hole
LVDS Connector & Screw

Custom
Date:
12/23/05 14:40:19
Rev
1.0
EFL50 LS-2766P
Sheet
1
10
of
13
PJ1
JUMP_43X118
PJ2
PJ3
ISL6227B+
+VGA_CORE
PR1
51_1206_5%
PC3
4.7U_1206_25V6K
+5VALW
PJ5
BST_1.2V
2BST_VGA-16
D
D
D
D
PR3
0_0603_5%
DH_VGA
LX_VGA
UGATE1
PHASE1
PC9
2
5
6
7
8
28
BOOT1
17
0.01U_0402_25V7K
BST_1.2V-1
1
2
PR4
0_0603_5%
BOOT2
23
UGATE2
24
DH_1.2V
25
LX_1.2V
PC11
0.1U_0402_16V7K
2
1
D
D
D
D
0.01U_0402_25V7K
SOFT2
PQ2
SI4800BDY_SO8
G
S
S
S
SOFT1
VCC
12
14
PU1
+1.2V
4
3
2
1
8
7
6
5
PC10
0.1U_0402_16V7K
2
1
PC8
2
VIN
BST_VGA
1
2
3
4
IRF7821_SO8
+1.2VSP
PL2
LGATE2
27
5
6
7
8
DL_1.2V
+ PC14
220U_6.3VM_R15
PQ4
SI4810BDY-T1_SO8
PR9
0_0402_5%
PC15
0.01U_0402_25V7K
4
3
2
1
PGND2
26
9
10
8
15
VOUT1
VSEN1
EN1
PG1
VOUT2
VSEN2
EN2
PG2/REF
20
19
21
16
OCSET2
18
PR10
3.4K_0402_1%
PR19
75K_0402_1%
W/O POWER PLAY
PC16
PR22
PR15
PR14
@ 0_0402_5%
10K_0402_1%
PR18
100K_0402_1%
ISL6227CA-T_SSOP28
2 +3VS_D
68K_0402_1%
susp# <3,10>
OCSET1
1 PR12
0_0402_5%
0.1U_0402_16V7K
<3,10> susp#
PR21
13
11
PC17
PR17
VSE_1.2V
0.1U_0402_16V7K
1
2
PR11 10K_0402_1%
DDR
VSE_VGA
GND
PGND1
LGATE1
ISEN2
ISE_1.2V
3UH_SPC-07040-3R0_5A_30%
G
S
S
S
ISEN1
22
PR8
1.27K_0402_1%
1
2
PHASE2
D
D
D
D
PR7
1.27K_0402_1%
1
2 ISE_VGA
DL_VGA
0_0402_5%
PR16
20K_0402_1%
1
2
3
4
PC19
@ 680P_0402_50V7K
2
1
PR6
0_0402_5%
PC13
0.01U_0402_25V7K
1
2
S PQ5
RHU002N06_SOT323
PR13
1 2
3
0.01U_0402_25V7K
PC20
2
1
2
G
RHU002N06_SOT323
PQ6
PR20
@ 0_0402_5%
1
2
+3VS_D
19.6K_0402_1%
2
1
PR5
2
1
1.15K_0402_1%
10K_0402_5%
PR27
<4>
PR26
10K_0402_5%
1
2 2
G
PC18
0.1U_0402_16V7K
PC7
2.2U_0805_10V6K
+5VALW
POWER_SEL
PR2
2.2_0603_5%
PQ1
S
S
S
G
PQ3
IRF7832_SO8
1
PR23
@ 0_0402_5%
PR25
0_0402_5%
2
1
+VGA_CORE
PR24
4.7_1206_5%
1
PL1
1.4UH_CEP125-1R4_15.5A_20%
1
2
+
PC12
220U_6.3VM_R15
FBMA-L11-322513-151LMA50T_1210
8
7
6
5
S
S
S
G
D
D
D
D
+VGA_CORE
PC6
0.1U_0603_25V7K
PD1
DAP202U_SOT323
+VGA_COREP
PL3
PC5
4.7U_0805_6.3V6K
JUMP_43X79
PC4
4.7U_1206_25V6K
+1.2VS
B+
PC2
10U_1206_25VAK
PC1
10U_1206_25VAK
JUMP_43X118
JUMP_43X118
+1.2VSP
+VGA_COREP
@ 0_0402_5%
With POWER PLAY
POWER_SEL
Low
High
1.0V
0.95V
+VGA_CORE
PR5=1.15K,PR16=20K,PR13=19.6K
PJ3,PJ1,PJ2,PJ4 short
PR5=1.15K,PR16=20K
PJ3,PJ1,PJ2,PJ4 short
Compal Secret Data
2005/12/22
Issued Date
Deciphered Date
2006/12/22
5
Title
Power
Custom
Date:
12/23/05 14:40:19
Power
Rev
1.0
EFL50 LS-2766P
Sheet
1
11
of
13
Version change list (P.I.R. List)

=========== 2005/12 R0.2 ==================
D
01. Reserve +3VS and +1.8VS delay circuit and reserve Jump. == To meet ATI PWR sequence.
Reserve PJ6, PJ7, U12, U13, C273, C274, C275, C276,
Q5, Q6, R130 and R131.
02. Change C42, C45, C46, C47 and C51, from 0.1U to 1U. == For 3D hang issue.
03. Change C101, from 0.1U to 1U.
== For 3D hang issue.
04. Add C44 as 330U
== For 3D hang issue.
05. Delete R63, 10K_0402_5%
== PCIE TX power saving.
B
Compal Secret Data
Issued Date
2005/12/22
Deciphered Date
2006/12/22
5
Title

P.I.R.

Custom
EFL50 LS-2766P
Date:
12/23/05 14:40:19
Rev
1.0
Sheet
1
12
of
13
ZZZ
U8
DA800005F10
--PCB ZKD LS-2766P
REV1 VGA/B
SA00000JW00
--S IC D2 16M16/600
HY5PS561621AFP-33
FBGA
DA800005F10
HYN64@
SA00000JW00
U9
SA00000JW00
--S IC D2 16M16/600
HY5PS561621AFP-33
FBGA
HYN64@
SA00000JW00
U10
SA00000JW00
--S IC D2 16M16/600
HY5PS561621AFP-33
FBGA
HYN128@ SA00000JW00
U11
SA00000JW00
--S IC D2 16M16/600
HY5PS561621AFP-33
FBGA
HYN128@ SA00000JW00
B
Compal Secret Data
Issued Date
2005/12/22
Deciphered Date
2006/12/22
5
Title

For BOM

Custom
EFL50 LS-2766P
Date:
12/23/05 14:40:19
Rev
1.0
Sheet
1
13
of
13

ACER - Aspire - 5500 - Compal - EFL50 - LS-2766P - SCHEMA

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ACER - Aspire - 5500 - Compal - EFL50 - LS-2766P - SCHEMA

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5

Mini (EFL50) ATI VGA/B M52-P

Compal Secret Data

Compal Electronics, Inc.

M54P/M52P BLOCK DIAGRAM

VGA_CRT_R, VGA_CRT_G, VGA_CRT_B, DACA_HSYNC, DACA_VSYNC

Compal Secret Data

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Secret Data

Straps: (Internal pull down)

0: 50% TX output swing

(must be pulled to 3.3V at reset using)

For No External ROM:

GPIO[9, GPIO[9]=1 External ROM Attached

0: Slave VIP host device present

Low -> VDDC=1.0V+-5% Performance Mode for M52

Vedio Memory Config. (VGA Internal PD)

128MB 16M16 (300MHz)

128MB 16M16 (300MHz)

Memory Aperture Size Select

Internal SS, Programmed via register-GENERICA = NC

Close to VGA Cbip

Compal Secret Data

PCI-Express Data Bus Lane Reversal and Polarity Inversion

VIP HOST/ EXTERNAL TMDS

Keep away from other signal at last 25mils

Compal Electronics, Inc.

Size Document Number

LVDS PLL&I/O GND

Use 15mils trace

if no DVI , dvi_det pull low

Compal Secret Data

Compal Electronics, Inc.

Size Document Number

Compal Secret Data

Compal Electronics, Inc.

Size Document Number

N29 2000mA 22U_0805_6.3V6M

Compal Secret Data

LVDS PLL, I/O

1000mA for GDDR1

Compal Electronics, Inc.

Size Document Number

Default VRAM chip is SAM: SA00000YC00.

Compal Secret Data

As close as ppossible to related pin

Compal Electronics, Inc.

Size Document Number

Default VRAM chip is SAM: SA00000YC00.

2128@ 0_0402_5% B1_A_BA0

Compal Secret Data

As close as ppossible to related pin

Compal Electronics, Inc.

Size Document Number

LCD/PANEL BD. CONN.

<5> VGA_LVDSBC<5> VGA_LVDSBC+

<5> VGA_LVDSB0<5> VGA_LVDSB0+

Those are at button side

For Board FIXED

Compal Electronics, Inc.

Compal Secret Data