COMP306L Machine Problems

Angelo R. dela Cruz, ECE

COMP306L UST-ECE engradc (c)2009

Exercise 1: Controlled LEDs

module exercise1 (clk, rst, led); input clk, rst; //input ports reg [7:0] state; //output port register output [7:0] led; //output ports assign led = state; /*output port has the same contents as state*/
COMP306L UST-ECE engradc (c)2009

Exercise 1
//Every positive edge of the clock
always @ (posedge clk) if (rst == 0) //if rst port is pressed state <= 8'b11111111; else state [0] <= 0; endmodule
COMP306L UST-ECE engradc (c)2009

Save as: exercise1.v

Creating Pin Assignment File

File > New > Other files (.tcl file)

COMP306L UST-ECE engradc (c)2009

Save as: pin_assign.tcl

Activity 1

Modify exercise1.v wherein the display of upper nibble LEDs will be the complement of the lower nibble LEDs if SW3, SW4 and dip SW8 is at ON (low) state.

COMP306L UST-ECE engradc (c)2009

Activity 2: Controlled LED

Modify exercise1.v so that the D1 LED is controlled by a push button that is, when the push button is pressed and D1 LED is turned off, D1 LED will light up. However, when the push button is pressed and D1 LED is lit up, D1 LED will be turned off.

COMP306L UST-ECE engradc (c)2009

Exercise 3: Blinking LEDs

module exercise3 (clk, rst, led); input clk, rst; reg [7:0] state; reg [23:0] counter; output [7:0] led; assign led = state;

COMP306L UST-ECE engradc (c)2009

Exercise 3: Blinking LEDs

always @ (posedge clk) if (rst == 0) counter <= 0; else if (counter == 8000000) counter <= 0; else counter <= counter+1;
COMP306L UST-ECE engradc (c)2009

Exercise 3: Blinking LEDs

always @ (posedge clk) if (rst == 0) state <= 8'b11111111; else if (counter == 8000000) state [0] <= ~state [0]; endmodule
COMP306L UST-ECE engradc (c)2009

Activity 3: Blinking LEDs

Modify exercise3.v such that the delay is controlled by push-button SW4. If SW4 is pressed, the delay is 2 sec, when SW4 is high the delay is 0.5 sec. Provide pins for reset (SW1) and clock.

COMP306L UST-ECE engradc (c)2009

Activity 4: LED Pattern

Modify exercise3.v to display the LED pattern as shown below:

A B

COMP306L UST-ECE engradc (c)2009

Hint: Use case statements

Case Statement Example

case (A) 0 : A <= 1; 1 : A <= 2; 2 : A <= 3; 3 : A <= 4; 4 : A <= 0; default : A <= 0; endcase
COMP306L UST-ECE engradc (c)2009

Exercise 5: LED Operation using Switches

Clock SW

SW_NOT (reg)

AND

TRIG (reg)

COMP306L UST-ECE engradc (c)2009

Exercise 5: LED Operation using Switches

SW
SW_NOT TRIG

TRIG

CLK

COMP306L UST-ECE engradc (c)2009

Exercise 5: LED Operation using Switches

always @ (posedge clk) begin sw_not <= ~sw; trig <= sw & sw_not; end
COMP306L UST-ECE engradc (c)2009

Activity 5: LED Operation using Switches

Modify activity 4. The display of the LEDs is controlled by push-button switch SW4. Provide pin for reset (SW1).

COMP306L UST-ECE engradc (c)2009

Exercise 6: LED-Segment Display

module exercise6 (clk,rst,m1,m2,m3,m4,a,b,c,d,e,f, g,dp); input clk, rst; reg [3:0] state; reg [6:0] number; output m1, m2, m3, m4, a, b, c, d, e, f, g, dp; parameter number4 = 7'b1001100;

assign {m4, m3, m2, m1} = state; assign {a, b, c, d, e, f, g} = number; assign dp = 1;
COMP306L UST-ECE engradc (c)2009

Exercise 6: LED-Segment Display

always @ (posedge clk) if (rst == 0) state <= 4'b0000; else state <= 4'b0001;
always @ (posedge clk) if (rst == 0) number <= 7'h7f; else number <= number4; endmodule
COMP306L UST-ECE engradc (c)2009

Activity 6

Using the debounce switch in exercise5, modify exercise6.v such that the seven-segment will display a count-up sequence every time push-button SW2 is pressed. Provide reset button (SW1)

COMP306L UST-ECE engradc (c)2009

Exercise 7: 7-Segment Display Part 2

module exercise7 (clk, rst, m1, m2, m3, m4, a, b, c, d, e, f, g, dp); input clk, rst; reg [3:0] state; reg [20:0] counter; reg [6:0] number; output m1, m2, m3, m4, a, b, c, d, e, f, g, dp; parameter parameter parameter parameter number1 number2 number3 number4 = = = = 7'b1001111; 7'b0010010; 7'b0000110; 7'b1001100;

assign {m4, m3, m2, m1} = state; assign {a, b, c, d, e, f, g} = number; assign dp = 1;
COMP306L UST-ECE engradc (c)2009

Exercise 7: 7-Segment Display Part 2

always @ (posedge clk) if (rst == 0) counter <= 0; else if (counter == 16000) counter <= 0; else counter <= counter+1;

COMP306L UST-ECE engradc (c)2009

Exercise 7: 7-Segment Display Part 2

always @ (posedge clk) if (rst == 0) state <= 4'b0000; else if (counter == 16000) case (state) 4b0000: state <= 4'b0001; 4b0001: state <= 4'b0010; 4b0010: state <= 4'b0100; 4b0100: state <= 4'b1000; 4b1000: state <= 4'b0000; default: state <= 4'b0000; endcase COMP306L UST-ECE
engradc (c)2009

Exercise 7: 7-Segment Display Part 2

always @ (posedge clk) if (rst == 0) number <= 7'h7f; else case (state) 4b1000: number 4b0100: number 4b0010: number 4b0001: number default: number endcase endmodule
COMP306L UST-ECE engradc (c)2009

<= <= <= <= <=

number1; number2; number3; number4; 7'h7f;

Activity 7

Modify exercise7.v such that the four LED-segment will shift to the right the display characters 1234 for every 1 second. Provide reset button (SW1)

COMP306L UST-ECE engradc (c)2009

Exercise 8: Counter
module exercise8 (clk, rst, m1, m2, m3, m4, a, b, c, d, e, f, g, dp); input clk, rst; output m1, m2, m3, m4; output a, b, c, d, e, f, g, dp; reg [23:0] counter; reg [19:0] state; reg [7:0] number; assign {m1, m2, m3, m4} = state; assign {a, b, c, d, e, f, g} = number; assign dp = 1; parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter number1 number2 number3 number4 number5 number6 number7 number8 number9 number0 = = = = = = = = = = 7'b1001111; 7'b0010010; 7'b0000110; 7'b1001100; 7'b0100100; 7'b0100000; 7'b0001111; 7'b0000000; 7'b0000100; 7'b0000001;

COMP306L UST-ECE engradc (c)2009

Exercise 8: Counter
always @ (posedge clk) if (rst == 0) counter <= 0; else if (counter == 16000000) counter <= 0; else counter <= counter+1;
always @ (posedge clk) if (rst == 0) state <= 4'b0000; else state <= 4'b0001;
COMP306L UST-ECE engradc (c)2009

Exercise 8: Counter
always @ (posedge clk) if (rst == 0) number <= number0; else if (counter == 16000000) case (number) number0: number <= number1; number1: number <= number2; number2: number <= number3; number3: number <= number4; number4: number <= number5; number5: number <= number6; number6: number <= number7; number7: number <= number8; number8: number <= number9; number9: number <= number0; default: number <= number0; COMP306L UST-ECE endcase engradc (c)2009 endmodule

Activity 8
1.

2.

Create Verilog HDL code that will count from 00 to 99, use 1 second delay. Create Verilog HDL code that will count from 00 to 99 every time SW4 is triggered (refer to exercise5)

COMP306L UST-ECE engradc (c)2009