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1. ARCHITECTURE
• Architecture of the TMS320C54XX comprises of:
CPU
Memory
ON-chip peripherals
• This DSP uses modified Harvard Architecture
• Provides a high degree parallelism due to separate
program and data spaces which allows
simultaneous access to program instructions and
data.
• They have 1 program and 3 data memory spaces
1. CPU
• Contains:
40-bit ALU
Two 40-bit accumulators
Barrel shifter
17× 17-bit multiplier
40-bit adder
Compare, select and store unit(CSSU)
Data address generation unit(DAGEN)
Program address generation unit(PAGEN)
1.1 ARITHMETIC LOGIC UNIT(ALU)