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A

Desert Eagle
LA-3161P

Compal confidential
2

HEL80/HEL81 Schematics Document


Mobile Yonah uFCPGA with Intel
Calistoga_GM/PM+ICH7-M
3

Thursday, February 23, 2006

Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.


Cover Sheet

Size Document Number


Custom HEL80 LA-3161P

Rev
0.3

Date:

Sheet
E

of

43

hexainf@hotmail.com

REV:0.3

Compal Confidential

Thermal Sensor
ADM1032

Yonah

Fan Control

Model Name : HEL80


File Name : LA-3161P

page 4

Clock Generator
SLG8LP465VTR

page 4

uPGA-478 Package

page 15

page 4-6

ZZZ1
1

CRT & TV-out

15W_PCB

H_A#(3..31)

FSB
533/667MHz

H_D#(0..63)

page 16

LVDS

LCD Conn.

Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2

Intel 945PM/GM

page 16

Dual Channel
1.8V DDRII 400/533

uFCBGA-1466
PCI-Express

page 13,14

BANK 0, 1, 2, 3

page 7-12

nVidia G73M

VGA board Conn.

DMI

PCI BUS

3.3V 33 MHz
IDSEL:AD16
(PIRQE#,
GNT#0,
REQ#0)

IDSEL:AD20
(PIRQA/B#,
GNT#2,
REQ#2)

IEEE 1394

ENE CB714

page 25

1394 Conn.
page 25

S-ATA

CardBus

VT6311S

page 23

Slot 0

Intel ICH7-M
BGA-652

3.3V ATA-100

3 in 1
socket

page 24

page 24

IDE

S-ATA Bridge
Marvell 8040
page 22

HD Codec

MDC 1.5
Conn
page 27

page 17

3.3V 24.576MHz/48Mhz

HD Audio

3.3V 48MHz

USB 2.0

Audio AMP

ALC883

page 29

page 28

page 18-21

CDROM
Conn.
page 22

USB port 1

New Card
Socket page
S-ATA HDD
Conn.

USB port 0

MINI CARD x2
35

LAN RJ45

page 27

USB Conn. x1

page 26

PCI Express

USB port5

Bluetooth
Conn page 27

page 34

Realtek
LAN 8111B

page 22

page 26

LPC BUS

TPM1.2

SLB9635 TT 1.2

PATA Conn.

page 35

DC-DC

page 22

DC-IN'
page

ENE KB910L

page

+1.05VP/+1.8VP

page 31

BATT OVP
INT KB /PWR BTN /Debug Port

Int.KBD

page

Touch Pad

page 30

page 30

page 34

page

BIOS

CIR
page 35

page

40

+0.9VPS
/+1.5VPS /
2.5VPS page

41

37

CHARGER
D2D /CMOS /FP /LID /KILL#

33

36

38

page 32

page 33

+3/5 VAWL

page

VCORE

39

page

42

TP /SW /USB OC /LED


2005/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

page 34

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Block Diagrams
Size Document Number
Custom

Rev
0.2

HEL80 LA-3161P

Date:

Sheet

Thursday, February 23, 2006


E

of

43

Voltage Rails

SKU ID Table
Vcc
Ra

+5VS
+3VS

power
plane

3.3V +/- 5%
100K +/- 5%
Rb
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC

Board ID

+2.5VS

0
1
2
3
4
5
6
7

+1.8VS

LDO3
LDO5

+5VALW

+1.8V

+1.5VS

+3VALW

+5V

+1.2VS
+VGA_CORE
+0.9VS

State

+CPU_CORE
+VCCP

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

SKU ID
* 0
1
2
3
4
5
6
7

O MEANS ON

MARK

S3 : STR
S4 : STD
S5 : SOFT OFF

X MEANS OFF

External PCI Devices


Device

IDSEL#

REQ#/GNT#

Interrupts

CardBus

AD20

PIRQA/B

13 94

AD16

PIRQE

V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V

+CPU_CORE

CPU

+VCCP

CPU
NB

+5VS

HEL80/81 SKU
HEL80 SKU
HEL81 SKU
TEST MODE

BOM Structure
S5 S4/AC & Battery
don't exist

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

PORT

NC FOR ALL

UMA@

Internal 945GM

VGA@

External G7xM

TPM@

TPM1.2

CIR@

CIR

1394@

1394

SATA@

SATA HDD

8040@

PATA HDD

IOMP@

IOMP

15W@

15W PANEL

APA@

HP out from AMP

HPA@

HP out from HP AMP

HP@

HP out from CODEC

0
1
2
3
4
5
6
7

NB
EXPRESS CARD
CLK_GEN
LCDVCC
VGA CARD (G7XM)
SB
R5C832
BIOS ROM
KB910L
CB1410

480mA
1A
200mA
1A
655mA
680mA
mA
15mA
200mA
mA

+2.5VS

VGA CARD (G7XM)


NB

130mA
(143mA)

DDR2_DIMM
NB (667Mhz)

+1.8V

Address

Device

Address

Smart Battery

0001 011X b

ADM1032

1001 100X b

EEPROM(24C16/02)

1010 000X b

ICH7 SM Bus address


Clock Generator
(SLG8LP465VTR)

1101 001Xb

DDRII DIMM0

1010 000Xb

DDRII DIMM1

1010 010Xb

2005/10/06

Issued Date

Deciphered Date

1A

DDR2_DIMM

2A

SB

+1.5VS

NB
SB
MiniCard
EXPRESS CARD
VGA CARD (G7XM)

2006/10/06

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

GDDR2

+1.5V

Compal Secret Data

Security Classification

10mA

DDR2_DIMM

+0.9VREF
+0.9VS

Address

6A
4.06A

EC SM Bus2 address

Device

Device

8A
3.1A

GDDR2
VGA CARD (G7XM)

+1.8VS

EC SM Bus1 address

1A
1.5A
1.8A
300mA
1A
mA
70mA
3A

+3VS

DEVICE
LEFT SIDE
BLUE TOOTH
RIGHT SIDE
CMOS
RIGHT SIDE
FINGER PRINTER
NEW CARD
TV

2.5A
9.8A
(14.7A)

EXPRESS CARD
HDD
ODD
MDC
APA2066
TPA0211
AD1986
USB PORT * 6

USB PORT LIST

FUNCTION

36A

Title

40mA
8.9A(13.8A)
3.8A
1A
0.65A
2A

Compal Electronics, Inc.


Notes List

Size Document Number


Custom HEL80 LA-3161P
Date:

Thursday, February 23, 2006

Rev
0.2
Sheet

of

43

hexainf@hotmail.com

+B

V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V

mA
160mA

KB910L
SB
RTL8110SBL/CL

+3VALW

+VCCP
This shall place near CPU
R130 1
2 56_0402_5%

ITP_TDI
H_D#[0..63] <7>

<7> H_REQ#[0..4]

<7> H_ADSTB#0
<7> H_ADSTB#1

J4
L4
M3
K5
M1
N2
J1
N3
P5
P2
L1
P4
P1
R1
Y2
U5
R3
W6
U4
Y5
U2
R4
T5
T3
W3
W5
Y4
W2
Y1

A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

K3
H2
K2
J3
L5

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#

H_ADSTB#0
H_ADSTB#1

L2
V4

ADSTB0#
ADSTB1#

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

E22
F24
E26
H22
F23
G25
E25
E23
K24
G24
J24
J23
H26
F26
K22
H25
N22
K25
P26
R23
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
T25
N24
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

DINV0#
DINV1#
DINV2#
DINV3#

J26
M26
V23
AC20

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

H23
M24
W24
AD23
G22
N25
Y25
AE24

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

A20M#
FERR#
IGNNE#
INIT#
LINT0
LINT1

A6
A5
C4
B3
C6
B4

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

STPCLK#
SMI#

D5
A3

H_STPCLK#
H_SMI#

YONAH

ADDR GROUP

DATA GROUP

CLK_CPU_BCLK A22
CLK_CPU_BCLK# A21

<7>
<7>
<7>
<7>
<7>
<7>
R69
<7>
56_0402_5%
<7>
1
2
<7>
<7>

+VCCP

<7>

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRD Y#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_RESET#

H_RS#[0..2]

<7>

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

H_TRDY#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

<20> ITP_DBRESET#
<7>
H_DBSY#
<19> H_DPSLP#
<19,42> H_DPRSTP#
<7>
H_DPWR#
<42> H_PROCHOT#
+VCCP

R68

68_0402_5%
<19> H_PWRGOOD
<7,19> H_CPUSLP#

R71
R70

2 @ 1K_0402_5%
2 51_0402_5%

1
1

H1
E2
G5
F1
H5
F21
G6
E4
D20
H4
B1
F3
F4
G3
G2

AD4
AD3
AD1
AC4

ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
HITM#
IERR#
LOCK#
RESET#

HOST CLK

CONTROL

RS0#
RS1#
RS2#
TRDY#

BPM0#
BPM1#
BPM2#
BPM3#

ITP_DBRESET# C20
H_DBSY#
E1
H_DPSLP#
B5
H_DPRSTP#
E5
H_DPWR#
D24
ITP_BPM#4
AC2
ITP_BPM#5
AC1
H_PROCHOT# D21

DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#

H_PW RGOOD D6
H_CPUSLP#
D7
ITP_TCK
AC5
ITP_TDI
AA6
ITP_TDO
AB3
TEST1
C26
TEST2
D25
ITP_TMS
AB5
ITP_TRST#
AB6

PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

H_THERMDA
A24
H_THERMDC
A25
H_THERMTRIP# C7

<7,19> H_THERMTRIP#

BCLK0
BCLK1

H_THERMDA, H_THERMDC routing together.


Trace width / Spacing = 10 / 10 mil

MISC

R82

R129

ITP_TDO

R128 1

2 56_0402_5%

56_0402_1%

ITP_BPM#5

R127 1

2 56_0402_5%

ITP_TRST#

R119 1

2 56_0402_5%

ITP_TCK

R120 1

2 56_0402_5%

2 @ 200_0402_5%
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4

PAD T14
PAD
PAD
PAD
PAD
PAD

T18
T20
T21
T17
T19

Thermal Sensor ADM1032AR


+3VS

C405
0.1U_0402_16V4Z

1
U24

C406
1
2

VDD

SCLK

EC_SMB_CK2

H_THERMDA

D+

SDATA

EC_SMB_DA2

H_THERMDC

D-

ALERT#

THERM#

GND

2200P_0402_50V7K

THERM#

EC_SMB_CK2 <31>
EC_SMB_DA2 <31>

ADM1032ARMZ-2REEL_MSOP8

2
10K_0402_5%

Address:100_1100

Note : ADM1032 has no SO8 lead free ones.Only MSO8

+5VS

D16
1SS355_SOD323

+5VS
C399
1
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

10U_1206_16V4Z
2

D15
2

<7>
<7>
<7>
<7>

U23

H_DSTBN#[0..3] <7>
<31> EN_FAN1

1
2
3
4

+VCC_FAN1
EN_FAN1

VEN
VIN
VO
VSET

1
8
7
6
5

GND
GND
GND
GND

LEGACY CPU

THERMDA
THERMDC
THERMTRIP#

1N4148_SOT23

G993P1UF_SOP8
H_DSTBP#[0..3] <7>
1
+3VS

1000P_0402_50V7K

10K_0402_5%

H_A20M# <19>
H_FERR# <19>
H_IGNNE# <19>
H_INIT# <19>
H_INTR
<19>
H_NMI
<19>

40mil

JP2

+VCC_FAN1

<31> FAN_SPEED1
1

H_STPCLK# <19>
H_SMI#
<19>

C397
2

10U_1206_16V4Z
C401
1
2

R297

THERMAL
DIODE

R303
1

+3VS

<15> CLK_CPU_BCLK
<15> CLK_CPU_BCLK#

ITP_DBRESET#

ITP_TMS

JP1A
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_A#[3..31]

<7>

C402
1000P_0402_50V7K

1
2
3

1
2
3

4
5

GND
GND

ACES_85205-03001

TYCO_1-1674770-2_Yonah~D
ME@

+VCCP
A

R72

2 2

@ 56_0402_5%

Compal Secret Data

Security Classification

B
E

OCP#

H_PROCHOT# 3

Q4
@ MMBT3904_SOT23

2006/10/06

Deciphered Date

Title

2005/11/07

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Compal Electronics, Inc.


Yonah CPU in mFCPGA479

<20>

Modified Q4 part number to SB039040000.


5

2005/10/06

Issued Date
OCP#

Size Document Number


Custom HEL80 LA-3161P
Date:

Rev
0.2
Sheet

Thursday, February 23, 2006


1

of

43

+VCCP

+CPU_CORE
JP1B

JP1C
D

+CPU_GTLREF

<42>
<42>

+CPU_CORE
R126
100_0402_1%
1
2

1K_0402_1%

VCCSENSE

R134
100_0402_1%
1
2

R67

VCCSENSE
VSSENSE

AF7
AE7

VCCSENSE
VSSSENSE

B26

VCCA

K6
J6
M6
N6
T6
R6
K21
J21
M21
N21
T21
R21
V21
W21
V6
G21

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

H_PSI#

AE6

PSI#

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

AD6
AF5
AE5
AF4
AE3
AF2
AE2

VID0
VID1
VID2
VID3
VID4
VID5
VID6

VCCSENSE
VSSENSE

+1.5VS
+VCCP

VSSENSE
C146
0.01U_0402_16V7K

C144
10U_0805_10V4Z

2K_0402_1%

Close to CPU pin AD26


within 500mils.

Close to CPU pin


within 500mils.

Trace / Width = 4 / 25 mils Trace / Width = 18 / 50 mils

CPU_BSEL

CPU_BSEL2

CPU_BSEL1

CPU_BSEL0

133

166

<42>

H_PSI#

<42>
<42>
<42>
<42>
<42>
<42>
<42>

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

AD26

+CPU_GTLREF
<15> CPU_BSEL0
<15> CPU_BSEL1
<15> CPU_BSEL2

B22
B23
C21

BSEL0
BSEL1
BSEL2

COMP0
COMP1
COMP2
COMP3

R26
U26
U1
V1

COMP0
COMP1
COMP2
COMP3

R80
27.4_0402_1%
1

R81
54.9_0402_1%
1

R123
27.4_0402_1%
1

R131
54.9_0402_1%
1

+CPU_CORE

Resistor placed within


0.5" of CPU pin.Trace
should be at least 25
mils away from any
other toggling signal.

COMP 0/2Trace / Width = 18 / 25 mils


COMP 1/3Trace / Width = 5 / 25 mils

GTLREF

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

E7
AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17
D2
F6
D3
C1
AF1
D22
C23
C24
AA1
AA4
AB2
AA3
M4
N5
T2
V3
B2
C3
T22
B25

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

YONAH

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AB26
AA25
AD25
AE26
AB23
AC24
AF24
AE23
AA22
AD22
AC21
AF21
AB19
AA19
AD19
AC19
AF19
AE19
AB16
AA16
AD16
AC16
AF16
AE16
AB13
AA14
AD13
AC14
AF13
AE14
AB11
AA11
AD11
AC11
AF11
AE11
AB8
AA8
AD8
AC8
AF8
AE8
AA5
AD5
AC6
AF6
AB4
AC3
AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1

AE18
AE17
AB15
AA15
AD15
AC15
AF15
AE15
AB14
AA13
AD14
AC13
AF14
AE13
AB12
AA12
AD12
AC12
AF12
AE12
AB10
AB9
AA10
AA9
AD10
AD9
AC10
AC9
AF10
AF9
AE10
AE9
AB7
AA7
AD7
AC7
B20
A20
F20
E20
B18
B17
A18
A17
D18
D17
C18
C17
F18
F17
E18
E17
B15
A15
D15
C15
F15
E15
B14
A13
D14
C13
F14
E13
B12
A12
D12
C12
F12
E12
B10
B9
A10
A9
D10
D9
C10
C9
F10
F9
E10
E9
B7
A7
F7

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

TYCO_1-1674770-2_Yonah~D
ME@

YONAH

POWER, GROUND

K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

TYCO_1-1674770-2_Yonah~D
ME@

Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


Yonah CPU in mFCPGA479

Size Document Number


Custom HEL80 LA-3161P
Date:

Rev
0.2

Thursday, February 23, 2006

Sheet
1

of

43

hexainf@hotmail.com

R79

POWER, GROUNG, RESERVED SIGNALS AND NC

+CPU_CORE

1
Place these capacitors on L8
(North side,Secondary Layer)

C411
22U_0805_6.3V6M

C417
22U_0805_6.3V6M

C175
22U_0805_6.3V6M

C193
22U_0805_6.3V6M

C443
22U_0805_6.3V6M

C191
22U_0805_6.3V6M

C206
22U_0805_6.3V6M

C208
22U_0805_6.3V6M

+CPU_CORE

1
Place these capacitors on L8
(North side,Secondary Layer)

C416
22U_0805_6.3V6M

C212
22U_0805_6.3V6M

C437
22U_0805_6.3V6M

C201
22U_0805_6.3V6M

C409
22U_0805_6.3V6M

C211
22U_0805_6.3V6M

C189
22U_0805_6.3V6M

C438
22U_0805_6.3V6M

+CPU_CORE

1
Place these capacitors on L8
(Sorth side,Secondary Layer)

C207
22U_0805_6.3V6M

C192
22U_0805_6.3V6M

C428
22U_0805_6.3V6M

C412
22U_0805_6.3V6M

C195
22U_0805_6.3V6M

C427
22U_0805_6.3V6M

C204
22U_0805_6.3V6M

C199
22U_0805_6.3V6M

+CPU_CORE

1
Place these capacitors on L8
(Sorth side,Secondary Layer)

C174
22U_0805_6.3V6M

C188
22U_0805_6.3V6M

C442
22U_0805_6.3V6M

C196
22U_0805_6.3V6M

C202
22U_0805_6.3V6M

C200
22U_0805_6.3V6M

C410
22U_0805_6.3V6M

C205
22U_0805_6.3V6M

Mid Frequence Decoupling

1
+
2

1
+
2

1
+
2

C415
330U_D2E_2.5VM_R9

C413
330U_D2E_2.5VM_R9

C431
330U_D2E_2.5VM_R9

C197
330U_D2E_2.5VM_R9

C198
330U_D2E_2.5VM_R9

South Side Secondary

C414
330U_D2E_2.5VM_R9

+CPU_CORE

ESR <= 1.5m ohm


Capacitor > 1980uF

1
+

North Side Secondary

2
B

+VCCP

1
C131
220U_D2_2VMR15

+
2

C209
0.1U_0402_16V4Z

C176
0.1U_0402_16V4Z

C178
0.1U_0402_16V4Z

C177
0.1U_0402_16V4Z

C210
0.1U_0402_16V4Z

C213
0.1U_0402_16V4Z

Place these inside


socket cavity on L8
(North side
Secondary)

Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


CPU Bypass capacitors

Size Document Number


Custom HEL80 LA-3161P
Date:

Rev
0.2
Sheet

Thursday, February 23, 2006


1

of

43

R31
54.9_0402_1%
2
1

R24
24.9_0402_1%
2
1

HADSTB#0
HADSTB#1

B9
C13

H_ADSTB#0
H_ADSTB#1

HCLKN
HCLKP

AG1
AG2

CLK_MCH_BCLK#
CLK_MCH_BCLK

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

K4
T7
Y5
AC4
K3
T6
AA5
AC5

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

<20>
<20>
<20>
<20>

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

<20>
<20>
<20>
<20>

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

<20>
<20>
<20>
<20>

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

J7
W8
U3
AB10

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

HCPURST#
HADS#
HTRDY#
HDPWR#
HDRDY#
HDEFER#
HHITM#
HHIT#
HLOCK#
HBREQ0#
HBNR#
HBPRI#
HDBSY#
HCPUSLP#

B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3

H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRD Y#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#

HRS0#
HRS1#
HRS2#

B4
E6
D6

H_RS#0
H_RS#1
H_RS#2

H_ADSTB#0 <4>
H_ADSTB#1 <4>

<13>
<13>
<14>
<14>

CLK_MCH_BCLK# <15>
CLK_MCH_BCLK <15>
H_DSTBN#[0..3] <4>

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

<13>
<13>
<14>
<14>

<4>
<4>
<4>
<4>

1
1

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

AC35
AE39
AF35
AG39

DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

AE37
AF41
AG37
AH41

DMITXN0
DMITXN1
DMITXN2
DMITXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

AC37
AE41
AF37
AG41

DMITXP0
DMITXP1
DMITXP2
DMITXP3

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

AY35
AR1
AW7
AW40

SM_CK0
SM_CK1
SM_CK2
SM_CK3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

AW35
AT1
AY7
AY40

SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

AU20
AT20
BA29
AY29

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

DDR_CS0_DIMMA# AW13
DDR_CS1_DIMMA# AW12
DDR_CS2_DIMMB# AY21
DDR_CS3_DIMMB# AW21

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

T12
T1

R33
R32
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

+1.8V

AE35
AF39
AG35
AH39

PAD
PAD

M_ODT0
M_ODT1
M_ODT2
M_ODT3
2 80.6_0402_1%
2 80.6_0402_1%

AL20
AF10

SM_OCDCOMP0
SM_OCDCOMP1

BA13
BA12
AY20
AU21

SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

AV9
AT9
AK1
AK41

H_RESET# <4>
H_ADS# <4> <20,42> DPRSLPVR
H_TRDY# <4>
H_DPWR# <4>
H_DRDY# <4>
<17,18,20,22,26,27,31,35> PLT_RST#
H_DEFER# <4>
H_HITM# <4>
H_HIT#
<4>
H_LOCK# <4>
H_BR0# <4>
H_BNR# <4>
H_BPRI# <4>
H_DBSY# <4>
H_CPUSLP# <4,19>

PM_BMBUSY#
G28
<20> PM_BMBUSY#
PM_EXTTS#0
F25
<13,14> PM_EXTTS#0
PM_EXTTS#1
1
H26
H_THERMTRIP#
G6
<4,19> H_THERMTRIP#
ICH_POK
AH33
<20,31> ICH_POK
PLTRST_R#
2
1
AH34
R60
100_0402_1%
K28
<18> MCH_ICH_SYNC#

D_REF_CLKN
D_REF_CLKP
D_REF_SSCLKN
D_REF_SSCLKP
CLK_REQ#

M_ODT0
M_ODT1
M_ODT2
M_ODT3
SMRCOMPN
SMRCOMPP

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
G_CLKP
G_CLKN

M_OCDOCMP0
M_OCDOCMP1

+DDR_MCH_REF
R93
0_0402_5%
2

CFG

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

CLK

<20>
<20>
<20>
<20>

<13>
<13>
<14>
<14>
<13>
<13>
<14>
<14>

H_DSTBP#[0..3] <4>

Description at page 11.

U22B

H_REQ#[0..4] <4>

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

HDINV#0
HDINV#1
HDINV#2
HDINV#3

VGA@

<13>
<13>
<14>
<14>

D8
G8
B8
F8
A8

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

PM

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

SM_RCOMPN
SM_RCOMPP

ICH_SYNC#

CALISTOGA_FCBGA1466~D
UMA@

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
CFG3
PAD
CFG4
PAD
CFG5
CFG6
PAD
CFG7
CFG8
PAD
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
PAD
CFG15
PAD
CFG16
CFG17
PAD
CFG18
CFG19
CFG20

MCH_CLKSEL0 <15>
MCH_CLKSEL1 <15>
MCH_CLKSEL2 <15>
T9
T3
CFG5
<11>
T10
CFG7
<11>
T7
CFG9
<11>
CFG10
<11>
CFG11
<11>
CFG12
<11>
CFG13
<11>
T4
T8
CFG16
<11>
T2
CFG18
<11>
CFG19
<11>
CFG20
<11>

AG33 CLK_MCH_3GPLL
AF33 CLK_MCH_3GPLL#
A27
A26

H32

A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1

RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8
RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13

T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35

CLK_MCH_DREFCLK# <15>
CLK_MCH_DREFCLK <15>

MCH_CLKREQ#

MCH_CLKREQ# <15>

+3VS

H_RS#[0..2] <4>
+1.8V

PM_EXTTS#0

R51
10K_0402_5%
2
1

PM_EXTTS#1

R56
@ 10K_0402_5%
2
1

1
R27

+VCCP

+VCCP
1
R22
2

221_0603_1%

1
R25
2

221_0603_1%

100_0402_1%

+H_SWNG1

0.1U_0402_16V4Z
C9

1
R23

100_0402_1%

0.1U_0402_16V4Z
C16

1
R29

100_0402_1%

0.1U_0402_16V4Z

1
C24

2
1
R38

+H_SWNG0

+H_VREF
200_0603_1%

R34

R26
100_0402_1%
2

+VCCP

0.1U_0402_16V4Z
C14

+DDR_MCH_REF

100_0402_1%

Layout Note:
H_XRCOMP / H_YRCOMP / +H_VREF / +H_SWNG0 /
+H_SWNG1 trace width and spacing is 10/20.

CLK_MCH_SSCDREFCLK# <15>
CLK_MCH_SSCDREFCLK <15>

Layout Note:
+DDR_MCH_REF
trace width and
spacing is 20/20.

CALISTOGA_FCBGA1466~D
UMA@

CLK_MCH_3GPLL <15>
CLK_MCH_3GPLL# <15>

CLK_MCH_DREFCLK#
CLK_MCH_DREFCLK

C40 CLK_MCH_SSCDREFCLK#
D41 CLK_MCH_SSCDREFCLK

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

SM_VREF0
SM_VREF1
PM_BMBUSY#
PM_EXTTS0#
PM_EXTTS1#
PM_THERMTRIP#
PWROK
RSTIN#

K16
K18
J18
F18
E15
F15
E18
D19
D16
G16
E16
D15
G15
K15
C15
H16
G18
H15
J25
K27
J26

Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


Calistoga (1/6)

Size Document Number


Custom HEL80/81 LA-3161P
Date:

Rev
0.2

Thursday, February 23, 2006

Sheet
1

of

43

hexainf@hotmail.com

R28
24.9_0402_1%
2
1

HVREF0
HVREF1
HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP
HXSWING
HYSWING

H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14

PM

J13
+H_VREF K13
H_XRCOMP E1
H_XSCOMP E2
H_YRCOMP Y1
H_YSCOMP U1
+H_SWNG0 E4
+H_SWNG1 W1

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

DDR MUXING

+VCCP

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

DMI

F1
J1
H1
J6
H3
K2
G1
G2
K9
K1
K7
J8
H4
J3
K11
G4
T10
W11
T3
U7
U9
U11
T11
W9
T1
T8
T4
W7
U5
T9
W6
T5
AB7
AA9
W4
W3
Y3
Y7
W5
Y10
AB8
W2
AA4
AA7
AA2
AA6
AA10
Y8
AA1
AB4
AC9
AB11
AC11
AB3
AC2
AD1
AD9
AC1
AD7
AC6
AB5
AD10
AD4
AC8

HOST

R30
54.9_0402_1%
2
1

H_A#[3..31] <4>

U22A
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

NC

H_D#[0..63]

U22

Note : 2005/12/26 modify pn


PM : SA00000KDC0
GM : SA0000059H0
<4>

RESERVED

<13> DDR_A_DQS[0..7]

<13> DDR_A_DQS#[0..7]

<13> DDR_A_MA[0..13]

AU12
AV14
BA20

SA_BS0
SA_BS1
SA_BS2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

AJ33
AM35
AL26
AN22
AM14
AL9
AR3
AH4

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

AK33
AT33
AN28
AM22
AN12
AN8
AP3
AG5

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

AK32
AU33
AN27
AM21
AM12
AL8
AN3
AH5

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

AY16
AU14
AW16
BA16
BA17
AU16
AV17
AU17
AW17
AT16
AU13
AT17
AV20
AV12

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN#
SA_RCVENOUT#

AY13
AW14
AY14
AK23
AK24

SA_CAS#
SA_RAS#
SA_WE#
SA_RCVENIN#
SA_RCVENOUT#

U22E
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

DDR SYS MEMORY A

<13> DDR_A_DM[0..7]

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

<13> DDR_A_CAS#
<13> DDR_A_RAS#
<13> DDR_A_WE#
T6 PAD
T13 PAD

AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D[0..63] <13>
<14> DDR_B_BS#0
<14> DDR_B_BS#1
<14> DDR_B_BS#2
<14> DDR_B_DM[0..7]

<14> DDR_B_DQS[0..7]

<14> DDR_B_DQS#[0..7]

<14> DDR_B_MA[0..13]

<14> DDR_B_CAS#
<14> DDR_B_RAS#
<14> DDR_B_WE#
T5 PAD
T11 PAD

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

AT24
AV23
AY28

SB_BS0
SB_BS1
SB_BS2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

AK36
AR38
AT36
BA31
AL17
AH8
BA5
AN4

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

AM39
AT39
AU35
AR29
AR16
AR10
AR7
AN5

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

AM40
AU39
AT35
AP29
AP16
AT10
AT7
AP5

SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

AY23
AW24
AY24
AR28
AT27
AT28
AU27
AV28
AV27
AW27
AV24
BA27
AY27
AR23

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVENIN#
SB_RCVENOUT#

AR24
AU23
AR27
AK16
AK18

SB_CAS#
SB_RAS#
SB_WE#
SB_RCVENIN#
SB_RCVENOUT#

CALISTOGA_FCBGA1466~D
UMA@

DDR SYS MEMORY B

U22D
<13> DDR_A_BS#0
<13> DDR_A_BS#1
<13> DDR_A_BS#2

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

AK39
AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3

DDR_B_D[0..63] <14>

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

CALISTOGA_FCBGA1466~D
UMA@

Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


Calistoga (2/6)

Size Document Number


Custom HEL80/81 LA-3161P
Date:

Rev
0.2
Sheet

Thursday, February 23, 2006


1

of

43

10 mils
U22C

LVDSA0+
LVDSA1+
LVDSA2+

LVDSA0+
LVDSA1+
LVDSA2+

B37
B34
A36

LA_DATA0
LA_DATA1
LA_DATA2

<16>
<16>
<16>

LVDSA0LVDSA1LVDSA2-

LVDSA0LVDSA1LVDSA2-

C37
B35
A37

LA_DATA#0
LA_DATA#1
LA_DATA#2

<16>
<16>
<16>

LVDSB0+
LVDSB1+
LVDSB2+

LVDSB0+
LVDSB1+
LVDSB2+

F30
D29
F28

LB_DATA0
LB_DATA1
LB_DATA2

<16>
<16>
<16>

LVDSB0LVDSB1LVDSB2-

LVDSB0LVDSB1LVDSB2-

G30
D30
F29

LB_DATA#0
LB_DATA#1
LB_DATA#2

<16>
<16>
<16>
<16>

LVDSAC+
LVDSACLVDSBC+
LVDSBC-

LVDSAC+
LVDSACLVDSBC+
LVDSBC-

A32
A33
E26
E27

LA_CLK
LA_CLK#
LB_CLK
LB_CLK#

<16> GMCH_LVDDEN

R287

2
2

<16>
<16>
<16>

R289
R290
R291

R50
R53

1
1

CRT_R
1
UMA@ 150_0402_1%
CRT_G
1
UMA@ 150_0402_1%
CRT_B
1
UMA@ 150_0402_1%

2
2
2

J20
1
4.99K_0402_1%
B16
B18
B19

3VDDCCL
3VDDCDA

2 UMA@ 39_0402_5%
2 UMA@ 39_0402_5%
<16>
CRT_B
<16>

CRT_G

<16>

CRT_R

2
R49

TVDAC_A
TVDAC_B
TVDAC_C
TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC

J29
K30

TV_DCONSEL1
TV_DCONSEL0

3VDDCCL
3VDDCDA

C26
C25

DDCCLK
DDCDATA

VSYNC
HSYNC
CRT_B

H23
G23
E23
D23
C22
B22
A21
B21

VSYNC
HSYNC
BLUE
BLUE#
GREEN
GREEN#
RED
RED#

J22

CRT_IREF

CRT_G
CRT_R

CRT_IREF
1
255_0402_1%

CRT

CRT_VSYNC
CRT_HSYNC

<16> CRT_VSYNC
<16> CRT_HSYNC

A16
C18
A19

2
R47

<16>
<16>

TV_COMPS
TV_LUMA
TV_CRMA

TV_COMPS
TV_LUMA
TV_CRMA

LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL

TV

R288

TV_COMPS
1
UMA@ 150_0402_1%
TV_LUMA
1
UMA@ 150_0402_1%
TV_CRMA
1
UMA@ 150_0402_1%

D32
J30
H30
H29
EDID_CLK_LCD
G26
EDID_DAT_LCD
G25
GMCH_LVDDEN
F32
2
1
B38
R58
1.5K_0402_1%
C35
C33
C32
GMCH_ENBKL

10 mils

+1.5VS_PCIE
R59
24.9_0402_1%
1
2
PEG_RXP[0..15] <17>

D40
D38

PEGCOMP

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38

PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15

EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38

PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15

EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

C180
C148
C163
C135
C182
C150
C167
C137
C184
C152
C161
C139
C186
C154
C165
C141

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K

PEG_M_TXN0
PEG_M_TXN1
PEG_M_TXN2
PEG_M_TXN3
PEG_M_TXN4
PEG_M_TXN5
PEG_M_TXN6
PEG_M_TXN7
PEG_M_TXN8
PEG_M_TXN9
PEG_M_TXN10
PEG_M_TXN11
PEG_M_TXN12
PEG_M_TXN13
PEG_M_TXN14
PEG_M_TXN15

EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

C179
C147
C162
C134
C149
C181
C166
C136
C183
C160
C151
C138
C185
C153
C140
C164

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K
VGA@ 0.1U_0402_10V7K

PEG_M_TXP0
PEG_M_TXP1
PEG_M_TXP2
PEG_M_TXP3
PEG_M_TXP4
PEG_M_TXP5
PEG_M_TXP6
PEG_M_TXP7
PEG_M_TXP8
PEG_M_TXP9
PEG_M_TXP10
PEG_M_TXP11
PEG_M_TXP12
PEG_M_TXP13
PEG_M_TXP14
PEG_M_TXP15

EXP_COMPI
EXP_COMPO

PCI-EXPRESS GRAPHICS

<16>
<16>
<16>

<16> GMCH_ENBKL

R286

SDVOCTRL_DATA
SDVOCTRL_CLK

LVDS

H27
H28

CALISTOGA_FCBGA1466~D
UMA@

PEG_RXN[0..15] <17>

PEG_M_TXP[0..15] <17>

PEG_M_TXN[0..15] <17>

2/20 modified to 0402_X7R

+3VS

R294

R293
2.2K_0402_5%
UMA@

2.2K_0402_5%
UMA@

<16> EDID_CLK_LCD
A

EDID_DAT_LCD

<16> EDID_DAT_LCD

Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


Calistoga (3/6)

Size Document Number


Custom HEL80/81 LA-3161P
Date:

Rev
0.2

Thursday, February 23, 2006

Sheet
1

of

43

hexainf@hotmail.com

EDID_CLK_LCD

+VCCP

+2.5VS
+2.5VS

10_0402_5%

+1.5VS

VCCA_TVBG
VSSA_TVBG

H20
G20

+3VS_TVBG

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

E19
F19
C20
D20
E20
F20

+3VS_TVDACA

VCCD_HMPLL0
VCCD_HMPLL1

AH1
AH2

+1.5VS

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

A28
B28
C28

VCCD_TVDAC
VCCDQ_TVDAC

D21
H19

VCCHV0
VCCHV1
VCCHV2

A23
B23
B25

2
VCCAUX32
VCCAUX33
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX37
VCCAUX38
VCCAUX39
VCCAUX40

+ C187

+3VS_TVDACB

220U_D2_4VM
2 @

+3VS_TVDACC

+3VS_TVDACC

C98
330U_D2E_2.5VM
2 UMA@

+3VS
L19
MBK1608301YZF_0603
2
1

+3VS_TVDACA
+3VS
L17
MBK1608301YZF_0603
2
1

1
C

+ C389
220U_D2_4VM
2 @

+3VS
L18
MBK1608301YZF_0603
2
1

+1.5VS_TVDAC
+3VS

+3VS_TVBG

2
1

+1.5VS

2
1

+3VS
R285
0_0603_5%
2
1

PCI-E/MEM/PSB PLL decoupling


+1.5VS_3GPLL

2005/10/06

+1.5VS_HPLL

Title

+1.5VS

R292
0_0603_5%
2
1

R21
0_0603_5%
2
1

+1.5VS

2006/10/06

Deciphered Date

45mA Max.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.5VS_TVDAC

R20
0_0603_5%
2
1

Compal Secret Data

Security Classification
Issued Date

+1.5VS

R61
0_0603_5%
2
1

+1.5VS_MPLL

+3VS_TVDACB

CALISTOGA_FCBGA1466~D
UMA@

AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14

C394
330U_D2E_2.5VM
2 UMA@

C43
0.1U_0402_16V4Z

+1.5VS_MPLL

C99
0.1U_0402_16V4Z

AF2

+1.5VS

C42
0.022U_0402_16V7K

VCCA_MPLL

C59
0.1U_0402_16V4Z

+2.5VS

L1
MBK1608301YZF_0603
2
+2.5VS

C51
0.022U_0402_16V7K

A38
B39

C73
0.1U_0402_16V4Z

VCCA_LVDS
VSSA_LVDS

C107
10U_0805_10V4Z

+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL

C103
10U_0805_10V4Z

B26
C39
AF1

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31

AG14
AF14
AE14
Y14
AF13
AE13
AF12
AE12
AD12

VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL

CRTDAC: Route caps within


250mil of Alviso. Route FB
within 3" of Calistoga

L2
MBK1608301YZF_0603
2
1

+1.5VS

C395
10U_0805_10V4Z

+2.5VS_CRTDAC

+1.5VS_DPLLB

L20
MBK1608301YZF_0603
2
1

C35
0.022U_0402_16V7K

C8
0.47U_0603_16V4Z
MCH_AB1

MCH_D2

E21
F21
G21

+1.5VS_DPLLA

C7
10U_0805_10V4Z

1
C15
0.22U_0603_16V7K

C93
0.22U_0603_16V7K

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2

C11
0.1U_0402_16V4Z

+1.5VS_3GPLL
+2.5VS

220U_D2_2VMR15

C65
0.1U_0402_16V4Z

AC33
G41
H41

C130

+1.5VS

C108
0.1U_0402_16V4Z

MCH_A6

close pin G41

C50
0.1U_0402_16V4Z

VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG

C391
0.022U_0402_16V7K

P O W E R

R63
0_0805_5%
2
1

C95
10U_0805_10V4Z

C54
2.2U_0805_10V6K

C390
0.47U_0603_16V4Z

C23
4.7U_0805_10V4Z

12/09 Modified

AB41
AJ41
L41
N41
R41
V41
Y41

C96
0.1U_0402_16V4Z

+1.5VS_PCIE

W=60 mils

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

C10
0.1U_0402_16V4Z

10_0402_5%

+2.5VS

C49
0.1U_0402_16V4Z

1 1

+3VS

R298

B30
C30
A30

C60
0.022U_0402_16V7K

close pin A38

C64
0.1U_0402_16V4Z

220U_D2_2VMR15

D17
RB751V_SOD323

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

1
2
C400
0.1U_0402_16V4Z

C69
0.022U_0402_16V7K

C89

VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT46
VTT47
VTT48
VTT49
VTT50
VTT51
VTT52
VTT53
VTT54
VTT55
VTT56
VTT57
VTT58
VTT59
VTT60
VTT61
VTT62
VTT63
VTT64
VTT65
VTT66
VTT67
VTT68
VTT69
VTT70
VTT71
VTT72
VTT73
VTT74
VTT75
VTT76

H22

C392
10U_0805_10V4Z

+1.5VS

AC14
AB14
W14
V14
T14
R14
P14
N14
M14
L14
AD13
AC13
AB13
AA13
Y13
W13
V13
U13
T13
R13
N13
M13
L13
AB12
AA12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
L12
R11
P11
N11
M11
R10
P10
N10
M10
P9
N9
M9
R8
P8
N8
M8
P7
N7
M7
R6
P6
M6
A6
R5
P5
N5
M5
P4
N4
M4
R3
P3
N3
M3
R2
P2
M2
D2
AB1
R1
P1
N1
M1

VCC_SYNC

C396
0.1U_0402_16V4Z

12/09 Modified

+2.5VS

U22H

+VCCP

C393
0.1U_0402_16V4Z

C6
10U_0805_10V4Z

R299

C97
0.1U_0402_16V4Z

1 1

RB751V_SOD323

C100
0.1U_0402_16V4Z

C398
0.01U_0402_16V7K

+2.5VS

D18

+1.5VS

45mA Max.
1

2
A

Compal Electronics, Inc.


Calistoga (4/6)

Size Document Number


Custom HEL80/81 LA-3161P
Date:

Re v
0.2

Thursday, February 23, 2006

Sheet
1

10

of

43

Strap Pin Table


CFG[3:17] have internal pull up

220U_D2_2VMR15

+
2

1
C77

220U_D2_2VMR15
2
@
B

AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1

CALISTOGA_FCBGA1466~D
UMA@

C13
0.47U_0603_16V4Z

+1.8V
VCC100
VCC101
VCC102
VCC103
VCC104
VCC105
VCC106
VCC107
VCC108
VCC109
VCC110

C12
0.47U_0603_16V4Z

M19
L19
N18
M18
L18
P17
N17
M17
N16
M16
L16

Place near pin AV1 & AJ1

CFG5
CFG7

0 = Reserved
1 = Mobile Yonah CPU*(Default)

CFG9

0 = Lane Reversal Enable


1 = Normal Operation (Default)*

CFG6

0 = Reserved

Place near pin AT41 & AM41

Reserved
XOR Mode Enabled
All Z Mode Enabled
Normal Operation *(Default)

10 = 1.05V*(Default)
01 = 1.5V

CFG10 CFG18

0 = Normal Operation * (Default)


1 = DMI Lane Reversal Enable

CFG19

0 = No SDVO Device Present *


(Default)

SDVO_CTRLDATA

1 = SDVO Device Present

CFG20

Place near pin BA23

=
=
=
=

0 = Dynamic ODT Disabled


1 = Dynamic ODT Enabled *(Default)

CFG16
1

1 = Calistoga
00
01
10
11

CFG[13:12]

= 667MT/s FSB
= 533MT/s FSB

0 = DMI x 2
1 = DMI x 4 *(Default)

PSB 4X CLK Enable

C44
0.1U_0402_16V4Z

VCC_SM100
VCC_SM101
VCC_SM102
VCC_SM103
VCC_SM104
VCC_SM105
VCC_SM106
VCC_SM107

+VCCP

011
001

CFG[2:0]

C88
0.1U_0402_16V4Z

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

MCH_AT41
MCH_AM41
C101
0.47U_0603_16V4Z

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

CFG[19:18] have internal pull down

(PCIE/SDVO select)

0 = Only PCIE or SDVO is


operational. *(Default)
1 = PCIE/SDVO are operating
simu.

1
1

+ C72
220U_D2_4VM
2 @

<7>

CFG5

<7>

CFG7

<7>

CFG9

<7>

CFG10

<7>

CFG11

<7>

CFG12

<7>

CFG13

<7>

CFG16

R36

2 @

2.2K_0402_5%

R44

2 @

2.2K_0402_5%

R40

2 @

2.2K_0402_5%

R41

2 @

2.2K_0402_5%

R39

2 @

2.2K_0402_5%

R37

2 @

2.2K_0402_5%

R42

2 @

2.2K_0402_5%

R35

2 @

2.2K_0402_5%

2
+3VS

<7>
<7>
<7>

Place near pin BA15

CFG18
CFG19
CFG20

R52
R54
R55

1
1
1

2 @ 1K_0402_5%
2 @ 1K_0402_5%
2 @ 1K_0402_5%

CALISTOGA_FCBGA1466~D
UMA@

Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


Calistoga (5/6)

Size Document Number


Custom HEL80/81 LA-3161P
Date:

Rev
0.2

Thursday, February 23, 2006

Sheet
1

11

of

43

hexainf@hotmail.com

1
C18

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6

C102
0.47U_0603_16V4Z

C22
0.22U_0603_16V7K

P O W E R

VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8
VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99

C17
0.1U_0402_16V4Z

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99

C19
0.1U_0402_16V4Z

AA33
W33
P33
N33
L33
J33
AA32
Y32
W32
V32
P32
N32
M32
L32
J32
AA31
W31
V31
T31
R31
P31
N31
M31
AA30
Y30
W30
V30
U30
T30
R30
P30
N30
M30
L30
AA29
Y29
W29
V29
U29
R29
P29
M29
L29
AB28
AA28
Y28
V28
U28
T28
R28
P28
N28
M28
L28
P27
N27
M27
L27
P26
N26
L26
N25
M25
L25
P24
N24
M24
AB23
AA23
Y23
P23
N23
M23
L23
AC22
AB22
Y22
W22
P22
N22
M22
L22
AC21
AA21
W21
N21
M21
L21
AC20
AB20
Y20
W20
P20
N20
M20
L20
AB19
AA19
Y19
N19

C76
10U_0805_10V4Z

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

C25
0.47U_0603_16V4Z

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

+1.8V

U22G

C36
10U_0805_10V4Z

C29
1U_0603_10V4Z

C57
0.22U_0603_16V7K

C94
10U_0805_10V4Z

C45
10U_0805_10V4Z

C47
0.22U_0603_16V7K

VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VCC_NCTF68
VCC_NCTF69
VCC_NCTF70
VCC_NCTF71
VCC_NCTF72

P O W E R

AD27
AC27
AB27
AA27
Y27
W27
V27
U27
T27
R27
AD26
AC26
AB26
AA26
Y26
W26
V26
U26
T26
R26
AD25
AC25
AB25
AA25
Y25
W25
V25
U25
T25
R25
AD24
AC24
AB24
AA24
Y24
W24
V24
U24
T24
R24
AD23
V23
U23
T23
R23
AD22
V22
U22
T22
R22
AD21
V21
U21
T21
R21
AD20
V20
U20
T20
R20
AD19
V19
U19
T19
AD18
AC18
AB18
AA18
Y18
W18
V18
U18
T18

+VCCP

+1.5VS

C91
0.47U_0603_16V4Z

U22F

+VCCP

U22I
AC41
AA41
W41
T41
P41
M41
J41
F41
AV40
AP40
AN40
AK40
AJ40
AH40
AG40
AF40
AE40
B40
AY39
AW39
AV39
AR39
AN39
AJ39
AC39
AB39
AA39
Y39
W39
V39
T39
R39
P39
N39
M39
L39
J39
H39
G39
F39
D39
AT38
AM38
AH38
AG38
AF38
AE38
C38
AK37
AH37
AB37
AA37
Y37
W37
V37
T37
R37
P37
N37
M37
L37
J37
H37
G37
F37
D37
AY36
AW36
AN36
AH36
AG36
AF36
AE36
AC36
C36
B36
BA35
AV35
AR35
AH35
AB35
AA35
Y35
W35
V35
T35
R35
P35
N35
M35
L35
J35
H35
G35
F35
D35
AN34
AK34
AG34
AF34

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99

U22J

P O W E R

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199

AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21

AN21
AL21
AB21
Y21
P21
K21
J21
H21
C21
AW20
AR20
AM20
AA20
K20
B20
A20
AN19
AC19
W19
K19
G19
C19
AH18
P18
H18
D18
A18
AY17
AR17
AP17
AM17
AK17
AV16
AN16
AL16
J16
F16
C16
AN15
AM15
AK15
N15
M15
L15
B15
A15
BA14
AT14
AK14
AD14
AA14
U14
K14
H14
E14
AV13
AR13
AN13
AM13
AL13
AG13
P13
F13
D13
B13
AY12
AC12
K12
H12
E12
AD11
AA11
Y11
J11
D11
B11
AV10
AP10
AL10
AJ10

VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS265
VSS264
VSS263
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279

P O W E R

VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1

CALISTOGA_FCBGA1466~D
UMA@

CALISTOGA_FCBGA1466~D
UMA@

Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


Calistoga (6/6)

Size Document Number


Custom HEL80/81 LA-3161P
Date:

Rev
0.2
Sheet

Thursday, February 23, 2006


1

12

of

43

+1.8V

+1.8V

+1.8V
1

<8> DDR_A_DQS#[0..7]
JP3
DDR_A_D4
DDR_A_D1

1
R87
1K_0402_1%

Layout Note:
Place near JP41

Layout Note:
+DDR_MCH_REF
trace width and
spacing is 20/20.

C171

C158

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D14
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D9
DDR_A_D15

+1.8V

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DDR_A_D16
DDR_A_D17

C81

C41

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C55

0.1U_0402_16V4Z

C85

C26

0.1U_0402_16V4Z

C90

2.2U_0805_10V6K

2.2U_0805_10V6K

C27

2.2U_0805_10V6K

C83

2.2U_0805_10V6K

C84

2.2U_0805_10V6K

DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19

DDR_A_D29
DDR_A_D24
DDR_A_DM3
DDR_A_D26
DDR_A_D27

<7> DDR_CKE0_DIMMA
<8> DDR_A_BS#2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

<8> DDR_A_BS#0
<8> DDR_A_WE#

+0.9VS

<8> DDR_A_CAS#
<7> DDR_CS1_DIMMA#
<7>

DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1

DDR_A_D37
DDR_A_D36

DDR_A_DQS#4
DDR_A_DQS4

C34

C67

C40

C75

C61

C52

C38

C31

C78

C46

C56

C63

C70

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

M_ODT1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_D35
DDR_A_D32
DDR_A_D40
DDR_A_D44

DDR_A_DM5
DDR_A_D41
DDR_A_D46
+0.9VS
RP1
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1

1
2
3
4

RP2
8
7
6
5

56_0804_8P4R_5%

8
7
6
5

1
2
3
4

DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_A_MA13

DDR_A_D49
DDR_A_D48

Layout Note:
Pla ce these resistor
closely JP41,all
trace length Max=1.5"

DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D54
DDR_A_D50

56_0804_8P4R_5%

DDR_A_D61
DDR_A_D60

RP6
DDR_A_BS#0

R43

DDR_A_MA10 R46

56_0402_5%
1
2
1

2
56_0402_5%

5
6
7
8

4
3
2
1

DDR_A_BS#1
DDR_A_MA0
DDR_A_MA2
DDR_A_MA4

DDR_A_DM7
DDR_A_D59
DDR_A_D58

56_0804_8P4R_5%
DDR_A_MA1
DDR_A_MA3
DDR_A_MA5
DDR_A_MA8

4
3
2
1

RP9
5
6
7
8

56_0804_8P4R_5%

5
6
7
8

4
3
2
1

<14,15> CLK_SMBDATA
<14,15> CLK_SMBCLK

DDR_A_MA6
DDR_A_MA7
DDR_A_MA11
DDR_CKE1_DIMMA

+3VS

4
3
2
1

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

DDR_A_D6
DDR_A_D0
DDR_A_DM0
DDR_A_D5
DDR_A_D7

11/9 Modify pn to SP070006V00

5
6
7
8

SO-DIMM A

DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0

M_CLK_DDR0 <7>
M_CLK_DDR#0 <7>

DDR_A_D11
DDR_A_D10

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_D20
DDR_A_D21
PM_EXTTS#0 <7,14>

DDR_A_DM2
DDR_A_D23
DDR_A_D22
DDR_A_D28
DDR_A_D25
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D31
DDR_A_D30
DDR_CKE1_DIMMA

DDR_CKE1_DIMMA <7>

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_A_MA13

DDR_A_BS#1 <8>
DDR_A_RAS# <8>
DDR_CS0_DIMMA# <7>
M_ODT0

<7>

DDR_A_D39
DDR_A_D38
DDR_A_DM4
DDR_A_D34
DDR_A_D33
DDR_A_D45
DDR_A_D43
B

DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D47
DDR_A_D42
DDR_A_D52
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

DDR_A_DM6
DDR_A_D51
DDR_A_D55
DDR_A_D57
DDR_A_D56
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63

R18
10K_0402_5%

R16
10K_0402_5%

Top side
Compal Secret Data

Security Classification

56_0804_8P4R_5%

2005/10/06

Issued Date

2006/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

DDR_A_D13
DDR_A_D12

FOX_ASOA426-M2RN-7F
ME@

56_0804_8P4R_5%

RP10
DDR_A_MA9
DDR_A_MA12
DDR_A_BS#2
DDR_CKE0_DIMMA

CLK_SMBDATA
CLK_SMBCLK

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

RP7

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

0.1U_0402_16V4Z

<14> +DDR_MCH_REF1
<8> DDR_A_MA[0..13]

2.2U_0805_10V6K

+DDR_MCH_REF1

1K_0402_1%

<8> DDR_A_DQS[0..7]

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

Title

Compal Electronics, Inc.


DDRII-SODIMM SLOT1

Size Document Number


Custom HEL80 LA-3161P
Date:

Rev
0.2

Thursday, February 23, 2006

Sheet
1

13

of

43

hexainf@hotmail.com

+DDR_MCH_REF1

R92

<8> DDR_A_D[0..63]
<8> DDR_A_DM[0..7]

+1.8V

<8> DDR_B_DQS#[0..7]

+1.8V

<8> DDR_B_D[0..63]

+DDR_MCH_REF1

<8> DDR_B_DM[0..7]

DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11

+1.8V

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19
DDR_B_D28
DDR_B_D25
DDR_B_DM3
DDR_B_D30
DDR_B_D31

<7> DDR_CKE2_DIMMB

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

<8> DDR_B_BS#2

DDR_CKE2_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

+0.9VS

<8> DDR_B_BS#0
<8> DDR_B_WE#
<8> DDR_B_CAS#
<7> DDR_CS3_DIMMB#

<7>

M_ODT3

DDR_B_CAS#
DDR_CS3_DIMMB#
M_ODT3
DDR_B_D32
DDR_B_D33

2
C33

C37

C62

C82

C48

C58

C80

C53

C39

C32

C74

C79

C68

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43

+0.9VS
RP3
DDR_B_CAS#
DDR_B_WE#
DDR_CS3_DIMMB#
M_ODT3

8
7
6
5

RP4
1
2
3
4

56_0804_8P4R_5%

4
3
2
1

5
6
7
8

DDR_B_MA13
M_ODT2
DDR_CS2_DIMMB#
DDR_B_RAS#

DDR_B_D48
DDR_B_D49

Layout Note:
Pla ce these resistor
closely JP42,all
trace length Max=1.5"

DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D51
DDR_B_D50
DDR_B_D56
DDR_B_D61

56_0804_8P4R_5%
RP5

DDR_B_BS#0
DDR_B_MA10

R48 1
2
56_0402_5%
R45 1

4
3
2
1

5
6
7
8

DDR_B_BS#1
DDR_B_MA0
DDR_B_MA2
DDR_B_MA4

DDR_B_DM7
DDR_B_D59
DDR_B_D58

56_0804_8P4R_5%

5
6
7
8

RP11
4
3
2
1

56_0804_8P4R_5%

4
3
2
1

5
6
7
8

CLK_SMBDATA
CLK_SMBCLK
+3VS

DDR_B_MA7
DDR_B_MA11
DDR_B_MA6
DDR_CKE3_DIMMB

DDR_B_DM1
M_CLK_DDR3
M_CLK_DDR#3

M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>

DDR_B_D14
DDR_B_D15

DDR_B_D21
DDR_B_D16
PM_EXTTS#0 <7,13>

DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D26
DDR_B_D24
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D29
DDR_B_D27

DDR_CKE3_DIMMB

DDR_CKE3_DIMMB <7>

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

DDR_B_BS#1 <8>
DDR_B_RAS# <8>
DDR_CS2_DIMMB# <7>

M_ODT2
DDR_B_MA13

M_ODT2

<7>

DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D39
DDR_B_D38
DDR_B_D44
DDR_B_D45

DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
M_CLK_DDR2
M_CLK_DDR#2

M_CLK_DDR2 <7>
M_CLK_DDR#2 <7>

DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D57
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
R17
1

+3VS

10K_0402_5%
A

R19

SO-DIMM B

56_0804_8P4R_5%

10K_0402_5%

11/9 Modify pn to SP07000BY00

1
2
3
4

Compal Secret Data

Security Classification
2005/10/06

Issued Date

56_0804_8P4R_5%

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1

DDR_B_D12
DDR_B_D13

P-TWO_A5692B-A0G16-P
ME@

RP12
DDR_CKE2_DIMMB 8
DDR_B_BS#2
7
DDR_B_MA12
6
DDR_B_MA8
5

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

DDR_B_D6
DDR_B_D7

RP8
DDR_B_MA1
DDR_B_MA3
DDR_B_MA5
DDR_B_MA9

<13,15> CLK_SMBDATA
<13,15> CLK_SMBCLK

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DDR_B_DM0

DDR_B_D17
DDR_B_D20

C30

C86

0.1U_0402_16V4Z

C71

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C66

0.1U_0402_16V4Z

C20

C92

2.2U_0805_10V6K

2.2U_0805_10V6K

C87

2.2U_0805_10V6K

C21

C28

2.2U_0805_10V6K

2.2U_0805_10V6K

DDR_B_D5
DDR_B_D4

C159

DDR_B_D2
DDR_B_D3

Layout Note:
Place near JP42

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

C172

DDR_B_DQS#0
DDR_B_DQS0
D

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

0.1U_0402_16V4Z

DDR_B_D0
DDR_B_D1

<8> DDR_B_MA[0..13]

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

2.2U_0805_10V6K

<8> DDR_B_DQS[0..7]

+DDR_MCH_REF1 <13>

JP4

2006/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Title

Compal Electronics, Inc.


DDRII-SODIMM SLOT2

Size

Document Number

Rev
0.2

HEL80 LA-3161P
Date:

Sheet

Thursday, February 23, 2006


1

14

of

43

PCI
MHz

133

100

33.3

R479
2.2K_0402_5%

R468
2.2K_0402_5%

Q22
2N7002_SOT23

166

100

33.3
1

<20,27,35> ICH_SMBDATA

2
0_0805_5% 1

Table : ICS954306

533MHz

No Stuff

CLK_Rd CLK_Re CLK_Rf

Stuff

CLK_Rd CLK_Re CLK_Rf

No Stuff

CLK_Ra CLK_Rb CLK_Rc

Stuff

CLK_Rd CLK_Rf

No Stuff

CLK_Ra CLK_Rb CLK_Rc

CLK_Ra

MCH_CLKSEL0 <7>
CLK_48M_ICH R4152
CLK_SD_48M
2
R400

<20> CLK_48M_ICH
<23> CLK_SD_48M

@ 1K_0402_5%

CLK_14M_ICH 2
R461

<20> CLK_14M_ICH

+VCCP

R158

30
36

VDDPCI
VDDPCI

12

VDDCPU

CPU_BSEL1

R157
1K_0402_5%

CLK_Rb

20

X1

CLK_XTAL_OUT

19

X2

41

USB_48MHz/FSLA

45

FSLB/TEST_MODE/24Mhz

CLKREF1
1
33_0402_5%

23

10

CPUCLKT0LP

14

CPUCLKC0LP

13

70

SEL_24M/PCICLK2

SRCCLKC8LP

69

<30> CLK_PCI_DB

33_0402_5% 2

1 R453

27

SEL_PCI6/PCICLK1

CLKREQ8#

71

33_0402_5% 2

1 R464

SRCCLKT7LP

66

22

SEL_PCI5/REF1
SRCCLKC7LP

67

43

DOTT_96MHz/27MHz_Nonspread
CLKREQ7#/48Mhz_1

38

44

DOTC_96MHz/27MHz_spread

63

37

ITP_EN/PCICLK_F0

CLK_MCH_DREFCLK

MCH_DREFCLK
2
UMA@ 0_0402_5%
MCH_DREFCLK#
2
UMA@ 0_0402_5%

1
R409
CLK_MCH_DREFCLK# 1
R408

CLK_PCI_ICH
2
33_0402_5%

1 PCI_ICH
R423
CLK_ENABLE#

2 10K_0402_5%

<13,14> CLK_SMBCLK

<13,14> CLK_SMBDATA

SRCCLKT6LP
SRCCLKC6LP

64

CLKREQ6#

62

SRCCLKT5LP

60

PCIE_LAN

61

PCIE_LAN#

GND

SRCCLKT3LP

55

GNDSRC

SRCCLKC3LP

56

15

GNDCPU

CLKREQ3#/PCICLK5

28

21

GNDREF

SRCCLKT2LP

52

PCIE_MCARD1

31

GNDPCI

SRCCLKC2LP

53

16

SMBCLK

CLKREQ5#/PCICLK6

29

SRCCLKT4LP

58

CLK_SMBDATA

17

SMBDAT

SRCCLKC4LP

59

CLKREQ4#

57

CLKIREF

PCI6

R419

R418

@ 10K_0402_5%

R438

35

GNDPCI

CLKREQ2#

26

42

GND48

SRCCLKT1LP

50

68

GNDSRC

SRCCLKC1LP

51

CLKREQ1#

46

LCD100/96/SRC0_TLP

47

LCD100/96/SRC0_CLP

48

R454

@ 10K_0402_5%
2

@ 10K_0402_5%

PCI_SIO

PCI_DB

R455

@ 10K_0402_5%

PCI_ICH

PCI5

R429

10K_0402_5%

+3VS

+3VS

73
74
75
76

@ 10K_0402_5%
2

CLK_Rf

C302
0.1U_0402_16V4Z

C301
0.1U_0402_16V4Z

C499 2

THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD

1 33P_0402_50V8J

Y5
14.31818MHz_20P_1BX14318BE1A

CLK_XTAL_IN

C503 2

1 33P_0402_50V8J

+3VS

C313
10U_0805_10V4Z

Place crystal within


500 mils of CK410

Place near U4
Place these components
near each pin within 40
mils.

H_STP_CPU# <20>

CLK_MCH_3GPLL
2
0_0402_5%
CLK_MCH_3GPLL#
2
0_0402_5%
MCH_CLKREQ#
1
0_0402_5%
CLK_PCIE_SATA
2
0_0402_5%
CLK_PCIE_SATA#
2
0_0402_5%

1
R472
MCH_3GPLL# 1
R470
CLKREQ8#
2
R214
PCIE_SATA
1
R462
PCIE_SATA# 1
R467
SATAREQ#

SRCCLKC5LP
CLK_SMBCLK

2 R483

MCH_3GPLL

VTT_PWRGD#/PD

2.2_0603_5%
2

CLK_PCIE_VGA
2
VGA@ 0_0402_5%
CLK_PCIE_VGA#
2
VGA@ 0_0402_5%

1
R473
1
R474

1
R451
1
R458
CLKREQ_LAN# 2
R447
PCIE_ICH
1
R434
PCIE_ICH#
1
R441
CLKREQ_ICH# 2
R170
PCIE_NC1
1
R422
PCIE_NC1#
1
R427
CLKREQ_NC#

39

ITP

2 +CK_VDD_48
2.2_0603_5%

CLK_CPU_BCLK
2
0_0402_5%
CLK_CPU_BCLK#
2
0_0402_5%

PCIE_VGA#

32

0_0402_5%

@ 1K_0402_5%

H_STP_PCI# <20>

1
R478
CPU_BCLK# 1
R477

PCIE_VGA

PCI_PCM

+3VS

1
R482

CPU_BCLK

2
72

+3VS

R439

0.1U_0402_16V4Z

2 +CK_VDD_REF
1_0603_5%

CLK_MCH_BCLK
2
0_0402_5%
CLK_MCH_BCLK#
2
0_0402_5%

SRCCLKC9LP
CLKREQ9#

CLK_Rc

C278

CLK_MCH_BCLK <7>
CLK_MCH_BCLK# <7>
CLK_CPU_BCLK <4>
CLK_CPU_BCLK# <4>

CLK_CPU_BCLK

2
R487
CLK_CPU_BCLK# 2
R486

1
@ 49.9_0402_1%
1
@ 49.9_0402_1%

CLK_MCH_BCLK

2
R485
CLK_MCH_BCLK# 2
R484

1
@ 49.9_0402_1%
1
@ 49.9_0402_1%

CLK_MCH_SSCDREFCLK
1
R406
CLK_MCH_SSCDREFCLK#
1
R405
CLK_MCH_3GPLL
1
R471
CLK_MCH_3GPLL#
1
R469
CLK_PCIE_VGA
1
R480
CLK_PCIE_VGA#
1
R481
CLK_PCIE_ICH
1
R433
CLK_PCIE_ICH#
1
R442
CLK_MCH_DREFCLK 1
R402
CLK_MCH_DREFCLK#1
R401
CLK_PCIE_SATA 1
R463
CLK_PCIE_SATA# 1
R466
CLK_PCIE_NC1
2
R421
CLK_PCIE_NC1# 2
R428
CLK_PCIE_LAN
2
R450
CLK_PCIE_LAN# 2
R457
CLK_PCIE_MCARD1 1
R404
CLK_PCIE_MCARD1# 1
R403

2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
1
@ 49.9_0402_1%
1
@ 49.9_0402_1%
1
@ 49.9_0402_1%
1
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%

SRCCLKT8LP

MCH_CLKSEL2 <7>

1
R397

1
R476
MCH_BCLK# 1
R475

SEL_48M/PCICLK3

2
G
Q5
S
2N7002_SOT23

0.1U_0402_16V4Z

MCH_BCLK

SRCCLKT9LP

PCICLK4/FCTSEL1

C494

33

R456
1K_0402_5%

CPUCLKC1LP

34

1
2
1
R449
0_0402_5%

11

PCI_LPC

R410 1

<20,31,42> VGATE

CPUCLKT1LP

PCI_1394

PCI_SIO

0.1U_0402_16V4Z

H_STP_CPU#

1 R435
1 R437
1 R445

PCI_DB

C304

24

REF0/FSLC/TEST_SEL

CPU_BSEL2

0.1U_0402_16V4Z

CPU_STOP#

<5>

H_STP_PCI#

1 R431

<18> CLK_PCI_ICH

C506

25

CPUCLKC2_ITP/SRCCLKC10LP

<42> CLK_ENABLE#

R448
@ 1K_0402_5%
8.2K_0402_5%
CLKREF1 2
1
1
2

0.1U_0402_16V4Z

PCI_SRC_STOP#

12_0402_5% 2
12_0402_5% 2
33_0402_5% 2

@ 1K_0402_5%

R430

33_0402_5% 2

<7> CLK_MCH_DREFCLK

+3VS

CPUCLKT2_ITP/SRCCLKT10LP

MCH_CLKSEL1 <7>

CLK_Re

VDDA
GNDA

<31> CLK_PCI_LPC
<35> CLK_PCI_TPM
<23> CLK_PCI_PCM

<7> CLK_MCH_DREFCLK#

+VCCP

0.1U_0402_16V4Z

VDD48

R156

C507

<25> CLK_PCI_1394

<30> CLK_14M_SIO

1
R154
0_0402_5%

<5>

VDDREF

@ 1K_0402_5%
1

10U_0805_10V4Z

VDDSRC
VDDSRC
VDDSRC
VDDSRC

CLK_XTAL_IN

1 12_0402_5%
FSA
1
12_0402_5%
FSB

R394

FSB

C490

+CK_VDD_REF 18
2
0.1U_0402_16V4Z
+CK_VDD_48 40
2
0.1U_0402_16V4Z

1
C505
1
C492

R395
1K_0402_5%

C264

R220
1

1
R393
0_0402_5%

U30

1
49
54
65

CPU_BSEL0

R407
CLK_Rd
8.2K_0402_5%
1
1
2

0.1U_0402_16V4Z

CLK_XTAL_OUT

R398
@ 56_0402_5%
FSA 2

C263

Q21
2N7002_SOT23

+VCCP

<5>

CLK_SMBCLK

CLK_Re

2
0_0805_5% 1

2
G
1

+CK_VDD_MAIN1

667MHz

1
R399

+3VS

<20,27,35> ICH_SMBCLK

*(Default)

+3VS

CLK_Ra CLK_Rb CLK_Rc

Stuff

CPU Driven

10U_0805_10V4Z

+CK_VDD_MAIN2

2
G

FSB Frequency Selet:

C285

CLK_SMBDATA

1
R208

+3VS

CLK_PCIE_VGA <17>
CLK_PCIE_VGA# <17>

CLK_MCH_3GPLL <7>
CLK_MCH_3GPLL# <7>
MCH_CLKREQ# <7>
CLK_PCIE_SATA <19>
CLK_PCIE_SATA# <19>
SATAREQ# <20>

2 CLK_PCIE_LAN
0_0402_5%
2 CLK_PCIE_LAN#
0_0402_5%
1
10K_0402_5%
2 CLK_PCIE_ICH
0_0402_5%
2 CLK_PCIE_ICH#
0_0402_5%
1
10K_0402_5%
2 CLK_PCIE_NC1
0_0402_5%
2 CLK_PCIE_NC1#
0_0402_5%
2 CLK_PCIE_MCARD1
0_0402_5%
2 CLK_PCIE_MCARD1#
0_0402_5%

CLK_PCIE_LAN <26>
CLK_PCIE_LAN# <26>

CLK_PCIE_ICH <20>
CLK_PCIE_ICH# <20>

CLK_PCIE_NC1 <35>
CLK_PCIE_NC1# <35>
CLKREQ_NC# <35>

1
R412
PCIE_MCARD1# 1
R411
CLKREQ_MCARD1#

CLK_PCIE_MCARD1 <27>
+3VS

CLK_PCIE_MCARD1# <27>
CLKREQ8#

2
R213
SATAREQ#
2
R417
CLKREQ_NC#
2
R189
CLKREQ_MCARD1# 2
R193

CLKREQ_MCARD1# <27>

SSCDREFCLK

2 CLK_MCH_SSCDREFCLK
UMA@ 0_0402_5%
2 CLK_MCH_SSCDREFCLK#
UMA@ 0_0402_5%

1
R414
SSCDREFCLK# 1
R413

1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%

CLK_MCH_SSCDREFCLK <7>
CLK_MCH_SSCDREFCLK# <7>
A

R425

FCTSEL1
(PIN34)

PIN43

PCI_DB=SEL_PCI6
PIN44

PIN47

PIN48

PCI_1394

@ 10K_0402_5%

PCI_1394 = FCTSEL1

R424

DOT96T

DOT96C

96/100M_T 96/100M_C

10K_0402_5%

1
5

27Mout

27MSSout

SRCT0

PCI_DB

PIN27

CLKREQ5

PCICLK6

ICS9LPR325AKLFT_MLF72

ICS9LPR325CKLFT_MLF72: SA00000RE20
SLG8LP465VTR: SA00000TS00

2005/03/10

Issued Date

2005/11/8 modify footprint to ICS954305DKLFT_MLF72 for Thermal Pad use

Compal Secret Data

Security Classification

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SRCC0
4

Title

Compal Electronics, Inc.


Clock generator

Size

Document Number

Rev
0.2

HEL80 LA-3161P
Date:

Sheet

Thursday, February 23, 2006


1

15

of

43

hexainf@hotmail.com

SRC
MHz

CPU
MHz

CLKSEL0

FSLA

FSLB
CLKSEL1

+CK_VDD_MAIN1

FSLC
CLKSEL2

+3VS

TV-OUT Conn.

UMA LCD / PANEL Conn.

VGA I/O PORT Conn.

JP42
JP6
R65

<17> CARD_LUMA

R64

<17> CARD_CRMA

LUMA

2 VGA@ 1 0_0402_5%
2 VGA@ 1 0_0402_5%

VGA_DDC_DAT
VGA_DDC_CLK
JVGA_HS
JVGA_VS

CRMA

RED

R302 2 UMA@ 1 0_0402_5%

TV_CRMA

COMP

2 R11
1
150_0402_1%

<9>

R301 2 UMA@ 1 0_0402_5%

TV_LUMA

R9
2
1
150_0402_1%

<9>

2 VGA@ 1 0_0402_5%
2 R10
1
150_0402_1%

R66

<17> CARD_COMP

GREEN
BLUE

1
3
5
7
9
11
13
15
17
19

1
3
5
7
9
11
13
15
17
19

2
4
6
8
10
12
14
16
18
20

2
4
6
8
10
12
14
16
18
20

21

G1

G2

22

LUMA
COMP
+3VS
+5VS
+LCDVDD

ACES_87216-2016

LVDSA0LVDSA0+

LVDSA0LVDSA0+

<9>
<9>

LVDSA1LVDSA1+

<9>
<9>

LVDSA2LVDSA2+

<9>
<9>

LVDSACLVDSAC+

2
L37
UMA@

R300 2 UMA@ 1 0_0402_5%

<9> TV_COMPS

<9>
<9>

CRMA

LVDSA1LVDSA1+
LVDSA2LVDSA2+
LVDSACLVDSAC+

1
KC FBM-L11-201209-221LMAT_0805

(60 MIL)

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

31
32

GND1
GND2

Pop when with internal graphics

LVDSB0LVDSB0+

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

LVDSB0- <9>
LVDSB0+ <9>

LVDSB1LVDSB1+

LVDSB1- <9>
LVDSB1+ <9>
1

LVDSB2LVDSB2+

LVDSB2- <9>
LVDSB2+ <9>

LVDSBCLVDSBC+

LVDSBC- <9>
LVDSBC+ <9>

EDID_DAT_LCD
EDID_CLK_LCD

EDID_DAT_LCD <9>
EDID_CLK_LCD <9>
+3VS

ACES_88242-3001

+5VALW
2

CRT Conn.

2
FCM1608C-121T_0603

RED

2
FCM1608C-121T_0603

GREEN

2
FCM1608C-121T_0603

BLUE

C539

C538

C537

C1
@

8P_0402_50V8K

8P_0402_50V8K

C2

2 UMA@ 1 0_0402_5%

C3

R77

8P_0402_50V8K

CRT_B

2 UMA@ 1 0_0402_5%

8P_0402_50V8K

<9>

R75

8P_0402_50V8K

CRT_G

2 UMA@ 1 0_0402_5%

8P_0402_50V8K

<9>

R73

R4
2
1
150_0402_1%

CRT_R

L41
R3
2
1
150_0402_1%

<9>

2 VGA@ 1 0_0402_5%
R2
2
1
150_0402_1%

R78

100K_0402_5%
UMA@

0.047U_0402_16V7K 0.1U_0402_16V4Z
UMA@ 2
UMA@ 2

Q14
2N7002_SOT23
UMA@

R282
2
UMA@

<9> GMCH_LVDDEN

2
G

2
G
S

<17> CARD_VGA_B

L40

2 VGA@ 1 0_0402_5%

1 2

L39

R76

<17> CARD_VGA_G

2 VGA@ 1 0_0402_5%

R281

300_0402_5%
UMA@
R74

<17> CARD_VGA_R

+3VS
Q13
UMA@
SI2301BDS_SOT23

+LCDVDD

R278

2/09 Add for Compliance Engineering request

+LCDVDD
1

Reverse pin 1 to 29

C383

1
2
0_0402_5% G

C381

C382

C384
UMA@

4.7U_0805_10V4Z
2 UMA@
2

Q15
2N7002_SOT23
UMA@

4.7U_0805_10V4Z

Pop when with internal graphics

INVERTER Conn.
D12
RB751V_SOD323
1
2

+3VS +3VS

JP40

+3VS

R13

2 VGA@ 1 0_0402_5%

VSYNC_R

R85

2 UMA@ 0_0402_5%

R84

2 UMA@ 0_0402_5%

2
2

R12

JVGA_HS
2
39_0402_5%

ENBKL

<31>

ENBKL
R284

SN74AHCT1G125DCKR_SC70-5

INVPWR_B+
C387
0.1U_0603_50V4Z
L16
1
2
KC FBM-L11-201209-221LMAT_0805
L15
1
2
2
1
C388
@ KC FBM-L11-201209-221LMAT_0805
68P_0402_50V8K

U2
Y

R15

JVGA_VS
2
39_0402_5%

SN74AHCT1G125DCKR_SC70-5

Compal Secret Data


2005/10/06

Issued Date

2006/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

DISPOFF#

100K_0402_5%
4

Security Classification

1
UMA@ 0_0402_5%
1
VGA@ 0_0402_5%

B+

0.1U_0402_16V4Z

Pop when with internal graphics

R94

U1
Y

C4
5

+5VS

R57

<17> G7X_ENBKL

<9> CRT_VSYNC
4

0.1U_0402_16V4Z

BKOFF#

<9> GMCH_ENBKL

<9> CRT_HSYNC

<31>

D13
RB751V_SOD323
1
2

R90

1
2
10K_0402_5% R1

OE#

<17> CARD_VSYNC

R283

C5

P
HSYNC_R

VGA_DDC_CLK

4.7K_0402_5%

2 VGA@ 1 0_0402_5%

Q2
2N7002_SOT23

R91

+5VS

<17> CARD_HSYNC

OE#

1 UMA@ 2 0_0402_5%
1 UMA@ 2 0_0402_5%

3VDDCDA
3VDDCCL

2 VGA@ 1 0_0402_5%

R83
R86

MOLEX_53780-0790

VGA_DDC_DAT
+3VS

<9>
<9>

R88

DISPOFF#

Q1
2N7002_SOT23
<17> CARD_DDCCLK

DAC_BRIG
INVPWR_B+

INVT_PWM

<31>

4.7K_0402_5%
2

2 VGA@ 1 0_0402_5%

R89

<31>

R279

4.7K_0402_5%

<17> CARD_DDCDATA

R280

4.7K_0402_5%

R14

+3VS

4.7K_0402_5%

1
2
3
4
5
6
7

+5VS

Title

Compal Electronics, Inc.


CRT & TVout Connector

Size Document Number


Custom HEL80 LA-3161P
Date:

Rev
0.2
Sheet

Thursday, February 23, 2006


E

16

of

43

MAX. 4.06A @ 1.8V


MAX. 130mA @ 2.5V
MAX. 655mA @ 3.3V
PEG_M_TXP[0..15]

PEG_M_TXP[0..15] <9>

PEG_M_TXN[0..15]

PEG_M_TXN[0..15] <9>

PEG_RXP[0..15]

PEG_M_TXP8
PEG_M_TXN8

PEG_RXP11
PEG_RXN11

PEG_M_TXP10
PEG_M_TXN10

PEG_RXP13
PEG_RXN13

PEG_M_TXP12
PEG_M_TXN12

PEG_RXP15
PEG_RXN15

PEG_M_TXP14
PEG_M_TXN14
+1.8VS

+5VS

<15> CLK_PCIE_VGA
<15> CLK_PCIE_VGA#
<16> CARD_DDCCLK
<16> CARD_DDCDATA
<16> CARD_VSYNC

2
L3

<16> CARD_HSYNC
B+

VGA@ KC FBM-L11-201209-221LMAT_0805

<16> CARD_VGA_R
<16> CARD_VGA_G
<16> CARD_VGA_B

PEG_RXP2
PEG_RXN2
PEG_RXP4
PEG_RXN4
PEG_RXP6
PEG_RXN6
C

PEG_RXP8
PEG_RXN8
+5VS

PEG_RXP10
PEG_RXN10
PEG_RXP12
PEG_RXN12
PEG_RXP14
PEG_RXN14
SUSP#
G7X_THER_ALERT#

PLT_RST#

SUSP#
<31,32,33,35,40,41>
G7X_THER_ALERT# <20>

VGA@

+2.5VS

VGA@

VGA@

VGA@

G7X_ENBKL <16>
PLT_RST# <7,18,20,22,26,27,31,35>

+3VS

CARD_COMP <16>
CARD_LUMA <16>
CARD_CRMA <16>

ACES_88363-08001
C142

ACES_88363-08001

PEG_RXN[0..15] <9>

C133

PEG_M_TXP6
PEG_M_TXN6

PEG_RXP9
PEG_RXN9

PEG_RXN[0..15]
PEG_RXP0
PEG_RXN0

VGA@

2
VGA@

Compal Secret Data

Security Classification
Issued Date

2005/10/06

2006/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


VGA/B connector

Size

Document Number

Rev
0.2

HEL80 LA-3161P
Date:

Sheet

Thursday, February 23, 2006


1

17

of

43

hexainf@hotmail.com

+2.5VS

PEG_RXP7
PEG_RXN7

41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

0.1U_0402_16V4Z

+3VS

PEG_M_TXP4
PEG_M_TXN4

41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

0.1U_0402_16V4Z

+1.5VS

PEG_M_TXP2
PEG_M_TXN2

PEG_RXP5
PEG_RXN5

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

0.047U_0402_16V4Z

PEG_M_TXP15
PEG_M_TXN15

PEG_RXP3
PEG_RXN3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

C132

PEG_M_TXP13
PEG_M_TXN13

PEG_M_TXP0
PEG_M_TXN0

C143

PEG_M_TXP11
PEG_M_TXN11

PEG_RXP1
PEG_RXN1

C157

PEG_M_TXP9
PEG_M_TXN9

41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

0.1U_0402_16V4Z

PEG_M_TXP7
PEG_M_TXN7
C

PEG_RXP[0..15] <9>

JP8
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

0.047U_0402_16V4Z

PEG_M_TXP5
PEG_M_TXN5

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

0.1U_0402_16V4Z

PEG_M_TXP3
PEG_M_TXN3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

C156

JP7
PEG_M_TXP1
PEG_M_TXN1

+3VS

2 8.2K_0402_5%

PCI_PLOCK#

R361 1

2 8.2K_0402_5%

PCI _IRDY#

R347 1

2 8.2K_0402_5%

PCI_SERR#

R350 1

2 8.2K_0402_5%

PCI_PERR#

R345 1

2 8.2K_0402_5%

PCI_REQ4#

R344 1

2 8.2K_0402_5%

PCI_REQ3#

U4B

<23,25,30> PCI_AD[0..31]

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

+3VS

R375 1

2 8.2K_0402_5%

PCI_PIRQA#

R377 1

2 8.2K_0402_5%

PCI_PIRQB#

R371 1

2 8.2K_0402_5%

PCI_PIRQC#

R366 1

2 8.2K_0402_5%

PCI_PIRQD#

R357 1

2 8.2K_0402_5%

PCI_PIRQE#

R367 1

2 8.2K_0402_5%

PCI_PIRQF#

R352 1

2 8.2K_0402_5%

PCI_PIRQG#

R360 1

2 8.2K_0402_5%

PCI_PIRQH#

R362 1

2 8.2K_0402_5%

PCI_REQ0#

R340 1

2 8.2K_0402_5%

PCI_REQ1#

R335 1

2 8.2K_0402_5%

PCI_REQ2#

R358 1

2 8.2K_0402_5%

PCI_REQ5#

<23> PCI_PIRQA#
<23> PCI_PIRQB#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

E18
C18
A16
F18
E16
A18
E17
A17
A15
C14
E14
D14
B12
C13
G15
G13
E12
C11
D11
A11
A10
F11
F10
E9
D9
B9
A8
A6
C7
B6
E6
D6

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#
REQ4# / GPIO22
GNT4# / GPIO48
GPIO1 / REQ5#
GPIO17 / GNT5#

D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#

PCI_REQ0# <25>
PCI_GNT0# <25>

PCI_REQ2#
PCI_GNT2#
PCI_REQ3#

PCI_REQ2# <23>
PCI_GNT2# <23>

C/BE0#
C/BE1#
C/BE2#
C/BE3#

B15
C12
D12
C15

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#

A7
E10
B18
A12
C9
E11
B10
F15
F14
F16

PCI _IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PLTRST#
PCICLK
PME#

C26
A9
B19

PCI_PLTRST#
CLK_PCI_ICH
PCI_PME#

G8
F7
F8
G7

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI

Interrupt

A3
B4
C5
B5

PIRQA#
PIRQB#
PIRQC#
PIRQD#

AE5
AD5
AG4
AH4
AD9

RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]

I/F

GPIO2 / PIRQE#
GPIO3 / PIRQF#
GPIO4 / PIRQG#
GPIO5 / PIRQH#

MISC
RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]
MCH_SYNC#

PCI_REQ4#

+3VS

PCI_REQ5#
5

PCI_FRAME#

R346 1

AE9
AG8
AH8
F21
AH20

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PCI_PCIRST#

<23,25,30>
<23,25,30>
<23,25,30>
<23,25,30>

2 8.2K_0402_5%

PCI_RST#
4
Y U27
@
NC7SZ08P5X_NL_SC70-5

PCI_TRDY#

R337 1

2 8.2K_0402_5%

PCI_IRDY# <23,25>
PCI_PAR <23,25>

PCI_RST# <23,25,30>

2
R332

PCI_DEVSEL# <23,25>
PCI_PERR# <23,25>

1
0_0402_5%
+3VS

PCI_SERR# <23>
PCI_STOP# <23,25>
PCI_TRDY# <23,25,30>
PCI_FRAME# <23,25,30>

PCI_STOP#

R342 1

PCI_PLTRST#

PCI_DEVSEL#

2 8.2K_0402_5%

2 8.2K_0402_5%

R341 1

CLK_PCI_ICH <15>
PCI_PME# <31>

4
Y U26

2
R311

PCI_PIRQE# <25>

PLT_RST#

PLT_RST# <7,17,20,22,26,27,31,35>

NC7SZ08P5X_NL_SC70-5
@

R343 1

1
0_0402_5%

MCH_ICH_SYNC# <7>

Place closely pin A9

ICH7_BGA652~D

CLK_PCI_ICH
B

R351
10_0402_5%
@

C460
10P_0402_50V8K
@

Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


ICH7-M(1/4)

Size

Document Number

Rev
0.2

HEL80 LA-3161P
Date:

Sheet

Thursday, February 23, 2006


1

18

of

43

C215
18P_0402_50V8J
2
1

OUT

ICH_RTCRST#
1 R373
1 R364

+RTCVCC
2

J1

2 332K_0402_1%
1M_0402_5%
2

1
@ JOPEN

INTVRMEN
INTRUDER#

<27> ICH_RST_MDC#

39_0402_5% 1 R388

39_0402_5% 1 R389

<27> ICH_SDOUT_MDC

<22> PSATA_IRX_DTX_N0_C
<22> PSATA_IRX_DTX_P0_C

PD _IORDY
PD_IRQ
SATA_LED#

R339 1
R338 1
R334 1

<22>
<22>
<22>
<22>
<22>

AE22
AH28

GATEA20
H_A20M#

2
2

FERR#

AG26

H_FERR#

GPIO49 / CPUPWRGD

AG24

H_PW RGOOD

IGNNE#
INIT3_3V#
INIT#
INTR

AG22
AG21
AF22
AF25

H_IGNNE#

LAN_TXD0
LAN_TXD1
LAN_TXD2

ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2

T4

ACZ_SDOUT

AF18

SATALED#

PSATA_IRX_DTX_N0_C
PSATA_IRX_DTX_P0_C
PSATA_ITX_DRX_N0_C
PSATA_ITX_DRX_P0_C

AF3
AE3
AG2
AH2

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

PSATA_IRX_DTX_N2_C
PSATA_IRX_DTX_P2_C

AF7
AE7
AG6
AH6

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

AF1
AE1

SATA_CLKN
SATA_CLKP

AH10
AG10

SATARBIASN
SATARBIASP

AG16
AH16
AF16
AH15
AF15

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

@ 56_0402_5%

+3VS
GATEA20 <31>
H_A20M# <4>

1 R310 0_0402_5%

H_CPUSLP# <4,7>

1 R319 0_0402_5%
R313 1
56_0402_5%

H_DPRSTP# <4,42>
H_DPSLP# <4>

+VCCP
H_FERR# <4>
H_PWRGOOD <4>
H_IGNNE# <4>

H_INIT#
H_INTR

RCIN#

AG23

KB_RST#

SMI#
NMI

AF23
AH24

H_SMI#
H_NMI

STPCLK#

AH22

H_STPCLK#

THERMTRIP#

AF26

THRMTRIP_ICH#

DA0
DA1
DA2

AH17
AE17
AF17

PD_A0
PD_A1
PD_A2

DCS1#
DCS3#

AE16
AD16

PD_CS#1
PD_CS#3

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15

AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15

PD_D0
PD_D1
PD_D2
PD_D3
PD_D4
PD_D5
PD_D6
PD_D7
PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15

DDREQ

AE15

PD_DREQ

IDE

R328 1
10K_0402_5%

@ 56_0402_5%
R125
H_DPRSTP# 1
2

LPC_FRAME# <30,31,35>

DPRSLP#
H_DPSLP#

U7
V6
V7

ACZ_RST#

PD _IORDY
PD_IRQ
PD_DACK#
PD_IOW#
PD_IOR#

A20GATE
A20M#

LPC_DRQ#0 <30>

H_CPUSLP_R#

LAN_RXD0
LAN_RXD1
LAN_RXD2

T2
T3
T1

PD_IORDY
PD_IRQ
PD_DACK#
PD_IOW#
PD_IOR#

LPC_FRAME#

SATA

2
2
2

AB3

AF24
AH25

U5
V4
T5

R5

1 R348
2
24.9_0402_1%

+3VS

LFRAME#

AG27

LAN_RSTSYNC

ICH_AC_RST_R#

CLK_PCIE_SATA#
CLK_PCIE_SATA

<15> CLK_PCIE_SATA#
<15> CLK_PCIE_SATA

LPC_DRQ#0

H_DPSLP# 1

CPUSLP#

LAN_CLK

ACZ_BCLK
ACZ_SYNC

ICH_AC_SDOUT_R

AC3
AA5

+VCCP
R124

TP1 / DPRSTP#
TP2 / DPSLP#

V3
U3

U1
R6

SATA_LED#

<34> SATA_LED#

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

ICH_AC_BITCLK_R
ICH_AC_SYNC_R

ICH_AC_SDIN0
ICH_AC_SDIN1

<28> ICH_AC_SDIN0
<27> ICH_AC_SDIN1

LDRQ0#
LDRQ1# / GPIO23

AC-97/AZALIA

2
2

AA6
AB5
AC4
Y6

LAN

<27> ICH_BITCLK_MDC
<27> ICH_SYNC_MDC

39_0402_5% 1 R385
39_0402_5% 1 R354

4.7K_0402_5%
8.2K_0402_5%
10K_0402_5%

W4
Y5

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LAD0
LAD1
LAD2
LAD3

RTCRST#

W1
Y1
Y2
W3

C484
1U_0603_10V4Z
1
2

RTXC1
RTCX2

AA3

ICH_INTVRMEN
SM_INTRUDER#

LPC_AD[0..3] <30,31,35>

RTC

ICH_RTCX2

1
2
R369
20K_0402_5%

+RTCVCC

U4A
AB1
AB2

H_INIT#
H_INTR
2 R325
1
10K_0402_5%

<4>
<4>
+VCCP

+3VS
KB_RST# <31>

IN

NC

LPC

NC

H_SMI#
H_NMI

<4>
<4>

R324
56_0402_5%

H_STPCLK# <4>
2

R139
10M_0402_5%
2
1

C214
18P_0402_50V8J
2
1

ICH_RTCX1

Y2
32.768KHZ_12.5P_1TJS125BJ2A251

CPU

1 R312
2
24.9_0402_1%
PD_A0
PD_A1
PD_A2

H_THERMTRIP# <4,7>

<22>
<22>
<22>

PD_CS#1 <22>
PD_CS#3 <22>

PD_D[0..15]

PD_D[0..15] <22>

PD_DREQ <22>

ICH7_BGA652~D

<22> PSATA_ITX_DRX_P0

PSATA_ITX_DRX_N0

1
C479

PSATA_ITX_DRX_N0_C
2
3900P_0402_50V7K

PSATA_ITX_DRX_P0

1
C480

PSATA_ITX_DRX_P0_C
2
3900P_0402_50V7K

Close to U7

D2

12/12 Added
<28> ICH_SDOUT_AUDIO

1
R376

2 ICH_AC_SDOUT_R
39_0402_5%

<28> ICH_SYNC_AUDIO

1
R353

2 ICH_AC_SYNC_R
39_0402_5%

1
R531
1
R532

+CHGRTC

<28> ICH_RST_AUDIO#

<28> ICH_BITCLK_AUDIO

1
R387

2 ICH_AC_RST_R#
39_0402_5%

1
R386

2 ICH_AC_BITCLK_R
39_0402_5%

BATT1

+RTCVCC
C240 2

ML1220T13RE
45@

BAS40-04_SOT23

SATA_RXn/p need tie to ground when SATA port no used

2005/10/06

Issued Date

Compal Secret Data

Security Classification

2006/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

BATT1.1
W=20mils

PSATA_IRX_DTX_N2_C
2
1K_0402_5%
PSATA_IRX_DTX_P2_C
2
1K_0402_5%

0.1U_0402_16V4Z
A

Title

Compal Electronics, Inc.


ICH7-M(2/4)

Size Document Number


Custom HEL80 LA-3161P
Date:

Rev
0.2

Thursday, February 23, 2006

Sheet
1

19

of

43

hexainf@hotmail.com

<22> PSATA_ITX_DRX_N0

Place closely pin B2

+3VS

CLK_14M_ICH

2G7X_THER_ALERT#

2
2

<28>
SB_SPKR
<35> SUS_STAT#
<4> ITP_DBRESET#

1 R323

RI#

A19
A27
A22

ITP_DBRESET#

SPKR
SUS_STAT#
SYS_RST#

<7> PM_BMBUSY#

OCP#

2
2

SPI_MISO

<15> H_STP_PCI#
<15> H_STP_CPU#

R550
SPI_CS#

2ICH_PCIE_WAKE#

PATA@
10K_0402_5%

<22> IDERST_CD#

R551
1 ICH_LOW_BAT#

@
1 R368

SPI_MOSI

8.2K_0402_5% 2 R327

IDERST_CD#

A21

GPIO26

B21
E23

GPIO27
GPIO28

2/13 Add feature:


Pull high for pure IDE interface
Pull low for SATA interface

GPIO18 / STPPCI#
GPIO20 / STPCPU#

AG18

GPIO32 / CLKRUN#

AC19
U2

T33 PAD
T40 PAD
EC_SMI#

<31>

AF19
AH18
AH19
AE19

AC1
B2

WAKE#
SERIRQ
THRM#

VGATE

AD22

VRMPWRGD

EC_SMI#

AC21
AC18
E21

GPIO6
GPIO7
GPIO8

GPIO

ICH7_BGA652~D

SB_INT_FLASH_SEL <32>

CLK_14M_ICH
CLK_48M_ICH

SUSCLK

C20

ICH_SUSCLK

B24
D23
F22

SLP_S3#
SLP_S4#
SLP_S5#

PWROK

AA4

GPIO16 / DPRSLPVR

R381
10_0402_5%
@

C483
10P_0402_50V8K
@

SLP_S3# <31>
SLP_S4# <31>
SLP_S5# <31>
ICH_POK <7,31>

2 10K_0402_5%
2 100_0402_5%

C21

ICH_LOW_BAT#

PWRBTN#

C23

PBTN_OUT#

LAN_RST#

C19

PLT_RST#

RSMRST#

Y4

EC_RSMRST#
R374 10K_0402_5%
1
2

E20
A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20

T37 PAD

1 R372
1 R95

AC22

C474
10P_0402_50V8K
@

CLK_14M_ICH <15>
CLK_48M_ICH <15>

TP0 / BATLOW#

GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25
GPIO35 / SATAREQ#
GPIO38
GPIO39

1 R336
2
100_0402_5%

SLP_S3#
SLP_S4#
SLP_S5#

GPIO33 / AZ_DOCK_EN#
GPIO34 / AZ_DOCK_RST#

ICH_PCIE_WAKE# F20
SIRQ
AH21
EC_THERM#
AF20

<15,31,42> VGATE

CLK14
CLK48

GPIO11 / SMBALERT#

AC20
AF21

T39 PAD
T46 PAD
<26,27,35> ICH_PCIE_WAKE#
<23,30,31,35> SIRQ
<31> EC_THERM#

GPIO0 / BM_BUSY#

H_STP_PCI#
H_STP_CPU#

PCI_CLKRUN#

<31,35> PCI_CLKRUN#

SATA@
10K_0402_5%

AB18
B23

T31 PAD

1 R330

OCP#

OCP#

<4>

10K_0402_5%

@
1 R359

PM_BMBUSY#

SATA
GPIO

A28

SB_SPKR
SUS_STAT#
ITP_DBRESET#

GPIO

@
1 R379

10K_0402_5%

I CH_RI#

SYS

1 R322

1 R309
2
8.2K_0402_5%

LINKALERT#

GPIO21 / SATA0GP
GPIO19 / SATA1GP
GPIO36 / SATA2GP
GPIO37 / SATA3GP

Clocks

1 R318

10K_0402_5%

1K_0402_5%

SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1

+3VALW

+3VALW
10K_0402_5%

C22
B22
A26
B25
A25

POWER MGT

10K_0402_5%

ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1

SMB

<15,27,35> ICH_SMBCLK
<15,27,35> ICH_SMBDATA

+3VALW

10K_0402_5%

10K_0402_5%
1

1 R329

R380
10_0402_5%
@

R321
2.2K_0402_5%
U4C

10K_0402_5%
D

R331
2.2K_0402_5%

R316

10K_0402_5%

R317

PCI_CLKRUN#

SIRQ

1 R326

8.2K_0402_5% 1 R333

10K_0402_5%

+3VALW
1

+3VALW

Place closely pin AC1

CLK_48M_ICH

DPRSLPVR <7,42>

PBTN_OUT# <31>
PLT_RST# <7,17,18,22,26,27,31,35>
EC_RSMRST# <31>

EC_SCI#

EC_SCI# <31>
ACIN
<31,36>
T36 PAD
EC_LID_OUT# <31>
T43 PAD
T32 PAD
T44 PAD
EC_FLASH#
EC_FLASH# <32>
SATAREQ#
SATAREQ# <15>
G7X_THER_ALERT#
G7X_THER_ALERT# <17>
T38 PAD

EC_LID_OUT#

Need update symbol

0.1U_0402_10V7K
0.1U_0402_10V7K

2
2

1 C424
1 C423

PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1
PCIE_C_TXP1

F26
F25
E28
E27

PERn1
PERp1
PETn1
PETp1

H26
H25
G28
G27

PERn2
PERp2
PETn2
PETp2

<26>
<26>
<26>
<26>

PCIE_RXN3
PCIE_RXP3
PCIE_TXN3
PCIE_TXP3

0.1U_0402_10V7K
0.1U_0402_10V7K

2
2

1 C435
1 C436

PCIE_RXN3
PCIE_RXP3
PCIE_C_TXN3
PCIE_C_TXP3

K26
K25
J28
J27

PERn3
PERp3
PETn3
PETp3

<35>
<35>
<35>
<35>

PCIE_RXN4
PCIE_RXP4
PCIE_TXN4
PCIE_TXP4

0.1U_0402_10V7K
0.1U_0402_10V7K

2
2

1 C432
1 C439

PCIE_RXN4
PCIE_RXP4
PCIE_C_TXN4
PCIE_C_TXP4

M26
M25
L28
L27

PERn4
PERp4
PETn4
PETp4

P26
P25
N28
N27

PERn5
PERp5
PETn5
PETp5

T25
T24
R28
R27

PERn6
PERp6
PETn6
PETp6

USB_OC#2

USB_OC#0

R2
P6
P1

SPI_CLK
SPI_CS#
SPI_ARB

SPI_MOSI
SPI_MISO

P5
P2

SPI_MOSI
SPI_MISO

D3
C4
D5
D4
E5
C3
A2
B3

OC0#
OC1#
OC2#
OC3#
OC4#
OC5# / GPIO29
OC6# / GPIO30
OC7# / GPIO31

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#5
USB_OC#6
USB_OC#7

SPI

<34>
<34>

SPI_CS#

PCI-EXPRESS

PCIE_RXN1
PCIE_RXP1
PCIE_TXN1
PCIE_TXP1

DIRECT MEDIA INTERFACE

U4D
<27>
<27>
<27>
<27>

USB

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

V26
V25
U28
U27

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

Y26
Y25
W28
W27

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

AB26
AB25
AA28
AA27

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

AD25
AD24
AC28
AC27

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

DMI_CLKN
DMI_CLKP

AE28
AE27

CLK_PCIE_ICH#
CLK_PCIE_ICH

C25
D25

DMI_IRCOMP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P

F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

USBRBIAS#
USBRBIAS

D2
D1

USBRBIAS

DMI_ZCOMP
DMI_IRCOMP

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

<7>
<7>
<7>
<7>

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

<7>
<7>
<7>
<7>

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

<7>
<7>
<7>
<7>

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

<7>
<7>
<7>
<7>

CLK_PCIE_ICH# <15>
CLK_PCIE_ICH <15>
R314 24.9_0402_1%
1
2
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

Within 500 mils


+1.5VS

RP13

<34>
<34>
<27>
<27>
<29>
<29>
<33>
<33>
<29>
<29>
<33>
<33>
<35>
<35>
<27>
<27>

USB_OC#2
USB_OC#3
USB_OC#1

4
3
2
1

5
6
7
8

+3VALW

10K_1206_8P4R_5%
RP14
USB_OC#0
USB_OC#5
USB_OC#6
USB_OC#7

4
3
2
1

5
6
7
8

+3VALW

10K_1206_8P4R_5%

R382 22.6_0402_1%
1
2

Within 500 mils


A

ICH7_BGA652~D

Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


ICH7-M(3/4)

Size Document Number


Custom HEL80 LA-3161P
Date:

Rev
0.2
Sheet

Thursday, February 23, 2006


1

20

of

43

+5VS

+3VS

+1.5VS

ICH_V5REF_SUS

F6

ICH_V5REF_RUN
D

C458
0.1U_0402_16V4Z

0.1U_0402_16V4Z
C457

1
C420

0.1U_0402_16V4Z
2

AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28
D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23
J22
J23
K22
K23
L22
L23
M22
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
T22
T23
T26
T27
T28
U22
U23
V22
V23
W22
W23
Y22
Y23

220U_D2_2VMR15

C425

C434

C429

0.1U_0402_16V4Z

2
0.1U_0402_16V4Z

Place close pin G10 or AD17


Place close pin
D28,T28,AD28.

+5VALW +3VALW

R365

D24

RB751V_SOD323
2

10_0402_5%

ICH_V5REF_SUS
C467

0.1U_0402_16V4Z
2

+3VS

C448

2
0.1U_0402_16V4Z

Place close pin AG28 within 100mlis.


+1.5VS_DMIPLL
R305
2
0_0603_5%

C430
0.01U_0402_16V7K

R308 +1.5VS_DMIPLLR
0.5_0603_1%
1
2
1

C421
10U_0805_10V4Z

+1.5VS

B27
+1.5VS_DMIPLL

AG28

+1.5VS

C470
0.1U_0402_16V4Z

+3VS
1

0.1U_0402_16V4Z

C452

C472

+1.5VS

0.1U_0402_16V4Z

Place close pin AH5.

+1.5VS
C461
1U_0603_10V4Z

Place close pin AH9.


+3VALW
C469
0.1U_0402_16V4Z

+1.5VS
2

C464
0.1U_0402_16V4Z

1
T45
T41

PAD
PAD

ICH_AA2
ICH_ Y7

V5REF_Sus
Vcc1_5_B[1]
Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]

AD2

VccSATAPLL

AH11

Vcc3_3[2]

AB10
AB9
AC10
AD10
AE10
AF10
AF9
AG9
AH9

Vcc1_5_A[10]
Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]

E3

VccSus3_3[19]

C1

VccUSBPLL

V5
V1
W2
W7

+3VALW

Vcc3_3 / VccHDA

U6
R7

VccDMIPLL

1
C459

Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]

A5
B13
B16
B7
C10
D15
F9
G11
G12
G16

P7

VccSus3_3[2]
VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]

A24
C24
D19
D22
G19

VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]
VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]

K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7

220U_D2_2VMR15

C449
0.1U_0402_16V4Z
1
2

C455
0.1U_0402_16V4Z

C456
4.7U_0805_10V4Z

0.1U_0402_16V4Z

Place close pin AH26

+3VS

Place close pin


A5, B7 & C10
+RTCVCC

C476
0.1U_0402_16V4Z

C465
0.1U_0402_16V4Z

+3VALW
C481
0.1U_0402_16V4Z

+3VALW
C473
0.1U_0402_16V4Z

Place close pin L1 & K3

AB17
AC17

Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]

T7
F17
G17

+1.5VS

VccSus1_05[1]

K7

C444 0.1U_0402_16V4Z
ICH_K7
PAD

T42

VccSus1_05[2]
VccSus1_05[3]

C28
G20

ICH_C28
ICH_G20

T16
T35

A1
H6
H7
J6
J7

PAD
PAD
+1.5VS
1

VccSus3_3/VccLAN3_3[1]
VccSus3_3/VccLAN3_3[2]
VccSus3_3/VccLAN3_3[3]
VccSus3_3/VccLAN3_3[4]

C453

0.1U_0402_16V4Z
1
2

+3VS
1

Vcc1_5_A[19]
Vcc1_5_A[20]

Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]

+VCCP
C450
1
2

AB8
AC8

+ C447

+3VS

AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19

W5

+3VALW

Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]
Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]

VccRTC

C454

1U_0603_10V4Z

AE23
AE26
AH26

VccSus3_3[1]

V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]

Vcc1_5_A[24]
Vcc1_5_A[25]

VccSus1_05/VccLAN1_05[1]
VccSus1_05/VccLAN1_05[2]

0.1U_0402_16V4Z

L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

VccSus3_3/VccSusHDA

Vcc3_3[1]

Vcc1_5_A[1]
Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]

AA2
Y7

V5REF[2]

AB7
AC6
AC7
AD6
AE6
AF5
AF6
AG5
AH5

Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]
Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]

C478
0.1U_0402_16V4Z

Place close pin A1

A4
A23
B1
B8
B11
B14
B17
B20
B26
B28
C2
C6
C27
D10
D13
D18
D21
D24
E1
E2
E4
E8
E15
F3
F4
F5
F12
F27
F28
G1
G2
G5
G6
G9
G14
G18
G21
G24
G25
G26
H3
H4
H5
H24
H27
H28
J1
J2
J5
J24
J25
J26
K24
K27
K28
L13
L15
L24
L25
L26
M3
M4
M5
M12
M13
M14
M15
M16
M17
M24
M27
M28
N1
N2
N5
N6
N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26
P3
P4
P12
P13
P14
P15
P16
P17
P24
P27

VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]

VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]

P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27

ICH7_BGA652~D

ICH7_BGA652~D
C445

0.1U_0402_16V4Z

Place close pin V1


Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


ICH7-M(4/4)

Size Document Number


Custom HEL80 LA-3161P
Date:

Rev
0.2

Thursday, February 23, 2006

Sheet
1

21

of

43

hexainf@hotmail.com

AD17

U4E

V5REF[1]

C468
0.1U_0402_16V4Z

G10

RB751V_SOD323

100_0402_5%

ICH_V5REF_RUN

C433
0.1U_0402_16V4Z

D23

C446
0.1U_0402_16V4Z

R355

C466
0.1U_0402_16V4Z

+VCCP
U4F

SA880400020 Marvell 8040 TQFP64_Lead Free


U11

2 8040@ 10K_0402_5%

R224 1

2 @ 10K_0402_5%

R247 1

2 8040@ 10K_0402_5%

PIDE_HIOCS16# R171 1

2 8040@ 10K_0402_5%

PIDE_R_RESET# 2
R235
2 12.1K_0603_1%
+3VS 8040@

PIDE_RESET#
8040@ 33_0402_5%

PLACE Close to U61


1
L11
1
L12

+1.8VS_VDDA
R492
8040@ 0_0603_5%
1
2

FG ND

C330

C329

2
8040@ MBK1608121YZF_0603
2
@ MBK1608121YZF_0603

+3VS

2005/09/04

SATA@
SATA_DTX_R_IRX_N0
SATA_DTX_R_IRX_P0

<19> PSATA_IRX_DTX_N0_C

PSATA_IRX_DTX_N0_C
1
C336

SATA_DTX_IRX_N0
2
3900P_0402_50V7K

<19> PSATA_IRX_DTX_P0_C

PSATA_IRX_DTX_P0_C
1
C331

SATA_DTX_IRX_P0
2
3900P_0402_50V7K

1
C216
2

1
C222
@
2

PIDE_DREQ

SATA
HDD
Connector

PIDE_INTRQ

1
R206 8040@
1
R223 8040@
1
R188 8040@
1
R263 @

JP25

T26
PAD
2

PIDE_CS1#
PIDE_DA2
PIDE_PDIAG#
1PCSEL
R198
475_0402_1%
PIDE_DD15
PIDE_DD14
PIDE_DD13
PIDE_DD12
PIDE_DD11
PIDE_DD10
PIDE_DD9
PIDE_DD8

R320

2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@

1
R194
1
R199
R_PIDE_DD3
1
R205
R_PIDE_DD11 1
R210
R_PIDE_DD4
1
R215
R_PIDE_DD10 1
R217
R_PIDE_DD5
1
R218
R_PIDE_DD9
1
R222
R_PIDE_DD6
1
R225
R_PIDE_DD8
1
R227
R_PIDE_DD7
1
R231
R_PIDE_RESET# 1
R241
R_PIDE_DD0
1
R177
R_PIDE_DD14 1
R176
R_PIDE_DD1
1
R175
R_PIDE_DD13 1
R190
R_PIDE_DIOR# 1
R181
R_PIDE_DIOW# 1
R180
R_PIDE_DREQ 1
R179
R_PIDE_DD15 1
R178
R_PIDE_DA1
1
R185
R_PIDE_INTRQ 1
R184
R_PIDE_DMACK# 1
R183
R_PIDE_DIORDY 1
R182
R_PIDE_CS1#
1
R207
R_PIDE_CS0#
1
R203
R_PIDE_DA2
1
R187
R_PIDE_DA0
1
R186
R_PIDE_PDIAG# 1
R169
R_PIDE_DD12

PIDE_DD2
0_0402_5%
PIDE_DD12
0_0402_5%
PIDE_DD3
0_0402_5%
PIDE_DD11
0_0402_5%
PIDE_DD4
0_0402_5%
PIDE_DD10
0_0402_5%
PIDE_DD5
0_0402_5%
PIDE_DD9
0_0402_5%
PIDE_DD6
0_0402_5%
PIDE_DD8
0_0402_5%
PIDE_DD7
0_0402_5%
PIDE_RESET#
0_0402_5%
PIDE_DD0
0_0402_5%
PIDE_DD14
0_0402_5%
PIDE_DD1
0_0402_5%
PIDE_DD13
0_0402_5%
PIDE_DIOR#
0_0402_5%
PIDE_DIOW#
0_0402_5%
PIDE_DREQ
0_0402_5%
PIDE_DD15
0_0402_5%
PIDE_DA1
0_0402_5%
PIDE_INTRQ
0_0402_5%
PIDE_DMACK#
0_0402_5%
PIDE_DIORDY
0_0402_5%
PIDE_CS1#
0_0402_5%
PIDE_CS0#
0_0402_5%
PIDE_DA2
0_0402_5%
PIDE_DA0
0_0402_5%
PIDE_PDIAG#
0_0402_5%

Y4
SATA_XTALI 1

R250
1

8040@

C339
27P_0402_50V8J
8040@

C340
27P_0402_50V8J
8040@

0.1U_0402_16V4Z

C498
8040@

IDERST_CD#

PLT_RST#

Y
A

4.7U_0805_10V4Z

<19>

+5VS

+3VS

C501
8040@

C303

C375

R307

1
R306

4.7U_0805_10V4Z
1

PD_IOW#
PD _IORDY
PD_IRQ
PD_A1
PD_A0
PD_CS#1
PIDE_LED#

<19> PD_IOW#
<19> PD_IORDY
<19> PD_IRQ

PD_CS#1
+5VS

2
@ 475_0402_1%
2
475_0402_1%
SATA@

PRI_CSEL

8040@

8040@
2
2
0.1U_0402_16V4Z

2005/10/06

Issued Date

2006/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

Compal Secret Data

Security Classification

PD_A[0..2] <19>
B

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

OCTEK_CDR-50DY1G
ME@

IDE_CSEL
Grounding for Master (When use SATA HDD)
Open or High for Slaver (Normal)

PD_D[0..15] <19>

JP10
IDE_RST#
PD_D7
PD_D6
PD_D5
PD_D4
PD_D3
PD_D2
PD_D1
PD_D0

0.1U_0402_16V4Z

C451
2 0.1U_0402_16V4Z

0.1U_0402_16V4Z

8040@

T30
PAD

PIDE_DD0
PIDE_DD1
PIDE_DD2
PIDE_DD3
PIDE_DD4
PIDE_DD5
PIDE_DD6
PIDE_DD7
PIDE_RESET#

PD_A[0..2]

U28
NC7SZ08P5X_NL_SC70-5

C504

+5VS
PIDE_LED#
PIDE_CS0#
PIDE_DA0
PIDE_DA1
PIDE_INTRQ
PIDE_DMACK#
PIDE_DIORDY
PIDE_DIOR#
PIDE_DIOW#
PIDE_DREQ

PD_D[0..15]
+3VS

<7,17,18,20,26,27,31,35> PLT_RST#

8040@

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44

(NEW)

PATA ODD Conn.

10M_0402_5%

+1.8VS

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44

R248
0_0402_5%
8040@

<20> IDERST_CD#

C314

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43

SUYIN_200055FB044G202ZR_44P_P2_PATA_HDD
PATA@

PIDE_LED#

<34> PIDE_LED#

SATA_XTALO

25MHZ_20PF_6X25000017
8040@

SUYIN_127072FR022G210ZR_22P_SATA
SATA@

R_PIDE_DD2

@
2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43

+5VS

2
4.7K_0402_5%
2
5.6K_0402_5%
2
10K_0402_5%
2
10K_0402_5%

SATA HDD ONLY


SATA to PATA HDD
PATA HDD ONLY

ODD
Connector

2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@
2
PATA@

PD_D2
0_0402_5%
PD_D12
0_0402_5%
PD_D3
0_0402_5%
PD_D11
0_0402_5%
PD_D4
0_0402_5%
PD_D10
0_0402_5%
PD_D5
0_0402_5%
PD_D9
0_0402_5%
PD_D6
0_0402_5%
PD_D8
0_0402_5%
PD_D7
0_0402_5%
IDE_RST#
0_0402_5%
PD_D0
0_0402_5%
PD_D14
0_0402_5%
PD_D1
0_0402_5%
PD_D13
0_0402_5%
PD_IOR#
0_0402_5%
PD_IOW#
0_0402_5%
PD_DREQ
0_0402_5%
PD_D15
0_0402_5%
PD_A1
0_0402_5%
PD_IRQ
0_0402_5%
PD_DACK#
0_0402_5%
PD _IORDY
0_0402_5%
PD_CS#3
0_0402_5%
PD_CS#1
0_0402_5%
PD_A2
0_0402_5%
PD_A0
0_0402_5%
PD_DIAG#
0_0402_5%

1
C225

Reverse pin 1 to 44, pin 2 to 43


+3VS

Place closed to Connector

PATA
HDD
Connector

0.1U_0402_16V4Z
8040@
C311

1
R113
1
R114
R_PIDE_DD3
1
R115
R_PIDE_DD11
1
R116
R_PIDE_DD4
1
R137
R_PIDE_DD10
1
R117
R_PIDE_DD5
1
R122
R_PIDE_DD9
1
R118
R_PIDE_DD6
1
R136
R_PIDE_DD8
1
R121
R_PIDE_DD7
1
R133
R_PIDE_RESET# 1
R135
R_PIDE_DD0
1
R108
R_PIDE_DD14
1
R111
R_PIDE_DD1
1
R110
R_PIDE_DD13
1
R112
R_PIDE_DIOR#
1
R106
R_PIDE_DIOW#
1
R105
R_PIDE_DREQ
1
R107
R_PIDE_DD15
1
R109
R_PIDE_DA1
1
R101
R_PIDE_INTRQ
1
R102
R_PIDE_DMACK# 1
R103
R_PIDE_DIORDY 1
R104
R_PIDE_CS1#
1
R97
R_PIDE_CS0#
1
R96
R_PIDE_DA2
1
R98
R_PIDE_DA0
1
R99
R_PIDE_PDIAG# 1
R100
R_PIDE_DD12

1
C217

+5VS

IDE

@
2

10K_0402_5%

2005/10/19

R_PIDE_DD2

1
C243

2005/11/4 Modified library pn:SP01000LU00

Marvell 8040

R_IDE

IDE

@
2

PATA HDD Conn.

PIDE_DD7

SATA

ICH7M

SATA_DTX_IRX_N0
3
SATA_DTX_IRX_P0
4
0_0404_4P2R_5%

2
1
RP16

R_SATA

1
C218

Place closed to 3811

@
2

1
C251

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

C344

PIDE_DIORDY
PSATA_ITX_DRX_P0
3
PSATA_ITX_DRX_N0
4
0_0404_4P2R_5%

@
2

1
C234

+1.8VS

0.01U_0402_16V7K
4.7U_0805_10V4Z
2 8040@ 2 8040@
2 8040@
0.1U_0402_16V4Z

SATA@

1
C236

W=60mils at least
+5VS

FGND

SATA_ITX_C_R_DRX_P0 2
SATA_ITX_C_R_DRX_N0 1
RP15

@
2

+1.8VS

88SA8040_TQFP64
8040@

1
C237

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

Title

PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15
PD_DREQ
PD_IOR#

PD_DREQ <19>
PD_IOR# <19>

PD_DACK#

PD_DACK# <19>

PD_DIAG#
PD_A2
PD_CS#3

1
C441
2

1
R315

2
100K_0402_5% +5VS
PD_CS#3 <19>

1
C440
2

1
C426
2

+5VS

1U_0603_10V4Z

ATAIOSEL

2 8040@
10K_0402_5%

+3VS

0.1U_0402_16V4Z

CNFG1 1
R246
ATAIOSEL

W=60mils at least

0.1U_0402_16V4Z

R226 1

T6

2 8040@
10K_0402_5%

1
R233

SATA_DTX_R_IRX_N0
SATA_DTX_R_IRX_P0

PLT_RST# <7,17,18,20,26,27,31,35>

0.1U_0402_16V4Z

T5
T6

GND
A+
AGND
BB+
GND

10U_0805_10V4Z

UART

T3

C338
1U_0603_10V4Z
@

1U_0603_10V4Z

25
30
8
42
57

2 @ 10K_0402_5%

1U_0603_10V4Z

VSS1
VSS2
GND_0
GND_1
GND_2

Power

R237 1

2
0_0402_5%
8040@

10U_0805_10V4Z

R490 1

T2

T2
T3

SATA_ITX_C_R_DRX_P0
SATA_ITX_C_R_DRX_N0
R249
1

10U_0805_10V4Z

26
44
4
9
41
56
24
29

SATA_RESET#

1
2
3
4
5
6
7

10U_0805_10V4Z

10K_0402_5%
8040@

HIOCS16#
HINTRQ
HDMACK#
HIORDY
HDIOR#
HDIOW#
HDMARQ
HRESET#
HPDIAG#
UAO
UAI

ISET
VDDIO_0
VDDIO_1
VDD_0
VDD_1
VDD_2
VAA1
VAA2

2 @ 10K_0402_5%

0.1U_0402_16V4Z

45
43

SATA_XTALI
SATA_XTALO

R245 1

T27
PAD
T28
PAD

22
23

T0

R212

52
53
54
55
58
59
60
16
46

XTLIN/OSC
XTLOUT

+3VS

SATA_RESET#
T0

PIDE_HIOCS16#
PIDE_INTRQ
PIDE_DMACK#
PIDE_DIORDY
PIDE_DIOR#
PIDE_DIOW#
PIDE_DREQ
PIDE_R_RESET#

17
33
34
35
36
37
38
39
40
20
19
18
21

JP9

R251
100K_0402_5%
@

10U_0805_10V4Z

HDA0
HDA1
HDA2
HCS0#
HCS1#

RST#
T0
T1
T2
T3
T4
T5
T6
T7
CNFG2
CNFG1
CNFG0
ATAIOSEL

PSATA_ITX_DRX_P0 <19>
PSATA_ITX_DRX_N0 <19>

10U_0805_10V4Z

50
51
49
48
47

TXP
TXM
RXP
RXM

SATA

2005/11/4 Modified library pn:DC010003J00


Main SATA +5V Default

SATA HDD Conn.

PIDE_DA0
PIDE_DA1
PIDE_DA2
PIDE_CS0#
PIDE_CS1#

SATA_DTX_IRX_P0
SATA_DTX_IRX_N0
PSATA_ITX_DRX_P0
PSATA_ITX_DRX_N0

32
31
27
28

HDD0
HDD1
HDD2
HDD3
HDD4
HDD5
HDD6
HDD7
HDD8
HDD9
HDD10
HDD11
HDD12
HDD13
HDD14
HDD15

+3VS

Config & Debug

62
64
2
5
7
11
13
15
14
12
10
6
3
1
63
61

Parallel ATA

PIDE_DD0
PIDE_DD1
PIDE_DD2
PIDE_DD3
PIDE_DD4
PIDE_DD5
PIDE_DD6
PIDE_DD7
PIDE_DD8
PIDE_DD9
PIDE_DD10
PIDE_DD11
PIDE_DD12
PIDE_DD13
PIDE_DD14
PIDE_DD15

0.1U_0402_16V4Z

1
C422
2

Compal Electronics, Inc.


HDD & CDROM

Size Document Number


Custom HEL80 LA-3161P
Date:

Rev
0.2
Sheet

Thursday, February 23, 2006


1

22

of

43

+S1_VCC

0.1U_0402_16V4Z

2
0.1U_0402_16V4Z

PCI_AD[0..31]

<18,25,30> PCI_AD[0..31]

PCI_CBE#[0..3]

<18,25,30> PCI_CBE#[0..3]

R197

@ 10_0402_5%

@ 10_0402_5%

1
R230

SM_CD#
43K_0402_5%

R204

+3VS

CLK_SD_48M

CLK_PCI_PCM

C295
@ 15P_0402_50V8J

C290
@ 15P_0402_50V8J

<18,25,30> PCI_RST#
<18,25,30> PCI_FRAME#
<18,25> PCI_IRDY#
<18,25,30> PCI_TRDY#
<18,25> PCI_DEVSEL#
<18,25> PCI_STOP#
<18,25> PCI_PERR#
<18> PCI_SERR#
<18,25> PCI_PAR
<18> PCI_REQ2#
<18> PCI_GNT2#
<15> CLK_PCI_PCM
+3VS

1
R229

<24> MS_PWREN#

C2
C1
D4
D2
D1
E4
E3
E2
F2
F1
G2
G3
H3
H4
J1
J2
N2
M3
N3
K4
M4
K5
L5
M5
K6
M6
N6
M7
N7
L7
K7
N8

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

E1
J3
N1
N5

CBE3#
CBE2#
CBE1#
CBE0#

PCI_RST#

G4
J4
K1
K3
L1
L2
L3
M1
M2
PCI_REQ2#
A1
PCI_GNT2#
B1
CLK_PCI_PCM H1
L8
L11

10K_0402_5%
PCI_AD20

R228 1
0_0402_5%

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

1
R192

<18> PCI_PIRQA#
2
<18> PCI_PIRQB#
<20,30,31,35> SIRQ
<34> 3IN1_LED#
<24> SDOC#

2
F4
100_0402_5%
K8
SD_PULLHIGH N9
K9
N10
SM_CD#
L10
3IN1_LED#
N11
M11
SDOC#
J9
PCI_RST#

M10

MFUNC5[3:0] = (0 1 0 1)
MFUNC5[4] = 1

<24>
SD_CD#
<24>
SD_WP#
<24> SD_PWREN#
<15> CLK_SD_48M
<24> SDCK_XDWE#

R209 1
<24>
<24>
<24>
<24>
<24>

2 33_0402_5%
SDCM_XDALE
SDDA0_XDD7
SDDA1_XDD0
SDDA2_XDCL
SDDA3_XDD4

B4
C8
D12
H11
L9
L6
N4
K2
G1
F3

B7
A11
E11
H13

S1_REG#
S1_A12
S1_A8
S1_CE1#

CRST#/RESET
CFRAME#/A23
CIRDY#/A15
CTRDY#/A22
CDEVSEL#/A21
CSTOP#/A20
CPERR#/A14
CSERR#/WAIT#
CPAR/A13
CREQ#/INPACK#
CGNT#/WE#
CCLK/A16

B9
B11
A12
A13
B13
C12
C13
A5
D13
B8
C11
B12
C5
D5

S1_RST
S1_A23
S1_A15
S1_A22
S1_A21
S1_A20
S1_A14
S1_WAIT#
S1_A13
S1_INPACK#
S1_WE#
1
R160
S1_BVD1
S1_WP

D11

S1_A19

CINT#/READY_IREQ#

D6

S1_RDY#

SPKROUT
CAUDIO/BVD2_SPKR#

M9
B5

PCM_SPK#
S1_BVD2

A4
L12
D9
C6
A2
E10
J13

S1_CD2#
S1_CD1#
S1_VS2
S1_VS1
S1_D2
S1_A18
S1_D14

MSINS#
MSPWREN#/SMPWREN#
MSBS/SMDATA1
MSCLK/SMRE#
MSDATA0/SMDATA2
MSDATA1/SMDATA6
MSDATA2/SMDATA5
MSDATA3/SMDATA3

H7
J8
H8
E9
G9
H9
G8
F9

MSBS_XDD1
MS_CLK
R161 1
MSD0_XDD2
MSD1_XDD6
MSD2_XDD5
MSD3_XDD3

SMBSY#
SMCD#
SMWP#
SMCE#

H6
J7
J6
J5

CSTSCHG/BVD1_STSCHG#
CCLKRUN#/WP_IOIS16#
CBLOCK#/A19

CCD2#/CD2#
CCD1#/CD1#
CVS2/VS2#
CVS1/VS1
CRSV3/D2
CRSV2/A18
CRSV1/D14

SD/MMC/MS/SM
VCC_SD

E8
F8
G7

SDCD#
SDWP/SMWPD#
SDPWREN33#

CLK_SD_48M

H5

SDCLKI
SDCLK/SMWE#
SDCMD/SMALE
SDDAT0/SMDATA7
SDDAT1/SMDATA0
SDDAT2/SMCLE
SDDAT3/SMDATA4
GND_SD

D3
H2
L4
M8
K11
F12
C10
B6

G5

CCBE3#/REG#
CCBE2#/A12
CCBE1#/A8
CCBE0#/CE1#

GRST#

E7

SD_CLK
F6
SDCM_XDALE E5
SDDA0_XDD7 E6
SDDA1_XDD0 F7
SDDA2_XDCL F5
SDDA3_XDD4 G6

S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3

MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
MFUNC7

SD_CD#
SD_WP#
SD_PWREN#

+VCC_SD

B2
C3
B3
A3
C4
A6
D7
C7
A8
D8
A9
C9
A10
B10
D10
E12
F10
E13
F13
F11
G10
G11
G12
H12
H10
J11
J12
K13
J10
K10
K12
L13

IDSEL

S1_A[0..25] <24>

S1_D[0..15]

CAD31/D10
CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0
CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6
CAD19/A25
CAD18/A7
CAD17/A24
CAD16/A17
CAD15/IOWR#
CAD14/A9
CAD13/IORD#
CAD12/A11
CAD11/OE#
CAD10/CE2#
CAD9/A10
CAD8/D15
CAD7/D7
CAD6/D13
CAD5/D6
CAD4/D12
CAD3/D5
CAD2/D11
CAD1/D4
CAD0/D3

PCIRST#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
PAR
PCIREQ#
PCIGNT#
PCICLK
RIOUT#_PME#
SUSPEND#

S1_A[0..25]

S1_D[0..15] <24>

+3VS

C321
4.7U_0805_10V4Z

C320
0.1U_0402_16V4Z

S1_IOWR# <24>
S1_IORD# <24>
S1_OE#
S1_CE2#

+S1_VCC

<24>
<24>

C257
0.1U_0402_16V4Z

C292
0.1U_0402_16V4Z

S1_REG# <24>
S1_CE1#

<24>

S1_RST

<24>

S1_WAIT# <24>

S1_INPACK# <24>
S1_WE# <24>
S1_A16
33_0402_5%
S1_BVD1 <24>
S1_WP
<24>

S1_RDY# <24>

S1_CD2#

S1_CD1#
2

PCM_SPK# <28>
S1_BVD2 <24>
S1_CD2#
S1_CD1#
S1_VS2
S1_VS1

<24>
<24>
<24>
<24>

C250
10P_0402_50V8K

C323
B

10P_0402_50V8K

MS_INS# <24>
MS_PWREN# <24>
MSBS_XDD1 <24>
2 33_0402_5%
MSCLK_XDRE# <24>
MSD0_XDD2 <24>
MSD1_XDD6 <24>
MSD2_XDD5 <24>
MSD3_XDD3 <24>

CB714_LFBGA169
A

**CB714 use B0 version

2005/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Cardbus Controller CB714


Size Document Number
Custom

Rev
0.2

HEL80 LA-3161P

Date:

Thursday, February 23, 2006

Sheet
1

23

of

43

hexainf@hotmail.com

2
0.1U_0402_16V4Z

1
C319

CARDBUS

1
C283

M12
N12

0.1U_0402_16V4Z
1
C259

VCCA2
VCCA1

1
C260

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

0.1U_0402_16V4Z

C296

1
C299

VCCD1#
VCCD0#

C258

A7
G13

0.1U_0402_16V4Z

U9
1

PCI Interface

0.1U_0402_16V4Z
D

+3VS

VPPD0
VPPD1
VCCD0#
VCCD1#
M13
N13

40mil

VPPD0
VPPD1
VCCD0#
VCCD1#

VPPD1
VPPD0

+3VS

<24>
<24>
<24>
<24>

VCC10
VCC9
VCC8
VCC7
VCC6
VCC5
VCC4
VCC3
VCC2
VCC1

PCMCIA Socket
Note : 11/10 modify library to meet spec
<23>

PCMCIA Power Control

S1_A[0..25]

<23> S1_D[0..15]

pn: SP01000IC00

S1_A[0..25]

02/17 modify footprint to FOX_1CA41521-EL-4F_68P_LT

S1_D[0..15]

+S1_VCC
JP17
U16

+S1_VCC

40mil
13
12
11

VCC
VCC
VCC

12V

+S1_VPP

W=40mil
C361
10U_0805_10V4Z

C360

5
6

5V
5V

R253

S1_D3
S1_D4
S1_D5
S1_D6
S1_D7
S1_CE1#
S1_A10
S1_OE#
S1_A11
S1_A9
S1_A8
S1_A13
S1_A14
S1_WE#
S1_RDY#

C317
0.1U_0402_16V4Z

C359

<23>

S1_CE1#

<23>

S1_OE#

0.1U_0402_16V4Z
+S1_VPP

VCCD0# <23>
VCCD1# <23>
VPPD0 <23>
VPPD1 <23>

C325
10U_0805_10V4Z

OC

SHDN

0.1U_0402_16V4Z

3.3V
3.3V

16

C357

10U_0805_10V4Z

3
4

GND

W=40mil

VCCD0#
VCCD1#
VPPD0
VPPD1

1
2
15
14

VCCD0
VCCD1
VPPD0
VPPD1

+3VS

C356

10

VPP

0.1U_0402_16V4Z

10U_0805_10V4Z

40mil

+5VS

C322

<23>
<23>

C318

S1_WE#
S1_RDY#
+S1_VCC
+S1_VPP

S1_A16
S1_A15
S1_A12
S1_A7
S1_A6
S1_A5
S1_A4
S1_A3
S1_A2
S1_A1
S1_A0
S1_D0
S1_D1
S1_D2
S1_WP

0.1U_0402_16V4Z

CP2211FD3_SSOP16

10K_0402_5%

S1_OE#
S1_WP
VCCD0#

1
R254
VCCD1#
1
R257

2
10K_0402_5%
2
10K_0402_5%

S1_RST
S1_CE1#
S1_CE2#

1
R443
2
R503
1
R491
1
R426
1
R432

43K_0402_5%

43K_0402_5%

43K_0402_5%

43K_0402_5%

43K_0402_5%

+S1_VCC
<23>

+S1_VCC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

S1_WP

69
70
71
72
73
74
75
76

+S1_VCC
+S1_VCC
+S1_VCC

GND
GND
D3
CD1#
D4
D11
D5
D12
D6
D13
D7
D14
CE1#
D15
A10
CE2#
OE#
VS1#
A11
IORD#
A9
IOWR#
A8
A17
A13
A18
A14
A19
WE#
A20
IREQ#
A21
VCC
VCC
VPP1
VPP2
A16
A22
A15
A23
A12
A24
A7
A25
A6
VS2#
A5
RESET
A4
WAIT#
A3
INPACK#
A2
REG#
A1
SPKR#
A0
STSCHG#
D0
D8
D1
D9
D2
D10
IOIS16#
CD2#
GND
GND

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

GND
GND
GND
GND
GND
GND
GND
GND

77
78
79
80
81
82
83
84

GND
GND
GND
GND
GND
GND
GND
GND

S1_CD1#
S1_D11
S1_D12
S1_D13
S1_D14
S1_D15
S1_CE2#
S1_VS1
S1_IORD#
S1_IOWR#
S1_A17
S1_A18
S1_A19
S1_A20
S1_A21
S1_A22
S1_A23
S1_A24
S1_A25
S1_VS2
S1_RST
S1_WAIT#
S1_INPACK#
S1_REG#
S1_BVD2
S1_BVD1
S1_D8
S1_D9
S1_D10
S1_CD2#

S1_CD1#

<23>

S1_CE2# <23>
S1_VS1
<23>
S1_IORD# <23>
S1_IOWR# <23>

+S1_VCC
+S1_VPP

S1_VS2
<23>
S1_RST
<23>
S1_WAIT# <23>
S1_INPACK# <23>
S1_REG# <23>
S1_BVD2 <23>
S1_BVD1 <23>

S1_CD2# <23>

FOX_1CA41521-EL-4F_68P_LT

+VCC_SD

C371
B

10U_0805_10V4Z

+3VS
+3VS

0.1U_0402_16V4Z

C368

+VCC_SD
<23> SDDA0_XDD7
<23> SDDA1_XDD0
<23> SDDA2_XDCL
<23> SDDA3_XDD4
<23> SDCK_XDWE#
<23> SD_WP#
<23> SDCM_XDALE
<23>
SD_CD#

R264

OUT
OUT
OUT
FLG

10K_0402_5%
1

GND
IN
IN
EN#

8
7
6
5

SDOC#

SDOC#

SDDA0_XDD7
SDDA1_XDD0
SDDA2_XDCL
SDDA3_XDD4
SDCK_XDWE#
SD_WP#
SDCM_XDALE
SD_CD#

<23>

G528_SO8
R261

Reserve for SD,MS CLK.


Close to Socket

0_0402_5%
MS_PWREN#

SDCK_XDWE# 1
C369

2
10P_0402_50V8K

MSCLK_XDRE#1
C370

2
10P_0402_50V8K

J3IN1

0.1U_0402_16V4Z

U17
1
2
3
4

10K_0402_5%

<23> MS_PWREN#

C367

+VCC_SD

+3VS

SD_PWREN#

40mil

R265

<23> SD_PWREN#

<23> MSD1_XDD6
+VCC_SD
<23> MSCLK_XDRE#
<23> MS_INS#
<23> MSD0_XDD2
<23> MSBS_XDD1
<23> MSD3_XDD3
<23> MSD2_XDD5

MSD1_XDD6

1
R538
MSCLK_XDRE#
MS_INS#
MSD0_XDD2
MSBS_XDD1
MSD3_XDD3
1
MSD2_XDD5 R539 1
R540

0_0402_5%

2
2 0_0402_5%
0_0402_5%

6
9
10
2
3
7
11
4
1
5
8

VDD_SD
DAT0_SD
DAT1_SD
DAT2_SD
CD/DAT3_SD
CLK_SD
WP_SD
CMD_SD
CD_SD
VSS_SD
VSS_SD

19
13
14
16
18
20
15
17
21
12
22
23

VCC_MS
VCC_MS
SCLK_MS
INS_MS
SDIO_MS
BS_MS
RESERVED_MS
RESERVED_MS
VSS_MS
VSS_MS
GND
GND
PROCO_MDR019-C0-1202

12/20 modified

2005/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

PCMCIA Socket
Size Document Number
Custom

Rev
0.2

HEL80 LA-3161P

Date:

Sheet

Thursday, February 23, 2006


1

24

of

43

+2.5VS_1394

+3VS

+3VS

C291

C270

C232

C309

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z


2
2
2
1394@
1394@
1394@
1394@

C310

C277

C231

U5
C265

1
2
3
4

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z


2
2
2
1394@
1394@
1394@
1394@

A0
A1
A2
GND

8
7
6
5

VCC
WP
SCL
SDA

EECK
EEDI

R146
510_0402_5%
1394@

EECK and EEDI is pull high internal


External pull high circuit is unnecessary

+3VS
L7
1394@
MBK1608301YZF_0603
1
2

20mils

PCI_STOP#
PCI_PERR#
PCI_PAR
PCI_PIRQE#
CLK_PCI_1394
PCI_GNT0#
PCI_REQ0#
1394_IDSEL
PCI _IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_FRAME#

<18,23> PCI_IRDY#
<18,23,30> PCI_TRDY#
<18,23> PCI_DEVSEL#
<18,23,30> PCI_FRAME#

87
86
73
72
62
59
REG_FB

84

REG_FB

REG_OUT

85

REG_OUT

XCPS
XREXT

60
63

XI

57

1394_XI

XO

58
67
68
69
70
71

TPB0TPB0+
TPA0TPA0+
TPBIAS0

XTPB1M
XTPB1P

XTPBIAS1

74
75
76
77
78

NC17
NC16
NC15
NC14
NC13
NC12
NC11
NC10
NC9
NC8
NC7
NC6
NC5
NC4
NC3
NC2
NC1
NC0

83
82
64
54
53
52
51
50
49
48
45
44
42
41
40
39
37
35

R142 1
R145 1
C227 1

2 1394@ 1K_0402_5%
2 1394@ 6.19K_0603_1%
2 1394@ 47P_0402_50V8J

REG_FB

+2.5VS_1394

When use external BJT


Populate Q35, R279

C228
10P_0402_50V8K
1394@

2/21 Add for Compliance Engineering request


15mils

VT6311S_LQFP128
1394@

L42

R165
54.9_0402_1%
1394@

1
R155
54.9_0402_1%
1394@

C252
0.33U_0603_10V7K
1394@

1
R153
54.9_0402_1%
1394@
2

3
1

D22
PSOT24C_SOT23
@
1
1

D21
PSOT24C_SOT23
@

R546
R547
R548
R549

1
1
1
1

2
2
2
2

JP21

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

4
3
2
1

TPA+
TPATPB+
TPB-

GND
GND
GND
GND

8
7
6
5

SUYIN_020115FB004S512ZL
1394@

R149
54.9_0402_1%
1394@

L43
1

C241
270P_0402_50V7K
1394@

WCM2012F2SF-121T04_0805
1394@

R150
4.99K_0402_1%
1394@

Modify WCM2012F2SF-900T04 this symbol for WCM2012F2SF-121T04

2005/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Note : This page copied from HBL50

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

IEEE1394 VIA VT6311S


Size Document Number
Custom

HEL80 LA-3161P

Date:

Thursday, February 23, 2006

Sheet
1

Rev
0.2
25
of

43

hexainf@hotmail.com

WCM2012F2SF-121T04_0805
1394@
@
@
@
@

C289
@ 10P_0402_50V8K

Q6
2SB1197K_SOT23
@
C

Y1
1394@
24.576MHZ_16P_X8A024576FG1H
1

2
2

2
B

C229
10P_0402_50V8K
1
2 1394@

TPA0+
TPA0TPB0+
TPB0-

R196
@ 10_0402_5%

+3VS

REG_OUT

TPBIAS0
CLK_PCI_1394

+3VS

XREXT

10mils

XTPB0M
XTPB0P
XTPA0M
XTPA0P
XTPBIAS0

PHY PORT1XTPA1M
XTPA1P

2 1394@ 1U_0603_10V4Z
2 @ 4.7K_0402_5%
2 1394@ 4.7K_0402_5%
2 1394@ 4.7K_0402_5%
2 0.1U_0402_16V4Z
1394@

1394_XO

PHY PORT0

PCI I/F

C226 1
R173 1
R147 1
R152 1
C238 1

OSCILLATOR

66
65
80
79
118
112
108
100
91
61
56
47
38
33
31
23
22
6
13
126

I2CEEN

EEDI
EECK

<18,23,30> PCI_CBE#3
<18,23,30> PCI_CBE#2
<18,23,30> PCI_CBE#1
<18,23,30> PCI_CBE#0
<18,23> PCI_STOP#
<18,23> PCI_PERR#
<18,23> PCI_PAR
<18> PCI_PIRQE#
<18,23,30> PCI_RST#
<15> CLK_PCI_1394
<18> PCI_GNT0#
<18> PCI_REQ0#

55
81
43
32

2 @ 4.7K_0402_5%

2 1394_IDSEL
1394@ 100_0402_5%

PHYRST#
BJT_CTL
I2CEN
PWRDET

R162 1

1
R219

others

26
27
28
29

PCI_AD16

EEPROM

+3VS
EECS

EECS
EEDO
SDA/EEDI
SCL/EECK

IDSEL:PCI_AD16

When use external EEPROM


Populate U14, R246, R253
Un-populate R261

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
CBE3#
CBE2#
CBE1#
CBE0#
STOP#
PERR#
PAR
INTA#
PCIRST#
PCICLK
GNT#
REQ#
IDSEL
PME#
IRDY#
TRDY#
DEVSEL#
FRAME#

+3VS

PCI_AD[0..31]

<18,23,30> PCI_AD[0..31]

VT6311S
94
95
96
97
98
101
102
103
106
107
109
113
114
115
116
117
2
3
4
7
8
9
10
11
14
15
16
18
19
20
24
25
104
119
1
12
125
127
128
88
89
90
92
93
105
34
121
123
124
120

GNDATX1
GNDARX1
GNDATX2
GNDARX2
GND19
GND18
GND17
GND16
GND15
GND10
GND9
GND8
GND7
GND6
GND5
GND4
GND3
GND2
GND1
GND0

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1
C230
C284
C267
C279
4.7U_0805_10V4Z
1394@
1394@
1394@
1394@
2
2
2
2
0.1U_0402_16V4Z

PVA5
PVA4
PVA3
PVA2
PVA1
PVA0

VDD4
VDD3
VDD2
VDD1
VCC6
VCC5
VCC4
VCC3
VCC2
VCC1

U10

46
30
21
111
99
36
17
5
122
110

+1394_PLLVDD

+2.5VS_1394

AT24C02N-10SU-2.7_SO8
1394@

+3VALW

PN : SA00000TL00 (QFN64 Lead Free)


R167

1 3.6K_0402_5%

2
R144

U8

+3VALW

+3VALW
1
4.7K_0402_5%

PCIE_PTX_IRX_P3

29

HSOP

<20> PCIE_RXN3

C307 1

0.1U_0402_10V7K

PCIE_PTX_IRX_N3

30

HSON

<20> PCIE_TXP3

23

HSIP

<20> PCIE_TXN3

24

HSIN

<15> CLK_PCIE_LAN

REFCLK_P

<15> CLK_PCIE_LAN#

27

REFCLK_N

20

PERSTB

LAN_CTRL18

VCTRL18

LAN_CTRL15

63

VCTRL15

2
2.49K_0402_1%

64

RSET

R164

R200 1

LANWAKEB

36

ISOLATEB

LAN_X1

60

CKXTAL1

LAN_X2

61

CKXTAL2

62

GVDD

2 1K_0402_1%

R201
15K_0402_5%

C249
C

1U_0603_10V4Z

27P_0402_50V8J

3
4
6
7

LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1-

MDIP2
MDIN2
MDIP3
MDIN3

9
10
12
13

LAN_MDI2+
LAN_MDI2LAN_MDI3+
LAN_MDI3-

GND
NC
NC
VCC

5
6
7
8

C224

1
0.1U_0402_16V4Z

LAN_CTRL18

+3VALW

Q7
MMJT9435T1G_SOT223

T25 PAD
T24 PAD

Q8
MMJT9435T1G_SOT223

40mil

40mil
+LAN_VDD18

10U_0805_10V4Z

+LAN_VDD15

C352

C350

0.1U_0402_16V4Z

10U_0805_10V4Z

C353
0.1U_0402_16V4Z

+LAN_VDD18

VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15

15
21
32
33
38
41
43
49
52
58

+LAN_VDD15

16
37
53
46

+3VALW

EGND

31

EGND

AVDD33

AVDD33

59

17
18
35
34
39
40
42
50
51

NC
NC
NC
NC
NC
NC
NC
NC
NC

27P_0402_50V8J

AVDD18

1
2
BLM18AG601SN1D_0603

C272
0.1U_0402_16V4Z

AVDD18
AVDD18
AVDD18
AVDD18
EVDD18

22

EVDD18

28

C281
0.1U_0402_16V4Z

C288
0.1U_0402_16V4Z

C300
0.1U_0402_16V4Z

C294

C315

C531

0.1U_0402_16V4Z

12/09 Added
+LAN_VDD15
C

AVDD33
2

5
8
11
14

0.1U_0402_16V4Z

AVDD18

C275
0.1U_0402_16V4Z

C297
0.1U_0402_16V4Z

C308
0.1U_0402_16V4Z

C305
0.1U_0402_16V4Z

C247
0.1U_0402_16V4Z

+LAN_VDD18

C245
0.1U_0402_16V4Z

+3VALW

RTL8111B_QFN64
AVDD33
C239
10U_0805_10V4Z

+3VALW
L4
1
2
BLM18AG601SN1D_0603
2
C266
1

C298
0.1U_0402_16V4Z

C246
0.1U_0402_16V4Z

C269
0.1U_0402_16V4Z

C287
0.1U_0402_16V4Z

C282
0.1U_0402_16V4Z

0.1U_0402_16V4Z

GbE Transformer: GST5009 (SP050005610) MY

LAN_CTRL15

L8

25

C256

DO
DI
SK
CS

C347

EGND

LAN_X2

C254

MDIP0
MDIN0
MDIP1
MDIN1

2
0_0603_5%

25MHZ_20PF_6X25000017
1

LAN_ACTIVITY#
LED_10/100
LED_1000
LAN_LINK#

VDD33
VDD33
VDD33
VDD33

Y3
LAN_X1

54
55
56
57

LED3
LED2
LED1
LED0

2
C248
0.1U_0402_16V4Z
@
1
R221

4
3
2
1

10U_0805_10V4Z

19

<20,27,35> ICH_PCIE_WAKE#

45
47
48
44

AT93C46-10SI-2.7_SO8

26

<7,17,18,20,22,27,31,35> PLT_RST#

+3VS

EEDO
EDDI/AUX
EESK
EECS

0.1U_0402_10V7K

2
4

2
4

C306 1

U7
<20> PCIE_RXP3

LAN Conn.

T22
JP22
LAN_ACTIVITY#

LAN_MDI3LAN_MDI3+

1
2
3

TCT1
TD1+
TD1-

MCT1
MX1+
MX1-

24
23
22

RJ45_MIDI3RJ45_MIDI3+

LAN_MDI2LAN_MDI2+

4
5
6

TCT2
TD2+
TD2-

MCT2
MX2+
MX2-

21
20
19

RJ45_MIDI2RJ45_MIDI2+

LAN_MDI1LAN_MDI1+

7
8
9

TCT3
TD3+
TD3-

MCT3
MX3+
MX3-

18
17
16

RJ45_MIDI1RJ45_MIDI1+

15
14
13

C463

R356

75_0402_1%

C462
0.01U_0402_16V7K

R370

LAN_LINK#

R138

75_0402_1%

Green LED-

Green LED+

RJ45_MIDI3-

PR4-

RJ45_MIDI3+

PR4+

RJ45_MIDI1-

PR2-

RJ45_MIDI2-

PR3-

RJ45_MIDI2+

PR3+

RJ45_MIDI1+

PR2+

RJ45_MIDI0-

PR1-

RJ45_MIDI0+

PR1+

1 300_0402_5%

R378

+3VALW

12

Yellow LED-

11

Yellow LED+

RJ45_GND
RJ45_GND

14

SHLD1

13

LANGND

1000P_1206_2KV7K
A

SHLD2

C220
1
2

75_0402_1%
2

0.01U_0402_16V7K

R349
75_0402_1%

0.5u_GST5009

0.01U_0402_16V7K

C471

C475
0.01U_0402_16V7K

FOX_JM74113-P2101-7F

10

+3VALW

RJ45_MIDI0RJ45_MIDI0+

MCT4
MX4+
MX4-

TCT4
TD4+
TD4-

1 300_0402_5%

10
11
12

LAN_MDI0LAN_MDI0+

R132

C221

C219
A

Place these components


colsed to LAN chip

0.1U_0402_16V4Z

4.7U_0805_10V4Z

Compal Electronics, Inc.


Title

LAN REALTEK RTL8111B


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Size

Document Number

Rev
0.2

HEL80 LA-3161P
Date:

Sheet

Thursday, February 23, 2006


1

26

of

43

Mini-Express Card(Slot 1-WLAN)

Mini-Express Card(Slot 2-TV)

<20,26,35> ICH_PCIE_WAKE#

JP28
R517 2
R518 2

1
1

0_0402_5%
0_0402_5%

CLK_PCIE_MCARD1#
CLK_PCIE_MCARD1

<15> CLK_PCIE_MCARD1#
<15> CLK_PCIE_MCARD1

<20> PCIE_RXN1
<20> PCIE_RXP1
<20> PCIE_TXN1
<20> PCIE_TXP1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53
2

GND1

JP20
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GND2

54

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

+3VS
+1.5VS
C511

C512

0.1U_0402_16V4Z
MINI_RF_OFF#
PLT_RST#

0.1U_0402_16V4Z

PLT_RST# <7,17,18,20,22,26,31,35>

+3VALW
+3VS
ICH_SMBCLK
ICH_SMBDATA

ICH_SMBCLK <15,20,35>
ICH_SMBDATA <15,20,35>

WLAN_AVTIVE
BT_AVTIVE
<15> CLKREQ_MCARD1#

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

R542
10K_0402_5%
2

W IRELESS_LED#

WIRELESS_LED# <34>

53

FOX_AS0B226-S56N-7F

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GND2

54

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
GND1

+3VS
+1.5VS
C403

C404

0.1U_0402_16V4Z
PLT_RST#

0.1U_0402_16V4Z

PLT_RST# <7,17,18,20,22,26,31,35>

+3VALW
ICH_SMBCLK
ICH_SMBDATA

ICH_SMBCLK <15,20,35>
ICH_SMBDATA <15,20,35>

USB20_N7
USB20_P7

USB20_N7 <20>
USB20_P7 <20>

FOX_AS0B226-S56N-7F

+3VS
+3VALW

MDC CONN.

R500

C488

JP23
2

10K_0402_5%
MINI_RF_OFF#

ICH_SDOUT_MDC

<19> ICH_SDOUT_MDC
D

Q33
2N7002_SOT23

2
G

RF_ON#

RF_ON#

<31>

R363 1

ICH_SYNC_MDC
2 33_0402_5%
ICH_RST_MDC#

GND1
RES0
IAC_SDATA_OUT
RES1
GND2
3.3V
IAC_SYNC
GND3
IAC_SDATA_IN
GND4
IAC_RESET#
IAC_BITCLK

2
4
6
8
10
12

13
14
15
16
17
18

02/06 Modified

1U_0603_10V4Z

20mil
+3VALW
ICH_BITCLK_MDC
1
C487

GND
GND
GND
GND
GND
GND

<19> ICH_SYNC_MDC
<19> ICH_AC_SDIN1
<19> ICH_RST_MDC#

1
3
5
7
9
11

ICH_BITCLK_MDC <19>

22P_0402_50V8J
3

ACES_88018-124G

Connector for MDC Rev1.5

11/9 Modify pn to SP01000FE00


+3VS

BT MODULE CONN
1

+3VALW

R541

1U_0603_10V4Z

<34> BTON_LED#

<20>
<20>
2
G

Q20
2N7002_SOT23

SI2301BDS_SOT23

JP15

BTON_LED#

W=40mils

R383

+BT_VCC

4.7U_0805_10V4Z

10K_0402_5%
C477

C482

Compal Secret Data


2005/10/06

Issued Date

2006/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

12/09 Modified

0.1U_0402_16V4Z

Security Classification

1
2
3
4
5
6
7
8
9
10

USB20_P1
USB20_N1
BTON_LED
WLAN_AVTIVE
BT_AVTIVE

USB20_P1
USB20_N1

Title

1
2
3
4
5
6
7
8
GND1
GND2

MOLEX_53780-0870
ME@

Compal Electronics, Inc.


Mini Card / MDC CONN

Size Document Number


Custom HEL80/81 LA-3161P
Date:

Rev
0.2

Thursday, February 23, 2006

Sheet
E

27

of

43

hexainf@hotmail.com

2
Q19

+BT_VCC

1
100K_0402_5%

<31> BTPWR_ON#

2
R384

0.1U_0402_16V4Z
BTPWR_ON#

C486

C485

10K_0402_5%
2

+VDDA

28.7K for Module Design (VDDA = 4.702)

R496
10K_0402_5%

+5VS

2
1U_0603_10V4Z

1
1
L9 1
C373
C364
2
@ KC FBM-L11-201209-221LMAT_0805
10U_0805_10V4Z
2
2
0.1U_0402_16V4Z

R497
10K_0402_5%
2

R252

C343 1
1U_0603_10V4Z

PCM_SPK#

R255

2
B
E

C351 1
1U_0603_10V4Z

SB_SPKR

R258

CNOISE

GND

+VDDA

SD

R262
30K_0402_1%
1

4.85V

C366
10U_0805_10V4Z

C374

MONO_IN

1U_0603_10V4Z
1
2
Q24
R495
2SC2411K_SC59 2.4K_0402_5%

R259
10K_0402_1%

0.1U_0402_16V4Z

2
1

<20>

560_0402_5%

ERROR

560_0402_5%

<23>

VOUT
SENSE or ADJ

SI9182DH-AD_MSOP8

C509
1
2

560_0402_5%

DELAY

C337 1
1U_0603_10V4Z

BEEP#

<31>

VIN

40mil
2

1
C510

(output = 250 mA)


U18

60mil

L10 1
2
KC FBM-L11-201209-221LMAT_0805

D3
RB751V_SOD323
2

R256
10K_0402_5%

HD Audio Codec
+AVDD_AC97
L13

<29>

AMP_RIGHT

16

MIC2_L

SURR_OUT_L

39

HP_C_L

17

MIC2_R

SURR_OUT_R

41

HP_C_R

23

LINE1_L

SIDESURR_OUT_L

45

24

LINE1_R

SIDESURR_OUT_R

46

18

CD_L

CEN_OUT

43

LFE_OUT

44

BIT_CLK

SDATA_IN

MIC1_L

21

MIC1_R
C332
220P_0402_50V7K

22

MIC1_R

12

PCBEEP

<19> ICH_RST_AUDIO#

11

RESET#

<19> ICH_SYNC_AUDIO

10

C341
1

C333
220P_0402_50V7K

AMP_LEFT <29>
AMP_RIGHT <29>

C365 1

PIN37_VREFO

37

LINE1_VREFO

29

LINE2_VREFO

31

SYNC
MIC1_VREFO_L
SDATA_OUT

2
3
13
34

GPIO0
GPIO1
SENSE A
SENSE B

47

SPDIFI/EAPD

48

28

MIC1_VREFO_R

32

MIC2_VREFO

30

VREF

27

C540
100P_0402_25V8K

2
FBMA-11-100505-301T 0402

4
7

2/13 modify this symbol to


FBMA-11-100505-301T 0402

HP_C_L

<29>

HP_C_R

<29>

2 22P_0402_50V8J
ICH_BITCLK_AUDIO <19>

R260 1

2 33_0402_5%

ICH_AC_SDIN0 <19>

J3
1

10mil
MIC1_VREFO_L

J6

MIC1_VREFO_R

AC97_VREF

@
2

JUMP_43X79

@
2

JUMP_43X79

10mil
1

JDREF

40

SPDIFO

VAUX

33

DVSS1
DVSS2

AVSS1
AVSS2

26
42

R266
20K_0402_1%

C362
10U_0805_10V4Z

ALC883-LF_LQFP48

DGND

1
R515

2
0_0603_5%

1
R498

2
@ 0_0603_5%

1
R494

2
@ 0_0603_5%

2005/09/20

1
L45

SPDIF

+3VS

10U_0805_10V4Z

<19> ICH_SDOUT_AUDIO

<29>

C376

AMP_LEFT

36

CD_GND

MIC1_R

35

FRONT_OUT_R

CD_R

MIC1_C_L
1U_0603_10V4Z
MIC1_C_R
1U_0603_10V4Z
MONO_IN

DVDD2

FRONT_OUT_L

LINE2_R

19
2

DVDD1

LINE2_L

20

15

R244

C342

C372

0.1U_0402_16V4Z

14

2.2K_0402_5%
MIC1_L

C363

38

U19

R243

MIC1_L

FBM-L11-160808-800LMT_0603

C378

2
0.1U_0402_16V4Z

2.2K_0402_5%
2
<29>

MIC1_VREFO_R

MIC1_VREFO_L

0.1U_0402_16V4Z

40mil
25

FBM-L11-160808-800LMT_0603
C355
10U_0805_10V4Z

0.1U_0402_16V4Z
1
1
C358

AVDD2

+VDDA

AVDD1

L44

20mil

GNDA
GND

GNDA

Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.


HD CODEC ALC883

Size Document Number


Custom HEL80 LA-3161P
Date:

Rev
0.2
Sheet

Thursday, February 23, 2006


E

28

of

43

+5VAMP

W=40mil

JP18

4.7U_0805_10V4Z

20mil

VOL_AMP
VOLMAX
1
0_0402_5%
NBA_PLUG

BYPASS

VOLMAX

13

SE/BTL#

6
3
4

20mil
1

SPKL-

16

SPKR-

LOUT+

11

SPKL+

ROUT+

14

SPKR+

GND
GND

5
12

LINRINBYPASS

D26
PSOT24C_SOT23

D27
PSOT24C_SOT23

+5VAMP
+5VAMP

APA2068KAI-TRL_SOP16

+5VAMP

C513
4.7U_0805_10V4Z

NBA_PLUG

R523

R516

100K_0402_5%

100K_0402_5%

2 SPDIF_PLUG#

Q27
SI2301BDS_SOT23

+5VAMP

C515

AMP_LEFT_RC
AMP_RIGHT_RC

LOUTROUT-

VOLUME

ACES_85204-0400
ME@

Speaker Conn.

2
1U_0603_10V4Z
2
1U_0603_10V4Z

MUTE
SHUTDOWN#

1
2
3
4

1K_0402_1%
@ R507
2
1

<28> AMP_RIGHT

C514
1K_0402_1%
@ R506
2
1

<28> AMP_LEFT

1
0.47U_0603_16V4Z
1
0.47U_0603_16V4Z

1
2

SPK_L+
SPK_LSPK_R+
SPK_R-

2
R501
2
C520
2
C519

MUTE
SHUTDOWN#

0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%

1 0.1U_0402_16V4Z

VDD
VDD

2
2
2
2

C517 2

10
15

1
1
1
1

U34
1

R514
R512
R513
R511

SPKL+
SPKLSPKR+
SPKR-

11/10 modify pn to SP02000G100

C345

0.1U_0402_16V4Z

PAD-OPEN 3x3m

+5VAMP

+5VALW

C354

PJP3

D
+5VAMP

SPDIF_PLUG#
2
G Q28
2N7002_SOT23

R504
10K_0402_5%
2

R505

D
Q25
2N7002_SOT23

2
G

<31> EC_MUTE

SPDIF_PLUG#

NBA_PLUG

Un-Plug

HP_Plug_In

SPDIF_Plug_In

(0.65V -> 10dB )


R508

1.5K_0402_1%
1
R502

2
S

VOL_AMP

1
1 2
3

SPDIF_PLUG# 2
Q26 G
2N7002_SOT23 @

SHUTDOWN#
2

10K_0402_5%

R509
@
5.1K_0402_1%

20mil

+5VSPDIF

MUTE

2
10K_0402_5%
C516

0.1U_0402_16V4Z

HPF Fc = 338Hz
R=1K, C=0.22U for HBQ60
L38
3

+3VS

SPDIF_PLUG#
+3VS

<28>

MIC1_R

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

MIC1_L
INT_MIC_L
MIC1_R
SPDIF_PLUG#
HP_L
HP_R

2
@ 150U_D_6.3VM
2
@ 150U_D_6.3VM
<28>

SPDIF

SPDIF

12/12 Modified
<20>
<20>

USB20_N4
USB20_P4

USB20_N4
USB20_P4
+5VSPDIF
USB20_N2
USB20_P2
+USB_VCCB

USB20_N2
USB20_P2

10
SVDD

PVDD

OUTL

5
C536
1U_0603_10V4Z
HPA@

SGND

C1N

PGND

C1P

17

NC-4

NC-6

NC-8

NC-12

12

NC-16

16

NC-20

20

INL

HPA@ 1U_0603_10V4Z
1

11

INR

SVss

13

1
C535

OUTR

HP_L

11/10 Modify pn to SP02000BJ00

2005/12/12 Modified

ALC883

HPA@

APA@

HP@

MAX4411ETP+_TQFN20
HPA@

Int MIC Conn.


Head Phone
AMP

15mil

L46
INT_MIC_L

2/16 Add for EMI

APA
AMP

2 FBMA-11-100505-301T 0402
1
L47
1
C541

2
FBMA-11-100505-301T 0402

@
8P_0402_50V8K 2

MIC1
1
2

1
2

3
4

GND
GND

ACES_88231-02001

PN : SP02000EZ00

HP

Compal Secret Data

Security Classification

2005/12/12 Modified

2005/10/06

Issued Date

2006/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

HP_R

BOM Structure
15

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
ACES_87213-2000
ME@

SHDNL#

PVss

2
2
1HP_LEFT_C
C534
HPA@ 1U_0603_10V4Z

SHDNR#

C533
HPA@ 1U_0603_10V4Z
2
1HP_RIGHT_C

19

18

HP_C_L

C522

MIC1_L

<20>
<20>

U38
14

EC_MUTE#

<28>

SPKL+
SPKR+

C521

<28>

D
G

HP_C_R

HP_C_R

R537
100K_0402_5%
HPA@

3
Q35
2N7002_SOT23
HPA@

<28>

<28>

R533 HP@
1
0_0402_5%
2
1
0_0402_5%
R534 HP@
R535 APA@
2
1
2
1 0_0402_5%
0_0402_5%
R536 APA@
2

JP19

1U_0603_10V4Z
HPA@ 1

3
Q34
2N7002_SOT23
HPA@
EC_MUTE

HP_C_L

20mil

+HP_VDD

2
1
MBK1608301YZF_0603
HPA@
C532

<28>

HEAD PHONE AMP

Audio Jack/USB Conn.

Title

Compal Electronics, Inc.


AMP & Audio Jack

Size Document Number


Custom HEL80 LA-3161P
Date:

Rev
0.2

Thursday, February 23, 2006

Sheet
E

29

of

43

hexainf@hotmail.com

INT_KBD CONN.( TYPE "D" KB)


Power BTN

KSI[0..7]

KSI[0..7]

KSO[0..15]

<31>

KSO[0..15] <31>
KSI1
KSI7
KSI6
KSO9

C109
C114
C118
C115

JP13

2
2
2
2

@ 100P_0402_50V8J
@ 100P_0402_50V8J
@ 100P_0402_50V8J
@ 100P_0402_50V8J

+3VALW

@ 100P_0402_50V8J
@ 100P_0402_50V8J
@ 100P_0402_50V8J
@ 100P_0402_50V8J

1
1
1
1

2
2
2
2

@ 100P_0402_50V8J
@ 100P_0402_50V8J
@ 100P_0402_50V8J
@ 100P_0402_50V8J

J2
J5

2
2

1
@ JOPEN
1
@ JOPEN

R267
100K_0402_5%

Bottom Side
D6
<34> ON/OFFBTN#

ON/OFFBTN#

ON/OFF#

ON/OFF# <31>

51ON#

51ON#

1
DAN202U_SC70

ACES_85202-2505L_25P_P1

C129
C126
C104
C105

1
1
1
1

2
2
2
2

@ 100P_0402_50V8J
@ 100P_0402_50V8J
@ 100P_0402_50V8J
@ 100P_0402_50V8J

KSO6
KSO3
KSO12
KSO13

C106
C110
C111
C112

1
1
1
1

2
2
2
2

@ 100P_0402_50V8J
@ 100P_0402_50V8J
@ 100P_0402_50V8J
@ 100P_0402_50V8J

KSO14
KSO11
KSO10
KSO15

C113
C116
C117
C122

1
1
1
1

2
2
2
2

@ 100P_0402_50V8J
@ 100P_0402_50V8J
@ 100P_0402_50V8J
@ 100P_0402_50V8J

<31>

EC_ON

EC_ON

KSO2
KSO4
KSO7
KSO8

2
G

<34,36>

2
2
2
2

C377

D4
C

RLZ20A_LL34

1
2

C124
C127
C128
C125

1
1
1
1

1000P_0402_50V7K

KSI3
KSO5
KSO1
KSI0

C119
C120
C121
C123

KSI4
KSI5
KSO0
KSI2

TOP Side

25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

1
1
1
1

KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1

Q11
2N7002_SOT23

R268

2005/12/21 Modified footprint : ACES_88502-2501_25P

10K_0402_5%

2005/12/21 Modified library pn:SP01000MZ00

JP16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

JP24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

FOR LPC SIO DEBUG PORT

+5VS
+3VS

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ#0
PCI_RST#
SIRQ

CLK_14M_SIO <15>

LPC_FRAME# <19,31,35>
LPC_DRQ#0 <19>
PCI_RST# <18,23,25>
CLK_PCI_DB <15>
SIRQ
<20,23,31,35>

LPC_AD[0..3]

2
R140

LPC_AD[0..3] <19,31,35>

1
10K_0402_5%

ACES_85201-2005
ME@

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

PCI_CBE#0
PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
PCI_AD1
PCI_AD3
PCI_AD5
PCI_AD7
PCI_AD8
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PCI_CBE#0 <18,23,25>
PCI_AD6 <18,23,25>
PCI_AD4 <18,23,25>
PCI_AD2 <18,23,25>
PCI_AD0 <18,23,25>
PCI_AD1 <18,23,25>
PCI_AD3 <18,23,25>
PCI_AD5 <18,23,25>
PCI_AD7 <18,23,25>
PCI_AD8 <18,23,25>
PCI_CBE#1 <18,23,25>
PCI_CBE#2 <18,23,25>
PCI_CBE#3 <18,23,25>

FOR PORT 80 DEBUG PORT

EC DEBUG PORT

JP26

<31>

EC_TX

EC_TX

1
2
3
4

ACES_85205-0400
ME@

CLK_PCI_DB <15>
+5VS
PCI_RST# <18,23,25>
PCI_FRAME# <18,23,25>
PCI_TRDY# <18,23,25>
PCI_AD9 <18,23,25>

PCI_AD9

1
2
3
4

+5VALW

ACES_85201-2005

Not lead free

Not lead free


Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


KBD,ON/OFF,T/P,LED/B,DEBUG

Size Document Number


Custom HEL80 LA-3161P
Date:

Rev
0.2
Sheet

Thursday, February 23, 2006


1

30

of

43

Analog Board ID definition,


Please see page 3.
+3VALW

+EC_AVCC

+EC_AVCC

C493

1
R446

<18> PCI_PME#

EC_PME#

2
0_0402_5%

KSO[0..15]
<30>

KSI[0..7]

+3VALW

<30>

RP17
1
2
3
4

KSO[0..15]

8
7
6
5

KSI[0..7]

FR D#
FSEL#

<35>
RCIRRX
<34> PROGRAM_BTN#

100K_1206_8P4R_5%
+5VALW
1
R191
1
R195

<4>
<4>
<32,37>
<32,37>

EC_SMB_CK1
2
4.7K_0402_5%
EC_SMB_DA1
2
4.7K_0402_5%

<30>
EC_TX
<20> SLP_S4#
<34> PWR_LED#
<34> NUM_LED#
<34> CHARGE_LED0#
<34> CHARGE_LED1#
<34> CAPS_LED#
<34> SCROLL_LED#
<33,35,40> SYSON

<20> EC_RSMRST#
<16> BKOFF#
<20> SLP_S3#
<20> EC_LID_OUT#
<20> SLP_S5#
<20>
EC_SMI#
R460 1
<34> USER_DEFINED#
<33> LID_SWITCH#
<17,32,33,35,40,41> SUSP#
<20> PBTN_OUT#

+3VALW

R436

R202

1
R444
1
R452

+3VS
4.7K_0402_5%
@

4.7K_0402_5%
@

EC_SMB_CK2
2
4.7K_0402_5%
EC_SMB_DA2
2
4.7K_0402_5%
C496

INVT_PWM/GPIO0F/PWM1
BEEP#/GPIO10/PWM2
OUT BEEP/GPIO12/PWM3
ACOFF/GPIO18/PWM4
FAN SPEED1/GPIO14/FANFB1
FAN SPEED2/GPIO15/FANFB2

25
27
30
31
32
33

INVT_PWM
BEEP#
INTERNET#
ACOFF
FAN_SPEED1
MB_ID

PSCLK1
PSDAT1
PSCLK2
PSDAT2
PSCLK3
PSDAT3

91
92
93
94
95
96

MODE#
VOL_UP#
VOL_DN#
STOP#
TP_CLK
TP_DATA

EC_SMB_DA2
EC_SMB_CK2
EC_SMB_DA1
EC_SMB_CK1

88
87
86
85

EC_TX

34
35
PWR_LED#
38
NUM_LED#
40
CHARGE_LED0# 99
CHARGE_LED1# 101
CAPS_LED#
100
SCROLL_LED# 102
SYSON
104
EC_RSMRST#
BKOFF#
SLP_S3#
EC_LID_OUT#
SLP_S5#
EC_SMI#
0_0402_5%
2
LID_SWITCH#
SUSP#
PBTN_OUT#
EC_PME#

4
7
8
16
17
18
19
20
21
22
23

PS2 interface

PCM_SPK#/EMAIL_LED#/ GPIO16
SB_SPKR/PWR_SUSP_LED#/ GPIO17
PWRLED#/ GPIO19
NUMLED#/ GPIO1A
BATT CHGI LED#/ E51CS#
BATT LOW LED#/ E51MR0
CAPS LED#/ E51TMR1
ARROW LED#/ E51 INT0
SYSON/GPIO56/ E51 INT1
EC_RSMRST#/ GPIO02
BKOFF#/GPIO03
PM SLP S3#/GPIO04
EC LID OUT#/GPIO06
PM SLP S05#/ GPIO07
EC SMI#/GPIO08
EC SWI#/GPIO09
LID SW#/ GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
EC PME#/GPIO0D

@ 100P_0402_50V8J
140
138

XCLKO
XCLKI

2/20 New pin define

90

PROGRAM_BTN#

User-1

30

INTERNET#

User-2

97

EMAIL#

INTERNET

19

USER_DEFINED#

EMAIL

41
43
29
36
45
46

EC_ON
AC IN
EC_THERM#
ON/OFF#
ICH_POK
RF_ON#

81
82
83
137
142
143

EC_MUTE
FSTCHG
VR_ON
BTPWR_ON#
VGATE
KILL_SW#

2005/10/06

+3VALW

EC_MUTE
<32>

KBA[0..19]

<32>

ADB[0..7]

1
R174
INTERNET# 1
R529
EMAIL#
1
R530

KBA[0..19]
ADB[0..7]

2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%

+5VS
TP_CLK 1
R211
TP_DATA 1
R216

2
4.7K_0402_5%
2
4.7K_0402_5%

KBA1

2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%

+3VALW
1
R238
KBA4
1
R239
KBA5
1
R240
ENBKL
EMAIL#
FRD#
FWR#
FSEL#

<16>
<34>
<32>
<32>
<32>

R242
CRY1

CRY2
@ 20M_0603_5%

EC_ON
<30>
ACIN
<20,36>
EC_THERM# <20>
ON/OFF# <30>
ICH_POK <7,20>
RF_ON# <27>
C335

EC_MUTE <29>
FSTCHG <38>
VR_ON
<42>
BTPWR_ON# <27>
VGATE
<15,20,42>
KILL_SW# <33>

10P_0402_50V8K

KB910L_LQFP144

C334
10P_0402_50V8K

X1
32.768KHZ_12.5P_1TJS125DJ2A073
A

2006/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Rb

0_0402_5%
14W@

Compal Secret Data

Security Classification
Issued Date

2/20 New added


5

ENBKL
EMAIL#
FR D#
FW R#
FSEL#

ALI/MH#/GPIO40
FSTCHG/GPIO41
VR ON/ GPIO42
GPIO57/GPIO57
GPIO58/GPIO58
GPIO59/GPIO59

MB_ID

ECAGND

Pin number

84
97
135
136
144

EC ON/ GPIO1B
AC IN/ GPIO1C
ECTHERM#/GPIO11
ONOFF/GPIO18
PCMRST#/GPIO1E
WL OFF#/GPIO1F

C495
CRY1
CRY2

SELIO2#/ GPIO43
SELIO#/ GPIO50
FRD#/RD#
FWR#/WR#
FSEL#/SELMEM#

SM BUS

Ra

100K_0402_5%
15W@

MODE#
<34>
VOL_UP# <34>
VOL_DN# <34>
STOP#
<34>
TP_CLK <34>
TP_DATA <34>

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

125
126
128
130
131
132
133
134
111
112
113
114
115
116
117
118
119
120
121
122
123
124
110
109
108
107
106
98

Data
BUS

R166

INVT_PWM <16>
BEEP#
<28>
INTERNET# <34>
ACOFF
<36,38>
FAN_SPEED1 <4>

R159

ADB0/D0
ADB1/D1
ADB2/D2
ADB3/ D3
ADB4/D4
ADB5/D5
ADB6/D6
ADB7/D7
KBA0/A0
KBA1/A1
KBA2/A2
KBA3/A3
KBA4/A4
KBA5/A5
KBA6/A6
KBA7/A7
KBA8/A8
KBA9/A9
KBA10/A10
KBA11/A11
KBA12/A12
KBA13/A13
KBA14/A14
KBA15/A15
KBA16/A16
KBA17/A17
KBA18/A18
KBA19/A19

Address
BUS

EC SMD2/ GPIO47/SDA2
EC SMC2/GPIO46/SCL2
EC SMD1/GPIO44/SDA1
EC SMC1/GPIO44/SCL1

Pin name

12/9 Modified with pin 35

KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25
KSO6/GPIO26
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
EC URXD/KSO16/GPIO48
EC UTXD/KSO17/GPIO49

+3VALW

47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
89
90

key Matrix
scan

DAC_BRIG <16>
EN_FAN1 <4>
IREF
<38>
PAD T23

DAC_BRIG
EN_FAN1
IREF

<42>

2
0.1U_0402_16V4Z

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
RCIRRX
PROGRAM_BTN#

1
1

76
78
79
80

139
129
103
13
28
39

@ 100P_0402_50V8J

EC_SMB_DA2
EC_SMB_CK2
EC_SMB_DA1
EC_SMB_CK1

1
C244

Title

Compal Electronics, Inc.


ENE-KB910L

Size Document Number


Custom
HEL80 LA-3161P
Date:

R ev
0.2

Thursday, February 23, 2006

Sheet
1

31

of

43

hexainf@hotmail.com

@ 10K_0402_5%

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPI032
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPI035
KSI6/GPIO36
KSI7/GPIO37

BATT_TEMP <37>
POUT

OUT

R440

63
64
65
66
67
68
69
70

ECAGND
2
1
C268 0.01U_0402_16V7K
BATT_OVP <38>

SKU_ID

DAC_BRIG/DA0/GPIO3D
EN DFAN1/DA1/GPIO3D
IREF2/DA2
EN DFAN2/DA3/ GPIO3F
DA output or GPO

PWR

AGND

BATT_TEMP
BATT_OVP

NC

+3VALW

71
72
73
74

BATTEMP/AD0/GPIO38
BATT OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
AD BID0/AD3/GPIO3B
AD INtput or GPI

FAN/PWM
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

UMA@

0.1U_0402_16V4Z

0_0402_5%
VGA@

IN

C500
@ 22P_0402_50V8J

<7,17,18,20,22,26,27,35> PLT_RST#
2
47K_0402_5%
<20>
EC_SCI#
<20,35> PCI_CLKRUN#
2
C233

8.2K_0402_5%

Rb

NC

1
R143

+3VALW

1
@ 10_0402_5%

GA20/ GPIO00/GA20
KBRST#/GPIO01/KBRST#
SERIRQ
LPC_FRAME# / LFRAME#
LPC AD3/LAD3
LPC AD2/LAD2
Host
LPC AD1/LAD1 INTERFACE
LPC AD0/LAD0
CLK_PCI_EC/PCICLK
PCIRST#
EC RST#/ ECRST#
EC SCI#/SCI#/GPIO0E
PM_CLKRUN#/ CLKRUN#

77

2
R465

R420
0.1U_0402_16V4Z

GND
GND
GND
GND
GND
GND

<15> CLK_PCI_LPC

1
2
3
5
LPC_AD3
6
LPC_AD2
9
LPC_AD1
10
LPC_AD0
12
14
15
EC_RST#
42
EC_SCI#
24
1
2
44
R148
@ 0_0402_5%

R420

75

SKU_ID

U13
<19>
GATEA20
<19>
KB_RST#
<20,23,30,35> SIRQ
<19,30,35> LPC_FRAME#
<19,30,35> LPC_AD3
<19,30,35> LPC_AD2
<19,30,35> LPC_AD1
<19,30,35> LPC_AD0
2

Ra

100K_0402_5%

EC_AVCC / AVCC

C235
1000P_0402_50V7K

C276
1000P_0402_50V7K

C502
0.1U_0402_16V4Z

C328
0.1U_0402_16V4Z

C327
0.1U_0402_16V4Z

C316
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1000P_0402_50V7K
1 ECAGND 2
1
2
L6
FBM-L11-160808-800LMT_0603

For HEL81

R416

C261

11
26
37
105
127
141

VCC/ EC VCC
VCC / EC VCC
VCC / EC VCC
VCC / EC VCC
VCC
VCC

+3VALW

+3VALW
L5
FBM-L11-160808-800LMT_0603
1
2
2
C255

+5VALW
1

+5VALW
C497 1

R488

U31
8
7
6
5

1
2

R493
100K_0402_5%

SUSP#

<31,37> EC_SMB_CK1
<31,37> EC_SMB_DA1

<17,31,33,35,40,41>

2
G

0.1U_0402_16V4Z

+3VALW

C508
1

2 0.1U_0402_16V4Z

100K_0402_5%

+3VALW

VCC
WP
SCL
SDA

A0
A1
A2
GND

1
2
3
4

AT24C16N10SC-2.7_SO8

5
A

EC_FLASH# <20>

R459
Q23
2N7002_SOT23

100K_0402_5%
2

U33
NC7SZ32P5X_NL_SC70-5

G Vcc

FWE#

FWR#

<31>

FOR DEBUG ONLY

INT_FLASH_EN#

C489 1

+3VALW

P
FSEL#

FSEL#

0.1U_0402_16V4Z

100K_0402_5%

1
Y

1
R392

<31>

OE#

R391 1

2 INT_FSEL#
22_0402_5%

R390

U29
2

10K_0402_5%

SN74AHCT1G125DCKR_SC70-5

+3VALW
1
R396

2
@ 0_0402_5%

12/9 Modified BOM Structure

<31>

KBA[0..19]

<31>

ADB[0..7]

KBA[0..19]
ADB[0..7]

1MB Flash ROM


1MB ROM Socket

+3VALW
U32

<31>

FRD#

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

21
20
19
18
17
16
15
14
8
7
36
6
5
4
3
2
1
40
13
37

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

INT_FSEL#
FR D#
FWE#

22
24
9

CE#
OE#
WE#

VCC0
VCC1

31
30

D0
D1
D2
D3
D4
D5
D6
D7

25
26
27
28
32
33
34
35

RP#
NC
READY/BUSY#
NC0
NC1

10
11
12
29
38

GND0
GND1

23
39

1
ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

JP27
C491
0.1U_0402_16V4Z

SB_INT_FLASH_SEL tie to ATI SB


GPIO1 and pull down

R489
RESET#

<20> SB_INT_FLASH_SEL
+3VALW

100K_0402_5%

KBA16
KBA15
KBA14
KBA13
KBA12
KBA11
KBA9
KBA8
FWE#
RESET#
INT_FLASH_EN#
SB_INT_FLASH_SEL
KBA18
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

KBA17

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

KBA19
KBA10
ADB7
ADB6
ADB5
ADB4
+3VALW
ADB3
ADB2
ADB1
ADB0
FR D#
FSEL#
KBA0

SUYIN_80065AR-040G2T

SST39VF080-70_TSOP40

Not Lead Free

Compal Secret Data

Security Classification
Issued Date

2005/10/06

Deciphered Date

2006/10/06

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.


BIOS & EC I/O Port

Size Document Number


Custom HEL80 LA-3161P
Date:

Thursday, February 23, 2006

Rev
0.2
Sheet

32

of

43

+5VALW to +5VS Transfer


1

+5VALW

+5VS

+3VALW to +3VS Transfer

+1.8V to +1.8VS Transfer

+3VALW

+1.8V

+3VS
U37

10U_0805_10V4Z

8
7
6
5

C529

D
D
D
D

S
S
S
G

1
2
3
4

SI4800BDY_SO8

R528

AOS 4422

C528
10U_0805_10V4Z

+VSB

0.1U_0402_16V4Z

10U_0805_10V4Z

D
D
D
D

U25
S
S
S
G

1
2
3
4

+VSB

AOS 4422

10U_0805_10V4Z

8
7
6
5

0.1U_0402_16V4Z

D
D
D
D

1
2
3
4

S
S
S
G

SI4800BDY_SO8

R304

C145
10U_0805_10V4Z

C155
0.1U_0402_16V4Z

AOS 4422

33K_0402_5%

2 SUSP
G
Q30
2N7002_SOT23

R296

470_0603_5%
@

1 1

470_0603_5%
@

D
2 SUSP
G
Q29
2N7002_SOT23

R62

470_0603_5%
@

D
SUSP
2
G
Q17
2N7002_SOT23

2
R295

+2.5VS

1 1

Q31
2N7002_SOT23

+1.8V

470_0603_5%
@

D
2 SYSON#
G
Q16
2N7002_SOT23

2
G

<17,31,32,35,40,41> SUSP#

1 1

1 1

1
1

2
1

Q12
2N7002_SOT23

470_0603_5%
@

2
C407
0.1U_0603_25V7K

+0.9VS

R526

2
G
3

SUSP

SUSP

+1.8VS

R527

10K_0402_5%
<41>

Q18
2N7002_SOT23

1 1

2
R525

47K_0402_5%

<31,35,40> SYSON

+5VS

2
G

1
R271

SYSON#

SUSP

+5VALW

C326
0.1U_0603_25V7K

+5VALW

Q9
2N7002_SOT23
3

2
G

0.1U_0603_25V7K

C530
SUSP

Q32
2N7002_SOT23

2
G

1
1

C408

C348
10U_0805_10V4Z

SI4800BDY_SO8

R236

C349

47K_0402_5%

SUSP

8
7
6
5

C346

C527

10K_0402_5%

+1.8VS

U15

+VSB

2 SUSP
G
Q3
2N7002_SOT23

LID Switch
CMOS Camera Conn
1
R141

R151 1

2
0_0402_5%

+5VS

VDD

U6

2 100K_0402_5%

+3VALW

OUTPUT
2

0.1U_0402_16V4Z

4.7U_0805_10V4Z
@ 2

LID_SWITCH# <31>
2

A3212ELHLT-T_SOT23W-3

C385

C242

C386

0.1U_0402_16V4Z

10P_0402_50V8K

JP11
USB20_N3
USB20_P3

USB20_N3
USB20_P3

<20>
<20>

1
GND

C223

D14
PSOT24C_SOT23
@

1
2
3
4
5
GND1
GND2

ACES_88266-05001
ME@

12/9 Change to SA032120010

1
2
3
4
5
6
7

Finger Print board + MP3 Module CONN.


1

For EMI

Kill Switch

D19
PSOT24C_SOT23
@

<20>
<20>

+3VS
T15 PAD

JP14

USB20_P5
USB20_N5

USB20_P5
USB20_N5

+3VS
6
5
4
3
2
1

FPR_SW
C169

C170

6
5
4
3
2
1

SW5
G2
G1

2
R269

8
7
<31>

KILL_SW#

1
10K_0402_5%

KILL_SW#

ACES_85202-0605L
1BS003-1211L_3P

0.1U_0402_16V4Z

ACES
Compal Secret Data

Security Classification

Issued Date

2005/10/06

Deciphered Date

2006/10/06

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

DC/DC Circuit
Size Document Number
Custom HEL80 LA-3161P
Date:

Thursday, February 23, 2006

Rev
0.2
Sheet

of

33

43

hexainf@hotmail.com

4.7U_0805_10V4Z
@ 2

T/P Board

USB Port

IOMP Board

+5VS

1
2
3
4
5
6

+USB_VCCA
U3

C203

1
2
3
4

GND
IN
IN
EN#

8
7
6
5

OUT
OUT
OUT
FLG

7
8
USB_OC#0

G528_SO8
0.1U_0402_16V4Z

1
R6

2
+3VALW
100K_0402_5%

D1
JP43

USB_OC#0 <20>

G1
G2

JP5
1
2
3
4
5
6

SWR#
SWL#

<35>
<35>

TP_CLK <31>
TP_DATA <31>

7
8

+5VS

ACES_85202-0605L

G1
G2

1
2
3
4
5
6

MODE_BTN#
VOL_UP#
VOL_DN#
STOP#

1
2
3
4
5
6

51ON#

MODE#

<31>

51ON#

<30,36>

DAN202U_SC70
IOMP@

ACES_85202-0605L

1
R5

2
+3VALW
100K_0402_5%

C190

VOL_UP# <31>

1000P_0402_50V7K
2 @

1
R8

2
+3VALW
100K_0402_5%

+USB_VCCA

VOL_DN# <31>

1000P_0402_50V7K
1
C194
150U_D_6.3VM

C168

C173
1
R7

2
+3VALW
100K_0402_5%

0.1U_0402_16V4Z

STOP#

<31>

JP44

5
6
7
8

GND1
GND2
GND3
GND4

+5VS

R543
+3VS

SUYIN_020173MR004G565ZR
ME@

10K_0402_5%

5
P

Q37
2N7002_SOT23-3

Q36
2N7002_SOT23-3

2
G

AMBER_LED#

+5VS
D7

8
7
6
5

R277

USB_OC#2

G528_SO8

R544

USB_OC#2 <20>

10K_0402_5%
C525

OUT
OUT
OUT
FLG

GND
IN
IN
EN#

1
2
3
4

C526

HT-110UD_1204

+USB_VCCB
U36

4.7U_0805_10V4Z

U20
NC7SZ08P5X_NL_SC70-5

D8
2

300_0402_5%

2
G

<27> BTON_LED#

<27> WIRELESS_LED#

+5VS

+5VS
R272

10P_0402_50V8K
1 @

C418

VCC
DD+
GND

C419

10P_0402_50V8K
@ 1

D20
PSOT24C_SOT23
@

<20> USB20_N0
<20> USB20_P0

1
2
3
4

1000P_0402_50V7K
2 @

2
G
Q39
2N7002_SOT23-3

<23> 3IN1_LED#

D7
2

HT-110UYG-CT_YEL/GRN
VALUE@

300_0402_5%

White LED

Q38
2N7002_SOT23-3

2
G

HIGH@

+5VS

D11
1

R275

R545
+3VS

<19>

SATA_LED#

SATA_LED# 1

U21
NC7SZ08P5X_NL_SC70-5

2
G
Q41
2N7002_SOT23-3

HT-110UYG-CT_YEL/GRN
VALUE@

HIGH@

+5VS
+5VALW

JP12

<31> PWR_LED#
<31>
EMAIL#
<31> USER_DEFINED#
<30> ON/OFFBTN#
<31> PROGRAM_BTN#
<31> INTERNET#
<31> SCROLL_LED#
<31> NUM_LED#
<31> CAPS_LED#

ON/OFFBTN#

1
2
3
4
5
6
7
8
9
10
11
12
13
14

1
2
3
4
5
6
7
8
9
10
11
12
13 G1
14 G2

<31> CHARGE_LED0#

R273

R274

2 300_0402_5%

CHARGE0

D10
2

2 300_0402_5%

CHARGE1

1
<31> CHARGE_LED1#

2/20 Modified
D9

HT-210UD/UYG_AMB/GRN
A

D9
15
16

<31> PWR_LED#

PWR_LED#

R276

2 300_0402_5%

HT-110UYG-CT_YEL/GRN
VALUE@

ACES_85202-1405L

Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

White LED

Q40
2N7002_SOT23-3

2
G
3

PIDE_LED# 2

5
+5VALW

PIDE_LED#

Switch Board CONN.

<22>

D11
2

300_0402_5%

10K_0402_5%

Title

White LED
HIGH@

Compal Electronics, Inc.


INDICATE LED

Size Document Number


Custom HEL80 LA-3161P
Date:

Rev
0.2
Sheet

Thursday, February 23, 2006


1

34

of

43

New Card Power Switch

New Card Socket (Left)


+3VALW_CARD1

CPUSB#
CPPE#
STBY#
SHDN#
SYSRST#
GND

OC#

23

RCLKEN
PERST#

22
9

C293

C273

10U_0805_10V4Z
2

<20>
<20>

C262

USB20_N6
USB20_P6

CP_USB#

0.1U_0402_16V4Z
<15,20,27> ICH_SMBCLK
<15,20,27> ICH_SMBDATA
+1.5VS_CARD1
<20,26,27> ICH_PCIE_WAKE#
+3VALW_CARD1

+3VS
RCLKEN1
PERST1#

+3VS

PERST1#

+3VS_CARD1

+3VS

CLKREQ1#
CP_PE#
1

R232
10K_0402_5%

R234
TPS2231PWPR_PWP24
CLKREQ1#

10K_0402_5%

+1.5VS

C271

10U_0805_10V4Z
2

+1.5VS_CARD1

2
2

D
3

1
C312

+3VALW

C253

10U_0805_10V4Z
2

+3VALW_CARD1

Q10
2N7002_SOT23
3

+3VS

C286

40mil

RCLKEN1 2
G

10U_0805_10V4Z
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z

11

16
17

40mil

C280

<15> CLK_PCIE_NC1#
<15> CLK_PCIE_NC1

C324
0.1U_0402_16V4Z

<20> PCIE_RXN4
<20> PCIE_RXP4

14
15
4
3
2

Aux_out
1.5Vout1
1.5Vout2

G Vcc

1.5Vin1
1.5Vin2

JP41

Imax = 0.75A

18
19

C274

10U_0805_10V4Z
2

+1.5VS_CARD1

Imax = 1.35A

3.3Vaux_in

+1.5VS

+3VS_CARD1

NC1
NC2
NC3
NC4
NC5

+3VALW

7
8

20

1
10
12
13
24

3.3Vout1
3.3Vout2

21

2 100K_0402_5% CP_USB#
2 100K_0402_5% CP_PE#
SUSP#
SYSON
PLT_RST#

R163 1
+3VALW
R168 1
<17,31,32,33,40,41> SUSP#
<31,33,40> SYSON
<7,17,18,20,22,26,27,31> PLT_RST#

3.3Vin1
3.3Vin2

60mils

5
6

+3VS_CARD1

Imax = 0.275A

U12
+3VS

<20> PCIE_TXN4
<20> PCIE_TXP4

CLKREQ_NC# <15>

U14
NC7SZ32P5X_NL_SC70-5

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND

27
28

GND
GND

FOXCONN 1CH4310C 26P P1 EXP_RVS

(NEW)

10U_0805_10V4Z
2

2005/11/4 Modified library pn:SP02000JC00


2005/12/9 Modified footprint to FOX_1CX43201_26P_LB

CIR

+3VALW
1

Update Part Number to SCR36236000


R270

RCIRRX

4
2

RCIRRX

<31>

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

D5
PSOT24C_SOT23
SWL#

<34>

SWR#

SWL#

SWR#

SWL#

Left switch

SMT1-05_4P
VALUE@

R520 1

XTALO
XTALI
TPM
SLB 9635 TT 1.1

14
13

TPM_XTALO
TPM_XTALI

LCLK
LFRAME#
LRESET#
SERIRQ
CLKRUN#
PP

GND
GND
GND
GND

GPIO2
GPIO

SW2
4

NC
NC
NC

SLB-9635-TT-1.2_TSSOP28
TPM@
C523
TPM@
18P_0402_50V8J
1
2

TPM_XTALI
R510
@ 10_0402_5%

NOT LEAD-FREE

12/9 Modified to @

1
3
12

@ ESD3

R521
4.7K_0402_5%
@

CLK_PCI_TPM

3
SMT1-05_4P
HIGH@

NOT LEAD-FREE

SUS_STAT# <20>
2 TPM@ 0_0402_5%

2
6

@ ESD4

28
9
8

4
11
18
25

6
5

21
22
16
27
15
7

LPCPD#
TESTB1/BADD
TEST1

LAD0
LAD1
LAD2
LAD3

SW3

6
5

Left switch
2

CLK_PCI_TPM
LPC_FRAME#
PLT_RST#
SIRQ
PCI_CLKRUN#

<15> CLK_PCI_TPM
<19,30,31> LPC_FRAME#
<7,17,18,20,22,26,27,31> PLT_RST#
<20,23,30,31> SIRQ
<20,31> PCI_CLKRUN#
1
2
+3VS
R522
TPM@ 4.7K_0402_5%

SWL#

26
23
20
17

R519 TPM@
10M_0402_5%
2
1

<34>

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

VDD
VDD
VDD
<19,30,31>
<19,30,31>
<19,30,31>
<19,30,31>

R524
4.7K_0402_5%
TPM@

Base I/O Address


0 = 02Eh
* 1 = 04Eh
1

U35
1000P_0402_50V7K
2 CIR@

C379

+3VS
1

OUT
GND

TSOP36236TR_4P
CIR@

VSB

Vs
GND

+3VS

24
19
10

2
1

4.7U_0805_10V4Z
2
CIR@

TPM 1.2

IR1
3
1

C380

+3VALW

CIR

100_0805_5%
CIR@

C518
@ 15P_0402_50V8J

X2
1

IN

NC

OUT

NC

TPM@ 32.768KHZ_12.5P_1TJS125DJ2A073

TPM_XTALO

SWR#

Right Switch

1
2

SWR#

Right Switch

SMT1-05_4P
VALUE@
@ ESD1

SW1
4

@ ESD2

Issued Date

NOT LEAD-FREE

Compal Secret Data

Security Classification

8
1

Note : TPM IC Lead free status is MN

3
SMT1-05_4P
HIGH@

NOT LEAD-FREE

2005/10/06

Deciphered Date

2006/10/06

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

New card
Size Document Number
Custom HEL80 LA-3161P
Date:

Thursday, February 23, 2006

Rev
0.2
Sheet

of

35

43

hexainf@hotmail.com

6
5

6
5

C524 TPM@
18P_0402_50V8J
SW4

BATT ONLY
Precharge detector
Min.
typ.
Max.
H-->L 6.138V 6.214V 6.359V
L-->H 7.196V 7.349V 7.505V

ACIN
Precharge detector
Min.
typ.
Max.
H-->L 14.589V 14.84V 15.243V
L-->H 15.562V 15.97V 16.388V

PJP1
@ JST_B5B-EH-A(LF)(SN)
1 1

PR2
1K_1206_5%
1
2

<20,31>
<31,38>

RTCVREF

ACOFF

<38>
PQ2
DTC115EUA_SC70

Vin Detector

PQ3
DTC115EUA_SC70

High 18.764 17.901 17.063


Low 17.745 16.9
16.03

3.3V

B+

PACIN

PR15
10K_0402_1%

PR16
10K_0402_1%
2
1

PU1A
LM393DG_SO8

PACIN

ACIN

1 2

1
PR9
10K_0402_1%
2

8
P

PC6
0.1U_0402_16V7K

PR11
0_0402_5%
1
2

PD3
RLZ4.3B_LL34

2
1
PR10
84.5K_0402_1%
1
PR14
20K_0402_1%
2

1
2

PC5
1000P_0402_50V7K

VS

PR12
22K_0402_1%
1
2

PR8
1K_1206_5%
1
2

VS

PR5
1M_0402_1%
1
2

VIN

PC131
0.01U_0402_25V7K
1
2

2
1
PR6
100K_0402_5%

2
PR175
10K_0402_1%
1
2

PR4
1K_1206_5%
1
2

VS

PQ1
TP0610K-T1-E3_SOT23

PR3
1K_1206_5%
1
2

1
PR13
100K_0402_5%

PD2
RLS4148_LLDS2
2
1

2
1
PR7
100K_0402_5%

12
1
PR1
PD1
10_1206_5%
RLZ24B_LL34

PC4
560P_0402_50V7K

PC3
100P_0402_50V8J

ADPIN

PL17
FBMA-L18-453215-900LMA90T_1812
1
2
PC2
100P_0402_50V8J

VIN

PC1
560P_0402_50V7K

PR17
2.2M_0402_5%
2
1

VL

2
1
PR18
499K_0402_1%

(6A,240mils ,Via NO.= 12)


1

+0.9VSP

PJ4
PAD-OPEN 3x3m
2

PQ5
RHU002N06_SOT323

2
G

(5A,200mils ,Via NO.= 10)


4

+3VALWP

PJ6
PAD-OPEN 3x3m
2

+3VALW

PC7
0.01U_0402_25V7K

PACIN <38>

+5VALWP

@
+0.9VS

PR29
47K_0402_5%
1

2
1
PR25
499K_0402_1%

1
PR24
191K_0402_1%

PRG++ 2

2
PR28
34K_0402_1%
2
1

PU1B
LM393DG_SO8

6
PC9
1000P_0402_50V7K

O
4

1
2

1
2

RTCVREF

1
3

PQ6
DTC115EUA_SC70

+5VALW

ACON

PR30
66.5K_0402_1%

PJ3
PAD-OPEN 3x3m
1
2

+1.8VP

<38>

+1.5VS

PR27
22K_0402_1%
1
2
<30,34> 51ON#
PJ2 PAD-OPEN 3x3m
1
2
+1.8V

PC12
0.22U_1206_25V7K

(6A,240mils ,Via NO.=12)

+5VALWP

GND

CHGRTCP

PD6
RB715F_SOT323

<37,39> MAINPWON

PJ1
PAD-OPEN 3x3m
1
2

IN

OUT

PQ4
TP0610K-T1-E3_SOT23

PC10
1U_0805_25V4Z

1
2

+1.5VSP

3
PC11
4.7U_0805_6.3V6K

+CHGRTC

PR23
200_0805_5%
2
1

2
1
PR26
100K_0402_5%

PU2
G920AT24U_SOT89

PR22
PR21
560_0603_5%
560_0603_5%
1
2 1
2

VS

2
1
PR19
100K_0402_1%

RTCVREF

PC8
0.1U_0603_25V7K

PD5
RB751V-40TE17_SOD323-2
2
1

VS

PC13
0.1U_0603_25V7K

BATT+

3.3V

1
PR267
68_1206_5%
2
1 1
2
PR20
PD4
68_1206_5%
RLS4148_LLDS2

VIN

(0.3A,40mils ,Via NO.= 2)

+2.5VSP

PJ11
PAD-OPEN 3x3m
2

PJ8
PAD-OPEN 3x3m
2
+VSB

+2.5VS

(4.5A,180mils ,Via NO.= 9)

+1.05VSP

PJ7
PAD-OPEN 3x3m
2

+VCCP

(5A,200mils ,Via NO.= 10)


A

+VSBP

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2005/10/17

Deciphered Date

2006/10/17

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

(0.3A,40mils ,Via NO.= 2)


B

Title

DCIN/DECTOR
Size
B
Date:

Document Number

Rev
0.2

Thursday, February 23, 2006


D

Sheet

36

of

43

1
2
PR32
150K_0402_1%

MAINPWON <36,39>

PR40
150K_0402_1%

1
2

PC19
1U_0603_6.3V6M

PU3A
LM393DG_SO8

VS

8
+

O
4

1
2
2

1
2

PC20
0.22U_1206_25V7K

VL

2
1
PR41
100K_0402_5%

PR42
22K_0402_1%
1
2

PU3B
LM393DG_SO8

PR44
0_0402_5%
2

S PQ8
RHU002N06_SOT323

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2005/10/17

Deciphered Date

2006/10/17

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

BATTERY CONN. / OTP


Size
B
Date:

Document Number

Rev
0.1

Thursday, February 23, 2006


D

Sheet

37

of

43

hexainf@hotmail.com

2
G
PC22
0.1U_0402_16V7K

1
2
PR43
100K_0402_5%

+VSBP

1
PC21
0.1U_0603_25V7K

B+

BATT_TEMP <31>

PQ7
TP0610K-T1-E3_SOT23

SPOK

PR39
2 150K_0402_1%
1
VL

1
PR38
1K_0402_1%

1
+3VALWP

PH1
100K_0603_1%_TH11-4H104FT

1
2
2
PR36
6.49K_0402_1%

PC18
1000P_0402_50V7K

<39>

1
PR35
100_0402_1%
2

2
1
PR31
100_0402_1%

TM_REF1

EC_SMB_DA1 <31,32>

PR34
1 442K_0603_1%
2

PR37
161.9K_0603_1%
2

EC_SMB_CK1 <31,32>

VL

VL

VS

2
1
PR33
10.7K_0402_1%

PR176
1K_0402_1%

PH1 under CPU botten side :


CPU thermal protection at 85 degree C
Recovery at 70 degree C

PC16
0.01U_0603_50V7K

PR268
0_0402_5%
1
2

@ 100K_0402_5%

@ PR178
100K_0402_5%

+3VALWP

PC15
1000P_0603_50V7K

PR177

BATT+

+3VALWP

CNT1
CNT2
EC_SMCA
EC_SMDA
TS_A
GND

PC14
1000P_0603_50V7K

PJ13
PAD-OPEN 3x3m
2

BATT++

1
2
3
4
5
6
7
8
9
10
11

1
2
3
4
5
6
7
8
9
G1
G2

PJP2
SUYIN_200275MR009G180ZR

PC17
0.1U_0603_25V7K

BATT++

4
1

OUT

20

VREF

VH

19

ACIN XACOK

18

-INE1

RT

17

+INE1

5
6
7
8

CTL

14

12

-INC1

+INC1

13

LXCHRG

3
2

1
PR64
47K_0402_5%

1
PR65
0_0402_5%

PC39
0.01U_0402_25V7K

PC40
10P_0402_50V8J
1
2

BATT+

BATT+

SEL

PC35
1500P_0603_50V7K
21
2

PR56
0.02_2512_1%
1
4

2
11

PR62
33K_0402_1%
MB39A126 1

PD11
EC31QS04

15

ACOFF <31,36>

PQ14
DTC115EUA_SC70

16

OUTC1 FB123

PL5
10U_LF919AS-100M-P3_4.5A_20%
1
2
PD10
EC31QS04

1
PR59
47K_0402_5%

-INE3

10

VIN

PR58
47K_0402_1%
1
2

ACOFF

PC32
0.1U_0603_25V7K
1
2

ACOK

ACOFF#

21

PQ13
AO4407_SO8

PC38
4.7U_1206_25V6K

VCC

PC29
0.22U_0603_16V7K
1
2
PC30
0.1U_0603_25V7K
1
2

CS

-INE2

CS

PC37
4.7U_1206_25V6K

+INE2

22

23

OUTC2

PC36
4.7U_1206_25V6K

GND

VIN

2
PR50
10K_0402_1%

PC26
2200P_0402_50V7K

1
2

PR48
47K_0402_1%
1
2

3
2
1

PC25
0.1U_0603_25V7K

PC24
4.7U_1206_25V6K

8
7
6
5

1
2

PC33
0.22U_0603_16V7K
1

PR66
22K_0402_1%
1
2

ACON

PR67
47K_0402_5%

+3VALWP
PC41
47P_0402_50V8J
1
2

CS
1

IREF=0.932*Icharge
IREF=0.466~2.8V
3

LI-3S :13.5V----BATT-OVP=1.5V
BATT-OVP=0.111*BATT+

PQ18
DTC115EUA_SC70

(100K/(100K+133K))*2.8V=1.2V
1.2/(20*0.02)=3A

PU12A
3

0
4

LM358ADR_SO8

2005/10/17

Compal Electronics, Inc.


2006/10/17

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Charge voltage
3S CC-CV MODE : 12.6V
SEL is L

Compal Secret Data

Security Classification
Issued Date

PC43
0.01U_0402_25V7K

4
8
P
1

LM358ADR_SO8

1.292V/(15*0.02)=4.3A

0
G

CP Point=4.3A
5V*(10K/(28.7k+10k))=1.292V

1
2
8
P

<31> BATT_OVP

PU12B
+ 5

2
1
2
1
PR69
PR68
499K_0402_1% 340K_0402_1%

VS

PQ19
DTC115EUA_SC70

VS

CC=3A

BATT+

2
1
PR72
105K_0402_1%

FSTCHG

<31>

PC42
0.01U_0402_25V7K

<36>

CHG_B+

2
1
PR53
10K_0402_1%
2
1
PR54
28.7K_0402_1%

PD12
RLS4148_LLDS2
2

PACIN

PR61
10K_0402_1%
2
1

S PQ17
RHU002N06_SOT323

2
G

<36>

PR57
PC34
1K_0402_1% 2200P_0402_50V7K
2
1
2

MB39A1261

PR60
133K_0402_1%
<31>
1
2

IREF
D

2
1
PR63
100K_0402_1%

PQ16
RHU002N06_SOT323

PR52
100K_0402_1%
2
1

PU4
MB39A126PFV-ER_SSOP24
1 -INC2 +INC2 24

PC31
0.01U_0402_25V7K

2
1
PR55
150K_0402_1%
2

2
G

ACOFF#

PC28
4700P_0402_25V7K
1
2

1
3
1
3

PQ15
DTC115EUA_SC70

PL18
FBMA-L18-453215-900LMA90T_1812
1
2

4
PR51
10K_0402_1%
1
2

47K

P2

MB39A126

1
PR49
0_0603_5%

PQ11
AO4407_SO8
1
2
3

PQ12
DTA144EUA_SC70
47K

P3

8
7
6
5

2
1
PR47
47K_0402_5%

1
2
3

Charger

B+

1
2
3
PC27
0.1U_0603_25V7K
2
1
PR46
200K_0402_1%

8
7
6
5

VIN

Fosc=14100/Rt=14100/47=300KHz

PR45
0.015_2512_1%

PQ10
AO4407_SO8

PQ9
AO4407_SO8

P2

PR54=23.7K_0402_1% Iadp=0~3.71A
PR54=28.7K_0402_1% Iadp=0~4.3A

PR45=0.02_2512_1%
PR45=0.15_2512_1%

PC23
4.7U_1206_25V6K

75W
90W

Title

PWR-Charger
Size
B
Date:

Document Number

Rev
0.1
Sheet

Thursday, February 23, 2006


E

38

of

43

B+

BST5B

PD13

PC45
0.1U_0603_25V7K
1
2

PL19
FBMA-L18-453215-900LMA90T_1812
PC46
0.1U_0603_25V7K
1
2

BST3B

B+++

B+++

PQ21
SI4800BDY-T1-E3_SO8

PQ20
SI4800BDY-T1-E3_SO8

5
6
7
8
D
D
D
D

PQ30
SI4810BDY-T1-E3_SO8

5
6
7
8
D
D
D
D
G
S
S
S

1
2
PL8
4.7UH_PCMC063T-4R7MN_5.5A_20%

LDO3

4
3
2
1

2
PR82
0_0603_5%
1
DH3

7
2

SPOK

1
+

+3VALWP

PC58
150U_V_6.3VM_R18

<37>

G
S
S
S
4
3
2
1

PC51
10U_1206_25VAK

1
2
2
PR79
0_0603_5%
1
2
1
2
PR84
PR81
499K_0402_1% 200K_0402_1%

1
2
17
VCC

DL3

PRO#

TON

1
2 1
2
PR83
PR80
499K_0402_1% 200K_0402_1%

11
28
26
24
27
22

1
2

PC49
0.1U_0402_16V7K

2
1
PR77
4.7_1206_5%
1
2
PR75
47_0402_5%
2
13

20

LD05

BST3A

2
1
2
PR93
PR90
0_0402_5% @ 3.57K_0402_1%

PC59
0.22U_0603_16V7K

2
1
2

ILIM3

3HG
LX3

PC61
0.047U_0603_16V7K

1
2

PC57
0.047U_0603_16V7K

REF

25

12

6
4
3

PR89
10_0402_5%2

PR94
47K_0402_5%
1
2

18

LX5
DL5
ILIM5
OUT5
PU6
FB5
BST3
N.C.MAX8734AEEI+_QSOP28 DH3
DL3
SHDN#
LX3
ON5
OUT3
ON3
FB3
SKIP#
PGOOD

V+

15
19
21
9
1

2VREF_19998

PZD1
PR88
RLZ5.1B_LL34
47K_0402_5%
1
2 1
2

1
2
PR91
100K_0402_5%

2
PR86
0_0402_5%

DH5

PC60
10
14.7U_0805_6.3V6K
2
PR92
0_0402_5%

BST5

16

VS

14

GND

BST5A

2VREF_1999
PC53
1U_0805_16V7K

2
PC54
4.7U_0805_6.3V6K
2
1

DL5

1 PC55
0.1U_0603_25V7K

PC52
1U_0805_25V4Z

PQ29
SI4810BDY-T1-E3_SO8

8
7
6
5
D
D
D
D
S
S
S
G
1
2
3
4

+5V Ipeak = 6.66A ~ 10A

VL

1
2
PR85
10.2K_0402_1%

2
PR87
0_0402_5%

PC56
150U_V_6.3VM_R18

+5VALWP

1
2
PL7
4.7UH_PCMC063T-4R7MN_5.5A_20%

PR76
4.7_1206_5%

DH5
LX5

23

PR78
0_0603_5%
2

PC50
2200P_0402_50V7K

2
PR74
0_0603_5%

B+++

5HG

VL

CHP202UPT_SOT323-3

8
7
6
5
D
D
D
D
S
S
S
G
1
2
3
4

PC48
1

10U_1206_25VAK

PC47
2200P_0402_50V7K
2
1

+3.3V Ipeak = 6.66A ~ 10A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2005/10/17

Deciphered Date

2006/10/17

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

+5VALWP/+3VALWP
Size Document Number
Custom
Date:

Rev
0.1

Thursday, February 23, 2006


D

Sheet

39

of

43

hexainf@hotmail.com

1
2

PC62
1U_0603_6.3V6M

MAINPWON <36,37>

OZ813_B+

1
PR95
51_0402_1%

1
2

PC69
22P_0402_50V8J

1.8VS2N

OCP=6A

PC70
4700P_0402_25V7K

1.8VS2P

PC185
PR274
680P_0603_50V7K
4.7_1206_5%
2
1
2
1

PQ23
SI4810BDY-T1-E3_SO8

D
D
D
D
G
S
S
S

OZ813_B+

1
2

PC81
22P_0402_50V8J

1.05VS1N

+
2

OCP=6A

PC82
4700P_0402_25V7K

PR109
2
PC8029.4K_0402_1%
5600P_0402_50V7K
2
1

+1.05VSP
1

PC78
220U_D2_4VM_R15

PR107
51_0402_1%

1.05VS1P

PR108
100K_0402_1%
1
2 1

PC79
10U_1206_25VAK

PL11
3.3UH_MPL73-3R3_6A_20% 28mohm
1
2

PQ31
SI4810BDY-T1-E3_SO8

4
3
2
1

G
S
S
S

D
D
D
D

5
6
7
8

PC132
@ 0.1U_0402_16V7K

PC186
PR275
680P_0603_50V7K
4.7_1206_5%
2
1
2
1

1
2

PC156
2.2U_0603_6.3V6K

1
2

+3VALWP

PQ24
SI4800BDY-T1-E3_SO8

5
6
7
8
D
D
D
D
G
S
S
S
4
3
2
1

PR273
0_0603_5%
DH_1.05V-2
1
2

DL_1.05V

2
PR263
0_0402_5%
1

4
3
2
1
2

VSET1
CS1N
CS1P
PGD1
LX1
HDR1

DH_1.05V-1

2
1
PR264
1K_0402_1%
1

+1.8VP
1

PR98
1
2
22K_0402_1%
PC68
6800P_0402_25V7K
1
2

+5VALWP

RB751V-40TE17_SOD323-2
PC76
0.1U_0603_25V7K

PC71
1U_0805_16V7K

LX1.05V

1.05VS1N

PR179
0_0402_5%
1
2

28mohm

PD17

1.05VS1P

PC77
1000P_0402_50V7K

PR97
100K_0402_1%
1
2

+5VALWP

BST_1.05V1

7
8
9
10
11
12
@

2
2

18
17
16
15
14
13

1
B

<17,31,32,33,35,41> SUSP#

RB751V-40TE17_SOD323-2
PD16
BST_1.8V
1
2

OZ813LN_QFN24

1.05SET

DL_1.8V

1
BST2
LDR2
VDDP
GDNP
LDR1
BST1

1.8VSET

PR106
150K_0402_1%
PR172
61.9K_0402_1%

24
23
22
21
20
19

25
GNDA

VSET2
CS2N
CS2P
PGD2
LX2
HDR2

ON/SKIP2
VIN
VREF
TSET
VDDA
ON/SKIP1

PC67
0.1U_0603_25V7K

2
PC75
0.01U_0402_25V7K

1
2

1
2

PC74
1U_0603_6.3V6M

2
PR104
100K_0402_1%

PR105
75K_0402_1%
1

PC73

1
2
3
4
5
6

DREF

0.1U_0603_25V7K
2
1

PC72
0.022U_0402_16V7K
2
1

PR103
24K_0402_1%
1
2

PR101
0_0402_5%
2
1

PR100
1K_0402_1%
1
2

PU7

5
6
7
8

LX_1.8V

PC65
1000P_0402_50V7K

PR99
22_0402_1%
1
2

1
2
C

PC184
0.01U_0402_25V7K

<31,33,35> SYSON

1.8VSET

PL10
3.3UH_MPL73-3R3_6A_20%
1
2

DH_1.8V-2

+5VALWP
PR266
0_0402_5%
2
1

B+

PC66
220U_D2_4VM_R15

PR262
@ 0_0402_5%
@
1
2
PR272
0_0603_5%
DH_1.8V-1
1
2

1.8VS2N
1.8VS2P

1
PR261
1K_0402_1%

SI4800BDY-T1-E3_SO8
PQ22
4 G
D 5
3 S
D 6
2 S
D 7
1 S
D 8

+3VALWP

PC63
10U_1206_25VAK

PL20
FBMA-L18-453215-900LMA90T_1812
1
2

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2005/10/17

2006/10/17

Deciphered Date

1.05VP/1.8VP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Size Document Number


Custom
Date:

Rev
0.1

Thursday, February 23, 2006

Sheet
1

40

of

43

PJ17
PAD-OPEN 3x3m
2

B+

PC83
10U_1206_25VAK

PHASE_VCCPP
PR265
10K_0402_1%
1
2

UG_VCCPP-1
PR110
1

0_0603_5%

PC85 0.1U_0402_16V7K

PVCC

12

PQ26

G
S
S
S

PR1122 6269_VCC
4.7_0603_5%
2 PC86

SI4800BDY-T1-E3_SO8

4
3
2
1

BOOT

D
D
D
D

13

14
UG

PHASE

VIN

PGOOD

GND
1

15

PU8

16

17

PR111
@4.7_0603_5%

5
6
7
8

1PR269
2
0_0603_5%

+5VS
BOOT_VCCPP

2.2U_0603_6.3V6K
UG_VCCPP-2

FCCM

EN

PGND

10

ISEN

OCP=6A

LG_VCCPP
PL13

G
S
S
S
4
3
2
1

VO

FSET

PC88
220U_D2_4VM_R15

ISL6269CRZ-T_QFN16

FB

PQ27
SI4810BDY-T1-E3_SO8

PR117
2

1
1

PR116
49.9K_0402_1%

22P_0402_50V8J

PC91

COMP

PC89
0.01U_0402_25V7K

ISEN_VCCPP
1
2
PR115
8.66K_0402_1%

+1.5VSP
1

D
D
D
D

0_0402_5%

1
2

LG

11

1
2
3.3UH_MPL73-3R3_6A_20%

PR113
2

2
47K_0402_5%

VCC

<17,31,32,33,35,40> SUSP#

PR114

PC87
2.2U_0603_6.3V6K

5
6
7
8

6269_VCC

PC90
0.01U_0402_25V7K

57.6K_0402_1%
PC92
6800P_0402_25V7K
PR118
1

4.53K_0402_1%
PR119
3K_0402_1%

+1.8VP
B

+3VS

2
2

PU9

FB

VIN

VREF

NC

VOUT

NC

TP

PR120
1K_0402_1%

1
2

PR124
PC101
1K_0402_1% 0.1U_0402_16V7K

PC103
@ 0.1U_0402_16V7K

+0.9VSP
1

2
G

RHU002N06_SOT323
PQ28 D

0_0402_5%
1
2

SUSP

<33>

PC98
@ 150U_D_6.3VM

APL5331KAC-TRL_SO8

0.01U_0402_25V7K

+
2

PR123

PC95
1U_0603_6.3V6M

PC102
22U_1206_6.3V6M

1
2

2
APL5912-KAC-TRL_SO8

22U_1206_6.3V6M

PC99

PC97
2

1
PR122
2.15K_0402_1%

EN

+3VALWP

NC

+2.5VSP
1

PR125
1K_0402_1%

VCNTL

GND

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2005/10/17

2006/10/17

Deciphered Date

+VCCPP/+2.5VSP/0.9VSP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Size Document Number


Custom
Date:

Rev
0.1

Thursday, February 23, 2006

Sheet
1

41

of

43

hexainf@hotmail.com

VOUT

PC94
22U_1206_6.3V6M

PC96
22U_1206_6.3V6M

6
VOUT

1
2

PC100
0.01U_0402_25V7K

GND

33K_0402_1%
1
2
1

,31,32,33,35,40> SUSP#

VIN

PR121

VIN

POK

VCNTL

PU10
7

1U_0603_6.3V6M

PJ9
JUMP_43X118

PC93

PJ10
JUMP_43X79

+5VS

+5VS

CPU_B+

B+

33

D2

LX1

28

LX1__CPU

34

D3

DL1

26

DL1__CPU

<5>

CPU_VID4

35

D4

PGND1

27

<5>

CPU_VID5

36

D5

GND

18

<5>

CPU_VID6

37

D6

CSP1

17

71.5K_0402_1%
1
7

TIME

CSN1

16

CSN1_CPU

CCV

FB

12

FB_CPU

REF

CCI

10

C CI_CPU

DPRSLPVR

DH2

21

DH2_CPU-1

BST2

20

BST2_CPU

LX2

22

LX2_CPU

DL2

24

DL2__CPU

PGND2

23

<7,20> DPRSLPVR

<4,19> H_DPRSTP#

40

PSI

PWRGD

CLKEN

DPRSTP

CSN2__CPU

POUT

GNDS

13

2
PR251
100_0402_5%

0_0402_5%
1
2

<5>

VSSENSE

VSSENSE

PQ34
AO4410_SO8

PR246
3K_0603_1%

100_0402_5%

PC173
470P_0402_50V8J

29.6

CPU_B+

PQ35
SI7840DP-T1-E3_SO8

PC181
0.1U_0402_16V7K

3
2
1

PR254 10K_0402_5%
2

PR257
2.1K_0402_1%

2
1

3
2
1

DL2__CPU

3
2
1

PL16
P_0.36H_ETQP4LR36WFC_24A_20%

5
6
7
8
5
6
7
8

PQ36
AO4410_SO8

PQ37
AO4410_SO8

PR258
3.48K_0402_1%
1
2

NTC
1

2005/10/17

Issued Date

Deciphered Date

0.22U_0603_16V7K

Compal Electronics, Inc.


2006/10/17

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

PC183

Compal Secret Data

Security Classification

PH3
2

10KB_0603_5%_ERTJ1VR103J

1
PR260 0_0402_5%
1
2

PC163
2200P_0402_50V7K
2
1

PC162
0.1U_0603_25V7K
2
1

PC161
10U_1206_25VAK
2
1

PC160
10U_1206_25VAK
2
1

PR243

PC172
4700P_0402_25V7K

2.2_0603_5%
PR271
1
2 DH2_CPU-2

PR255
10_0402_5%

POUT
2

<31>

PC171 0.022U_0402_16V7K
CPU_VCC_SENSE
1
2

PR248
20K_0402_1%

<4> H_PROCHOT#

VCCSENSE

<BOM Structure>
1
2

2.61K_0402_1%
2

NTC PR245
@ 3K_0603_1%

@ PR252
56_0402_5%
PR253

BSTM2_CPU

+3VS

PR250
@ 10K_0402_5%

0.22U_0603_16V7K

PR235
100_0402_5%

PR242
1

PC175
2
1

PC174
1000P_0402_50V7K

PR249
0_0402_5%

MAX8770GTL+_TQFN40

PH2 NTC
2

10KB_0603_5%_ERTJ1VR103J<5>
1
2

PC169

PR238 3K_0603_1%
1
2

2
0_0402_5%
@ PR247
1
2
1

PR239

15

3.48K_0402_1%
PR230
2
1

PR237 0_0402_5%
1
2

CSN2

VR_ON

14

VRHOT

<31>

CSP2

38

PR241
@ 2K_0402_1%
1

1
<15> CLK_ENABLE#

SHDN

CSP2_CPU

<15,20,31> VGATE

2
PR240
10K_0402_1%

PR244
0_0402_5%

PR256
4.7_1206_5%

0_0402_5%

H_PSI#
+3VS

<5>

CSP1__CPU

11

0.22U_0603_16V7K 39

PQ33
AO4410_SO8

+CPU_CORE

CPU_VID3

PC180
2200P_0402_50V7K
2
1

CPU_VID2

<5>

10_0402_5%
1

<5>

1
PC168
2

PC187
680P_0402_50V7K

+CPU_CORE
PL15
P_0.36H_ETQP4LR36WFC_24A_20%
2
1

@ PR229
2

DH1__CPU-1

PC179
0.1U_0603_25V7K
2
1

29

PC178
10U_1206_25VAK
2
1

DH1

PC177
10U_1206_25VAK
2
1

D1

PC176
10U_1206_25VAK
2
1

32

PC167
680P_0603_50V7K 2.1K_0402_1%
PR226
1
2

CPU_VID1

PR224
4.7_1206_5%
2
1

<5>

0.22U_0603_16V7K
PC166
BSTM1_CPU 1
2

PR236

BST1_CPU 1

3
2
1

30

5
6
7
8

BST1

5
6
7
8

D0

PC170

PC159
10U_1206_25VAK
2
1

31

PC182
680P_0603_50V7K

0_0402_5%

200K_0402_5%
2 PR216 1

PR234

470P_0402_50V8J
1
499_0402_1%

0_0603_5%
PR220
2

CPU_VID0

PR2322

PR233

<5>

3
2
1

PR228 0_0402_5%

TON

PR227 0_0402_5%

VDD

THRM

DL1__CPU

PR225 0_0402_5%

25

Vcc

3
2
1

PR223 0_0402_5%

+
2

2.2_0603_5%
PR270
1
2DH1_CPU-2
4

0_0603_5%

PR222 0_0402_5%

19

0.22U_0603_16V7K

PR221 0_0402_5%

V CC

PQ32
SI7840DP-T1-E3_SO8

PU11

NTC
100K_0402_5%
PR218
1
2
PR219 0_0402_5%

PC165
1U_0603_6.3V6M

PR217
13K_0402_5%

2
2

PC164
2.2U_0603_6.3V6K

PC157
0.01U_0402_25V7K

0_1206_5%
PR215
10_0402_5%

PL14
FBMA-L18-453215-900LMA90T_1812
1
2

PC158
100U_25V_M

PR214
5VS12

Title

+CPU_CORE
Size Document Number
Custom
Date:

R ev
0.1

Thursday, February 23, 2006

Sheet
1

42

of

43

CF10
1

CF13
1

CF11
1

CF12
1

FM3
1

CF3
1

CF6
1

FM1
1

H1
HOLEA

CF7
1

CF2
1

CF1
1

CF4

CF5

CF9

CF14
1

FM4
1

H2
HOLEA

CF8
1

FM2
1

H3
HOLEA

H4
HOLEA

H5
HOLEA

H6
HOLEA

H7
HOLEA

H8
HOLEA

H9
HOLEA

H10
HOLEA

H16
HOLEA

H27
HOLEA

H26
HOLEA

H20
HOLEA

H19
HOLEA

H25
HOLEA

H18
HOLEA

H17
HOLEA

H24
HOLEA

H15
HOLEA

H23
HOLEA

H22
HOLEA

H14
HOLEA

H13
HOLEA

H21
HOLEA

H12
HOLEA

H11
HOLEA

2/13 Modified

H34
HOLEA

H33
HOLEA

H32
HOLEA

H31
HOLEA

H30
HOLEA

H29
HOLEA

H28
HOLEA

2005/10/17

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/10/17

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Holes
Size Document Number
Custom
Date:

Rev
0.1

Thursday, February 23, 2006

Sheet
1

43

of

43

hexainf@hotmail.com

2/13 New added

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