&

: H 312

2012
2
Datapath

:
1.
.
2. .
3. .
4. (ALU).
5. (MEM).

non-pipelined

CHARIS-2 (CHAnia Risc
Instruction Set, 2) :
1. 32 32 bits. R0 .
2. 32 bit , DLX
.
3. R-type: add, sub, or, and, not, jr.
4. I-type: addi, ori, andi, lw, sw, beqz, bnez.
5. J-type: j, jr.
format R-type :
6-bit

5-bit

5-bit

5-bit

5-bit

6-bit

Opcode

Rs

rt

Rd

not-used

funct

 format I-type :
6-bit

5-bit

5-bit

16-bit

opcode

rs

rt

Immediate

format J-type :
6-bit

26-bit

opcode

Disp

byte,
( lw sw)
4 bytes.
:
Opcode

FUNC

110000

001011

add

RF[rd] RF[rs] + RF[rt]

110000

001111

sub

RF[rd] RF[rs] - RF[rt]

110000

000110

and

RF[rd] RF[rs] & RF[rt]

110000

000001

not

RF[rd] ! RF[rs]

110000

000111

or

RF[rd] RF[rs] | RF[rt]

110000

001000

shr

RF[rd] RF[rs] >>1

110000

001101

shl

RF[rd] RF[rs] <<1

110000

100000

jr

PC RF[rs] ( rt = 0)

011000

PC disp << 2

000011

addi

RF[rt] RF[rs] + SignExtend(Imm)

000111

andi

RF[rt] RF[rs] & ZeroFill(Imm)

001111

ori

RF[rt] RF[rs] | ZeroFill(Imm)

011111

beqz

if (RF[rs] == 0)
PC PC + 4 + (SignExtend(Imm) << 2)
else PC PC + 4

111111

bneq

100001

lw

if (RF[rs] != 0)
PC PC + 4 + (SignExtend(Imm) << 2)
else PC PC + 4
RF[rt] MEM[RF[rs] + SignExtend(Imm)]

100011

sw

MEM[RF[rs] + SignExtend(Imm)] RF[rt]

: nop add, R0, R0, R0 mov

add, Rd, Rs, R0.

. CHARIS
. ,
:
.
ALU ,
Register File, Immediate ,
..

.
.
. (IF)
1024x32
Wizard Xilinx ROM
1024 32 bits. .
: ,
. :

Addr

10 bit

Dout

32 bit

Clk

1bit

 : Project
IP (Coregen & Architecture Wizard) MEM1024x32
, NEXT Memories & Storage elements

RAMs & ROMs
Block Memory Generator NEXT Finish.
NEXT Single Port ROM.
Generate.

B1.
,
.
:
1. PC (32 bit)
2.
3. ( /incrementor 4)
PC + 4
4. (PC + 4) +Immediate
branch
5. 4 1 4 (PC+4,
PC+4+Immediate, Displacement, Register) PC.
:

PC_Immed

32 bit

Immediate beqz, bnez

PC_Disp

32 bit

Displacement j

PC_Reg

32 bit

Reg jr (RF[rs])

PC_sel

2 bit

PC:
0 PC+4,
1 PC+4 + Immediate,
2 Displacement,
3 Register

PC_LdEn
Instr

1 bit
32 bit

PC

Reset

1 bit

Reset PC

Clk

1 bit


1.

2. VHDL

,
, , .
IFSTAGE.vhd
3. .
mem1024x32.coe

PC.
PC_Reg
PC_Disp
PC_Immed

MUX

+4

PC_Sel

PC_LdEn

PC

Clk

IMEM

Instr

Reset

1: .
. (DECODE)
1
,
.
:
1.
2. 2 1 2
(rt rd)

3. 2 1 2
(ALU MEM)
4. 16 bits immediate
32 bits
immediate 2 , zero-filling signextension immediate 32 bit.

Instr
RF_WrAddr_sel

32 bit
1 bit

:
0 rt
1 rd

RF_WrEn

1 bit

ALU_out

32 bit

ALU

MEM_out

32 bit

RF_WrData_sel

1 bit

:
0 ALU
1 MEM

RF_A

32 bit

RF A EXSTAGE IFSTAGE

RF_B

32 bit

RF B EXSTAGE MEMSTAGE

Immed

32 bit

Immediate IFSTAGE EXSTAGE

Clk

1 bit

1.

2. r0 0 ().
;

3. VHDL

Register File
, , , .
: DECSTAGE.vhd
4.
.

.
Read
register1

Instr(25-21)
Instr(20-16)

Read
register2

Instr

Read
data1

RF

Write
register

Instr(15-11)

Read
data2

RF_A

RF_B

Write data
Instr(15-0)
16 bit

MUX

ALU_out
32 bit

MEM_out
RF_ WrData_sel

Instr(25-0)

Immed

RF_ WrAddr_sel

PC_Disp

2: .

. (ALU)
ALU 1 ,
.
:
1. ALU
2. ALU
(RF(B) Immediate).
(ALU) :

RF_A

32 bit

RF[rs] ALU(A)

RF_B

32 bit

RF[rt]

Immed

32 bit

Immediate

ALU_Bin_sel

1 bit

E B ALU RF_B Immediate

ALU_func

4 bit

ALU

ALU_out

32 bit

ALU ( MEM WB)

1.

2. VHDL

,
, , .
:ALUSTAGE.vhd
3.
.

Immed

ALU_Bin_sel

ALU_out

MUX

RF_B

ALU

RF_A

ALU_func

3: .
. (MEM)
Wizard Xilinx RAM
(Block Memory Generator) 1024 32 bits.
. :
/, ,
.

clk

1 bit

Mem_WrEn

1 bit

Mem_RdEn

1 bit

----

ALU_out_to_MEM_addr

32 bit

ALU ( MEM_AddrIn)

RF_B_to_MEM_in

32 bit

RF[rt]
sw ( _DataIn)

MEM_ out

32 bit

lw (
_DataOut)

1.

2. VHDL
.
C:\HRY312\MEMSTAGE.vhd
3. .
mem1024x32.coe
.

MEM_AddrIn

MEM

MEM_DataOut

MEM_DataIn

MEM_WrEn

4: .


1. VHDL ().
2. datapath
.
3. ( ).
4. datapath
- .
5. (

).
/

modules
.
:
Project.

4 Load Init File
Browse

.coe, .
, Generate
.