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Kapoor Three State Registers Three state register consists of a three state switch. Three state switch has 3 o/p states -- low, high and open ( high impedance). When the device is in Hi-Z condition the connection before & after the device is electrically disconnected A tri-state device has 3 lines input ,output & ENABLE. When Enable is activated the tri-state device functions the same way as ordinary logic device. Active high Enable (normally open switch) -- The truth table is as shown. When ENABLE = low, Dout = Hi-Z. Thus when ENABLE is high, circuit acts like a inverting buffer because Dout = Symbol Enable 0 1 1 Din X 0 1 Dout Hi-Z 1 0

Din

Dout

ENABLE Active low Enable ( Switch is closed when Enable = low) (normally closed switch) Din Dout Enable 1 0 0 Din X 0 1 Dout Hi-Z 1 0

ENABLE Buffer A Digital Buffer is single input device that does no invert or perform any type of logical operation on its input signal as its output exactly matches that of its input signal. In other words, its Output equals its Input. Boolean expression of: Q = A. Symbol Truth Table A Q 0 0

1 1 A Tri-state Buffer You might think that a buffer is useless. After all, the output is exactly the same as the input. What's the point of such a gate? The answer is a practical issue from real circuits. As you may know, logic gates process 0's and 1's. 0's and 1's are really electric current at certain voltages. If there isn't enough current, it's hard to measure the voltage. The current can decrease if the fan out is large. Here's an example:

The "fan out" is the number of devices that an output is attached to. Thus, the AND gate above is attached to the inputs of four other devices. It has a fan out of 4. If the current coming out of the AND gate is i, then assuming each of the four devices gets equal current, then each device gets i / 4 of the current.

T.Y. E.I. /2 / 1 Tri State Devices & Buffers 2 N.Kapoor However, if we put in a buffer: then the current can be "boosted" back to the original strength. Thus, a buffer (like all logic gates) is an active device. It requires additional inputs to power the gate, and provide it voltage and current. You might wonder "Do I really need to know this? Isn't this just EE stuff?". That's true, it is. The point of the discussion was to motivate the existence of a plain buffer.

The Tri-state Buffer As well as the standard Digital Buffer seen above, there is another type of digital Buffer circuit whose output can be "electronically" disconnected from its output circuitry when required. This type of Buffer is known as a 3-State Buffer or commonly Tristate Buffer. A Tri-state Buffer can be thought of as an input controlled switch which has an output that can be electronically turned "ON" or "OFF" by means of an external "Control" or "Enable" signal input. This control signal can be either a logic "0" or a logic "1" type signal resulting in the Tri-state Buffer being in one state allowing its output to operate normally giving either a logic "0" or logic "1" output. But when activated in the other state it disables or turns "OFF" its output producing an open circuit condition that is neither "High" or "low", but instead gives an output state of very high impedance, high-Z, or more commonly Hi-Z. Then this type of device has two logic state inputs, "0" or a "1" but can produce three different output states, "0", "1" or "Hi-Z" which is why it is called a "3-state" device. There are two different types of Tri-state Buffer, one whose output is controlled by an "Active-HIGH" control signal and the other which is controlled by an "Active-LOW" control signal, as shown below. Active "HIGH" Tri-state Buffer Symbol

Truth Table Enable A 1 0 1 1 0 0 Tri-state Buffer 0 1 Read as Output = Input if Enable is equal to "1"

Q 0 1 Hi-Z Hi-Z

An Active-high Tri-state Buffer is activated when a logic level "1" is applied to its "enable" control line and the data passes through from its input to its output. When the enable control line is at logic level "0", the buffer output is disabled and a high impedance condition, Hi-Z is present on the output. Active "LOW" Tri-state Buffer Symbol

Truth Table Enable A Q 0 0 0 0 1 1 1 0 Hi-Z Tri-state Buffer 1 1 Hi-Z Read as Output = Input if Enable is NOT equal to "1" An Active-low Tri-state Buffer is the opposite to the above, and is activated when a logic level "0" is applied to its "enable" control line. The data passes through from its input to its output. When the enable control line is at logic level "1", the buffer output is disabled and a high impedance condition, Hi-Z is present on the output.

T.Y. E.I. /2 / 1 Tri State Devices & Buffers 3 N.Kapoor Tri-state Buffer Control The Tri-state Buffer is used in many electronic and microprocessor circuits as they allow multiple logic devices to be connected to the same wire or bus without damage or loss of data. For example, suppose we have a data line or data bus with some memory, peripherals, I/O or a CPU connected to it. Each of these devices is capable of sending or receiving data onto this data bus. If these devices start to send or receive data at the same time a short circuit may occur when one device outputs to the bus a logic "1" the supply voltage, while another is set at logic level "0" or ground, resulting in a short circuit condition and possibly damage to the devices. Tri-state Buffer Control ----Then, the Tri-state Buffer can be used to isolate devices and circuits from the data bus and one another. If the outputs of several Tri-state Buffers are electrically connected together Decoders are used to allow only one Tri-state Buffer to be active at any one time while the other devices are in their

high impedance state. An example of Tri-state Buffers connected to a single wire or bus is shown belowIt is also possible to connect Tri-state Buffer "back-to-back" to produce a Bi-directional Buffer circuit with one "active-high buffer" connected in parallel but in reverse with one "active-low buffer". Here, the "enable" control input acts more like a directional control signal causing the data to be both read "from" and transmitted "to" the same data bus wire. Octal Buffer 74LS244 ---It is unidirectional buffer having two groups of 4 buffers. Each group is controlled by enable lines

0 0 1

0 0 1

1As 0 1 X

1Ys 0 1 Hi-Z

2As 0 1 1

2ys 0 1 Hi-Z

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Bi directional Buffers It has two buffers one for each direction.The direction of data transfer is decided by a pin called direction control DIR. Bidirectional buffer is used for data bus of microcomputer system. OCTAL BUS TRANSCEIVER (74LS245)

TRUTH TABLE

T.Y. E.I. /2 / 1 DECODER / ENCODER 1 N.Kapoor DECODER / ENCODER Digital computers, microprocessors and other digital systems are binary operated i.e. the data is processed in form of 0s & 1s . However human operators are more familiar with decimal system. Therefore the need arises for interfacing between digital system and human operators. To accomplish this task, numerous binary codes have been developed. The process of generating these binary codes is known as encoding. The reverse process is known as decoding. Therefore an encoder converts an active input signal into a coded output signal. The Digital Encoder ---Unlike a multiplexer that selects one individual data input line and then sends that data to a single output line or switch, a Digital Encoder more commonly called a Binary Encoder takes ALL its data inputs one at a time and then converts them into a single encoded output. So we can say that a binary encoder, is a multi-input combinational logic circuit that converts the logic level "1" data at its inputs into an equivalent binary code at its output. Generally, digital encoders produce outputs of 2-bit, 3-bit or 4-bit codes depending upon the number of data input lines. An "n-bit" binary encoder has 2n input lines and n-bit output lines with common types that include 4-to-2, 8-to-3 and 16-to-4 line configurations. The output lines of a digital encoder generate the binary equivalent of the input line whose value is equal to "1" and are available to encode either a decimal or hexadecimal input pattern to typically a binary or B.C.D. output code. 4-to-2 Bit Binary Encoder

One of the main disadvantages of standard digital encoders is that they can generate the wrong output code when there is more than one input present at logic level "1". For example, if we make inputs D1 and D2 HIGH at logic "1" at the same time, the resulting output is neither at "01" or at "10" but will be at "11" which is an output binary number that is different to the actual input present. Also, an output code of all logic "0"s can be generated when all of its inputs are at "0" OR when input D 0 is equal to one. One simple way to overcome this problem is to "Prioritise" the level of each input pin and if there was more than one input at logic level "1" the actual output code would only correspond to the input with the highest designated priority. Then this type of digital encoder is known commonly as a Priority Encoder or P-encoder for short. Priority Encoder The Priority Encoder solves the problems mentioned above by allocating a priority level to each input. The priority encoders output corresponds to the currently active input which has the highest priority. So when an input with a higher priority is present, all other inputs with a lower priority will be ignored. The priority encoder comes in many different forms with an example of an 8-input priority encoder along with its truth table shown below. 8-to-3 Bit Priority Encoder

T.Y. E.I. /2 / 1 DECODER / ENCODER 2 N.Kapoor Priority encoders 74LS148---Priority encoders are available in standard IC form and it, has nine inputs and five outputs. The data inputs are indicated by the numbers 74LS47 0 7( active LOW (logic "0") )inputs and the encoded outputs are labeled A0 A2. The additional input, EI, and the two additional outputs, EO and GS, are used for cascading chips when more than eight inputs are required.

Table is the truth table for the 74LS148. As is evident in the table, this chip uses active-LOW inputs and active-LOW outputs. Inputs Outputs 0 1 2 3 4 5 6 7 EI A2 A1 A0 GS EO X X X X X X X X H H H H H H H H H H H H H H L H H H H L X X X X X X X L L L L L L H X X X X X X L H L L L H L H X X X X X L H H L L H L L H X X X X L H H H L L H H L H X X X L H H H H L H L L L H X X L H H H H H L H L H L H X L H H H H H H L H H H L H L H H H H H H H L H H H L H

Binary Decoder --A Decoder is the exact opposite to that of an "Encoder" we looked at in the last tutorial. It is basically, a combinational type logic circuit that converts the binary code data at its input into one of a number of different output lines, one at a time producing an equivalent decimal code at its output. Binary Decoders have inputs of 2-bit, 3-bit or 4-bit codes depending upon the number of data input lines, and a n-bit decoder has 2n output lines. Therefore, if it receives n inputs (usually grouped as a binary or Boolean number) it activates one and only one of its 2n outputs based on that input with all other outputs deactivated. A decoders output code normally has more bits than its input code and practical binary decoder circuits include, 2-to-4, 3-to-8 and 4-to16 line configurations. A binary decoder converts coded inputs into coded outputs, where the input and output codes are different and decoders are available to "decode" either a Binary or BCD (8421 code) input pattern to typically a Decimal output code. Commonly available BCD-to-Decimal decoders include the TTL 7442 or the CMOS 4028. An example of a 2-to-4 line decoder along with its truth table is given below. It consists of an array of four NAND gates, one of which is selected for each combination of the input signals A and B. A 2-to-4 Binary Decoders----

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In this simple example of a 2-to-4 line binary decoder, the binary inputs A and B determine which output line from D0 to D3 is "HIGH" at logic level "1" while the remaining outputs are held "LOW" at logic "0" so only one output can be active (HIGH) at any one time. Therefore, whichever output line is "HIGH" identifies the binary code present at the input, in other words it "de-codes" the binary input and these types of binary decoders are commonly used as Address Decoders in microprocessor memory applications. Some binary decoders have an additional input labelled "Enable" that controls the outputs from the device. This allows the decoders outputs to be turned "ON" or "OFF" and we can see that the logic

74LS138 Binary Decoder diagram of the basic decoder is identical to that of the basic demultiplexer. Therefore, we say that a demultiplexer is a decoder with an additional data line that is used to enable the decoder. An alternative way of looking at the decoder circuit is to regard inputs A, B and C as address signals. Each combination of A, B or C defines a unique address which can access a location having that address. Sometimes it is required to have a Binary Decoder with a number of outputs greater than is available, or if we only have small devices available, we can combine multiple decoders together to form larger decoder networks as shown. Here a much larger 4-to-16 line binary decoder has been implemented using two smaller 3-to-8 decoders. A 4-to-16 Binary Decoder Configuration -- -

T.Y. E.I. /2 / 1 DECODER / ENCODER 4 N.Kapoor Inputs A, B, C are used to select which output on either decoder will be at logic "1" (HIGH) and input D is used with the enable input to select which encoder either the first or second will output the "1". Memory Address Decoder ---Binary Decoders are most often used in more complex digital systems to access a particular memory location based on an "address" produced by a computing device. In modern microprocessor systems the amount of memory required can be quite high and is generally more than one single memory chip alone. One method of overcoming this problem is to connect lots of individual memory chips together and to read the data on a common "Data Bus". In order to prevent the data being "read" from each memory chip at the same time, each memory chip is selected individually one at time and this process is known as Address Decoding. In this application, the address represents the coded data input, and the outputs are the particular memory element select signals. Each memory chip has an input called Chip Select or CS which is used by the MPU to select the appropriate memory chip and a logic "1" on this input selects the device and a logic "0" on the input de-selects it. By selecting or de-selecting each chip, allows us to select the correct memory device for a particular address and when we specify a particular memory address, the corresponding memory location exists ONLY in one of the chips. For example, Lets assume we have a very simple microprocessor system with only 1Kb of RAM memory and 10 address lines. The memory consists of 128x8-bit (128x8 = 1024 bytes) devices and for 1Kb we will need 8 individual memory devices but in order to select the correct memory chip we will also require a 3-to-8 line binary decoder as shown below. Memory Address Decoding----

The binary decoder requires 3 address lines, (A0 to A2) to select each one of the 8 chips (the lower part of the address), while the remaining 7 address lines (A3 to A9) select the correct memory location on that chip (the upper part of the address). Having selected a memory location using the address

bus, the information at the particular internal memory location is sent to the "Data Bus" for use by the microprocessor. This is of course a simple example but the principals remain the same for all types of memory chips or modules. Binary Decoders are very useful devices for converting one digital format to another, such as binary or BCD type data into decimal or octal etc and commonly available decoder IC's are the TTL 74LS138 3-to-8 line binary decoder or the 74ALS154 4-to-16 line decoder. They are also very useful for interfacing to 7-segment displays such as the TTL 74LS47 which we will look at in the next tutorial. Fig 1 shows block diagram of 3 to 8 decoder 74LS138. (They are also called 1 out of 8 binary decoders or demultiplexers).It has three input lines and eight active low output lines. It requires three Enable inputs. Two are active low and one is active high; All three Enable lines should be activitated so that the device can function as a decoder. For example if the 74LS138 is enabled (G 2 A G 2 B ) = 0o and G1 = 1) and if the input is 101, the output Y5 will go low and others will remain high. Verify the outputs for all combinations of inputs as shown in table 1

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Figure 1 Figure 2 Keep Vcc = +5V, enable inputs (G 2 A G 2 B ) = 0 and G1 = 1 (+5V) Function Table Inputs Enable G1 G2 X H L X H L H L H L H L H L H L H L H L C X X L L L L H H H H Select B X X L L H H L L H H A X X L H L H L H L H Y0 H H L H H H H H H H Y1 H H H L H H H H H H Y2 H H H H L H H H H H Outputs Y3 H H H H H L H H H H Y4 H H H H H H L H H H Y5 H H H H H H H L H H Y6 H H H H H H H H L H Y7 H H H H H H H H H L