Professional Documents
Culture Documents
Experimental Set up
Pan and Tilt Mechanism Power Supplies
b t ca e ern Eth
le
Amplifiers
Control Hardware
NI recommends configuring a private network between the cRIO and the host system (student laptops):
IP: 192.168.0.2
IP: 192.168.0.3
IP: 192.168.0.2
IP: 192.168.0.3
IP: 192.168.0.2
Complete PAC Architecture Using LabVIEW FPGA, LabVIEW Real-Time and Host PC
4. On the Projects tab, enter the name of your project in the Project name text box. 5. Click the Browse button. The Select project directory dialog box appears. 6. Browse to the directory where you want to save the LEP file. Click the Select Cur Dir button. The directory path appears in the Project location listbox. 7. Click the OK button.
10. Click OK. 11. Select FileSave Project in the Embedded Project Manager window. LabVIEW saves the configuration settings in the LEP file.
Double-click the function. The Configure Digital Input dialog box appears. Select Slot4/cRIO-9411/DI 0 from the Terminal pull-down menu. Click the Add Input button and select Slot4/cRIO-9411/DI 1 from the Terminal pull-down menu. Click the Add Input button and select Slot4/cRIO-9411/DI 4 from the Terminal pull-down menu.
8. Click the OK button. 9. On the block diagram, use the subvi EncSignalSub1(fpga).vi and make the interconnections shown in the lower left While Loop of figure 1.
12. Select Slot2/cRIO-9263/AO 3 from the Terminal pull-down menu. 13. Click the Add Output button and select Slot2/cRIO-9263/AO 2 from the Terminal pulldown menu. 14. Click the OK button.
Figure 1
Figure 2
4. 5. 6. 7.
Click the Build button. In the Warning: Beginning compile for FPGA dialog box, click the OK button. When LabVIEW returns the Successful Compile Report dialog box, click the OK button. In the Embedded Project Manager window, click the Download button. Click the Run button when the VI has finished downloading.
4. Right-click the function and select Select Target VI from the shortcut menu. The Select Target VI dialog box appears. Browse to the VI that you downloaded to the FPGA and click the OK button. 5. Right-click the Open FPGA VI Reference function and select FPGAcRIO-9101. 6. Place a While Loop on the block diagram to the right of the Open FPGA VI Reference function. Right-click the conditional terminal and select CreateControl. 7. Place the Close FPGA VI Reference function outside of the While Loop. 8. Place the Read/Write Control function inside the While Loop. 9. Wire the HW Exec Ref Out and Error out outputs of the Open FPGA VI Reference function to the HW Exec Ref and Error in inputs of the Read/Write Control function. 10. Right-click the Unselected output of the Read/Write Control function and select Position TILT from the shortcut menu. This terminal corresponds to the actual Position TILT indicator you created in the FPGA VI.
22. 23.
Make all the other standard connections shown in figure3. Save the Host VI and run it.
Figure 3
Figure 4
References