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Manufacturing Process
EE141
CMOS Process
Manufacturing Process
EE141
SiO2 p+
n+
p-epi p+
Manufacturing Process
EE141
M1
M3
This two-inverter circuit (of Figure 3.25 in the text) will be manufactured in a twin-well process.
Digital Integrated Circuits Manufacturing Process EE141
Circuit Layout
Manufacturing Process
EE141
http://www.fullman.com/semiconductors/semiconductors.html
For a complete walk-through of the process (64 steps), check the Book web-page
http://bwrc.eecs.berkeley.edu/Classes/IcBook
Manufacturing Process
EE141
Photo-Lithographic Process
optical mask oxidation
Typical operations in a single photolithographic cycle (from [Fullman]). photoresist development acid etch process step spin, rinse, dry
Manufacturing Process
EE141
Patterning of SiO2
Chemical or plasma etch Si-substrate (a) Silicon base material Photoresist SiO2 Si-substrate (b) After oxidation and deposition of negative photoresist Si-substrate UV-light Patterned optical mask Exposed resist Si-substrate (c) Stepper exposure Digital Integrated Circuits Si-substrate (f) Final result after removal of resist Manufacturing Process EE141 (e) After etching Hardened resist SiO 2 Si-substrate
(d) After development and etching of resist, chemical or plasma etch of SiO 2 Hardened resist SiO 2
SiO 2
Create contact and via windows Deposit and pattern metal layers
Digital Integrated Circuits Manufacturing Process EE141
p+
(c) After plasma etch of insulating trenches using the inverse of the active area mask
Manufacturing Process
EE141
Manufacturing Process
EE141
n +
p+ (h) After n+ source/drain and p+source/drain implants. These steps also dope the polysilicon.
SiO 2 (i) After deposition of SiO 2 insulator and contact hole etch.
Manufacturing Process
EE141
Al SiO 2 (k) After deposition of SiO insulator, etching of vias, 2 deposition and patterning of second layer of Al.
Manufacturing Process
EE141
Advanced Metalization
Manufacturing Process
EE141
Advanced Metalization
Manufacturing Process
EE141
Design Rules
Jan M. Rabaey
Manufacturing Process
EE141
3D Perspective
Polysilicon Aluminum
Manufacturing Process
EE141
Design Rules
l l l
Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules)
Manufacturing Process
EE141
Manufacturing Process
EE141
Manufacturing Process
EE141
Well
Transistor Layout
Transistor
Manufacturing Process
EE141
2 2
Manufacturing Process
EE141
Select Layer
2 3 2 1 3 3 Select
Substrate
Digital Integrated Circuits Manufacturing Process
Well
EE141
A n p+ Field Oxide
EE141
Layout Editor
Manufacturing Process
EE141
Manufacturing Process
EE141
Sticks Diagram
V DD In 3 Out
Dimensionless layout entities Only topology is important Final layout generated by compaction program
1
GND
Stick diagram of inverter
Digital Integrated Circuits
Manufacturing Process
EE141