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CMOS Manufacturing Process

Digital Integrated Circuits

Manufacturing Process

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CMOS Process

Digital Integrated Circuits

Manufacturing Process

EE141

A Modern CMOS Process


gate-oxide TiSi2 AlCu SiO2 Tungsten
poly
p-well n-well

SiO2 p+

n+

p-epi p+

Dual -Well Trench -Isolated CMOS Process

Digital Integrated Circuits

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Circuit Under Design


VDD M2 M4 Vin Vout Vout2 VDD

M1

M3

This two-inverter circuit (of Figure 3.25 in the text) will be manufactured in a twin-well process.
Digital Integrated Circuits Manufacturing Process EE141

Circuit Layout

Digital Integrated Circuits

Manufacturing Process

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The Manufacturing Process


For a great tour through the process and its different steps, check

http://www.fullman.com/semiconductors/semiconductors.html

For a complete walk-through of the process (64 steps), check the Book web-page

http://bwrc.eecs.berkeley.edu/Classes/IcBook

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Photo-Lithographic Process
optical mask oxidation

photoresist removal (ashing)

photoresist coating stepper exposure

Typical operations in a single photolithographic cycle (from [Fullman]). photoresist development acid etch process step spin, rinse, dry

Digital Integrated Circuits

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Patterning of SiO2
Chemical or plasma etch Si-substrate (a) Silicon base material Photoresist SiO2 Si-substrate (b) After oxidation and deposition of negative photoresist Si-substrate UV-light Patterned optical mask Exposed resist Si-substrate (c) Stepper exposure Digital Integrated Circuits Si-substrate (f) Final result after removal of resist Manufacturing Process EE141 (e) After etching Hardened resist SiO 2 Si-substrate

(d) After development and etching of resist, chemical or plasma etch of SiO 2 Hardened resist SiO 2

SiO 2

CMOS Process at a Glance


Define active areas Etch and fill trenches

Implant well regions

Deposit and pattern polysilicon layer

Implant source and drain regions and substrate contacts

Create contact and via windows Deposit and pattern metal layers
Digital Integrated Circuits Manufacturing Process EE141

CMOS Process Walk-Through


p-epi + p SiN 34 p-epi + p SiO 2 (b) After deposition of gate-oxide and sacrificial nitride (acts as a buffer layer) (a) Base material: p+ substrate with p-epi layer

p+

(c) After plasma etch of insulating trenches using the inverse of the active area mask

Digital Integrated Circuits

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CMOS Process Walk-Through


SiO 2 (d) After trench filling, CMP planarization, and removal of sacrificial nitride

(e) After n-well and VTp adjust implants

(f) After p-well and VTn adjust implants

Digital Integrated Circuits

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CMOS Process Walk-Through


poly(silicon) (g) After polysilicon deposition and etch

n +

p+ (h) After n+ source/drain and p+source/drain implants. These steps also dope the polysilicon.

SiO 2 (i) After deposition of SiO 2 insulator and contact hole etch.

Digital Integrated Circuits

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CMOS Process Walk-Through


Al (j) After deposition and patterning of first Al layer.

Al SiO 2 (k) After deposition of SiO insulator, etching of vias, 2 deposition and patterning of second layer of Al.

Digital Integrated Circuits

Manufacturing Process

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Advanced Metalization

Digital Integrated Circuits

Manufacturing Process

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Advanced Metalization

Digital Integrated Circuits

Manufacturing Process

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Design Rules

Jan M. Rabaey

Digital Integrated Circuits

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3D Perspective
Polysilicon Aluminum

Digital Integrated Circuits

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Design Rules
l l l

Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules)

Digital Integrated Circuits

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CMOS Process Layers


Layer Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Color Yellow Green Green Red Blue Magenta Black Black Black Representation

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Layers in 0.25 m CMOS process

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Intra-Layer Design Rules


Same Potential 0 or 6 10 3 Active 3 2 Select Contact or Via Hole 2 2 3
Metal2 3
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Different Potential 9 Polysilicon 2 Metal1 3 2

Well

Transistor Layout
Transistor

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Vias and Contacts


2 Via 1 1 5 Metal to 1 Active Contact Metal to Poly Contact 3 2 4

2 2

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Select Layer
2 3 2 1 3 3 Select

Substrate
Digital Integrated Circuits Manufacturing Process

Well
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CMOS Inverter Layout


GND In VD D A A

Out (a) Layout

A p-substrate n+ (b) Cross-Section along A-A


Digital Integrated Circuits Manufacturing Process

A n p+ Field Oxide

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Layout Editor

Digital Integrated Circuits

Manufacturing Process

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Design Rule Checker

poly_not_fet to all_diff minimum spacing = 0.14 um.

Digital Integrated Circuits

Manufacturing Process

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Sticks Diagram
V DD In 3 Out
Dimensionless layout entities Only topology is important Final layout generated by compaction program

1
GND
Stick diagram of inverter
Digital Integrated Circuits

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