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ECE4680 ALU-II.1
2002-2-20
CarryIn A
Mux
Result
ECE4680 ALU-II.2
2002-2-20
ECE4680 ALU-II.3
2002-2-20
ECE4680 ALU-II.4
2002-2-20
ECE4680 ALU-II.5
2002-2-20
shift right logical srl $1,$2,10 shift right arithm. sra $1,$2,10 shift left logical sllv $1,$2,$3 shift right logical srlv $1,$2, $3 shift right arithm. srav $1,$2, $3
ECE4680 ALU-II.6
2002-2-20
Compare to zero and branch BLEZ rs, offset BGTZ rs, offset BLT BGEZ BLTZAL rs, offset BGEZAL if R[rs] <= 0 then PC-relative branch > < >= if R[rs] < 0 then branch and link (into R 31) >=
ECE4680 ALU-II.7
2002-2-20
ECE4680 ALU-II.8
2002-2-20
ECE4680 ALU-II.9
2002-2-20
CarryIn
Mux
Result
ECE4680 ALU-II.10
2002-2-20
Shifters Three different kinds: logical-- value shifted in is always "0" "0" msb lsb "0"
rotating-- shifted out bits are wrapped around (not in MIPS) left msb lsb right msb lsb
Note: these are single bit shifts. A given instruction might request 0 to 32 bits to be shifted!
ECE4680 ALU-II.11 2002-2-20
D3 D2 D1 D0
Q3 0 0 0 Q2 Q3 0 0
0 1 2 3 0 1 2 3
D3
D2
Q3 0 Q2 Q3 Q1 Q2 Q0 Q1
0 1 0 1 0 1 0 1 x1
0 0
0 1 0 1 0 1 0 1 x2
D3 D2 D1 D0
Q0 Q1 Q2 Q3
0 1 2 3
D0
ECE4680 ALU-II.12
2002-2-20
S0 (0, 1)
S1 (0, 2) S2 (0, 4)
S3 (0, 8) Shamt = S3S2S1S0 ; If SiS=0, go straight; if Si=0, go skew. If right-to-left connections are added, it could support Rotate Shift Right.
ECE4680 ALU-II.13
2002-2-20
MULTIPLY (p250)
Paper and pencil example: Multiplicand Multiplier x 1000 1001 1000 0000 0000 1000 1001000
Product
m bits x n bits = m+n bit product Binary makes it easy: only 2 choices at each step 1 => place multiplicand ( 1 x multiplicand) 0 => place 0 ( 0 x multiplicand) 3 versions of multiply hardware & algorithm: successive refinement
ECE4680 ALU-II.14
2002-2-20
B1
A3
A2
A1
A0 B2
A3
A2
A1
A0
B3
P7
P6
P5
P4
P3
P2
P1
P0
Stage i accumulates A * 2 i if Bi == 1 Q: How much hardware for 32 bit multiplier? Critical path?
ECE4680 ALU-II.15 2002-2-20
B2 B3
at each stage shift A left ( x 2) use next bit of B to determine whether to add in shifted multiplicand accumulate 2n bit partial product at each stage
ECE4680 ALU-II.16
2002-2-20
Multiplicand 64 bits
Shift Left
64-bit ALU
Product 64 bits
Write
Control
ECE4680 ALU-II.17
2002-2-20
Start
1.Test Multiplier0
Multiplier0 = 0
1a. Add multiplicand to product and place the result in Product register.
Product Multiplier 0000 0000 0011 0000 0010 0001 0000 0110 0000 0000 0110
32nd repetition?
ECE4680 ALU-II.19
2002-2-20
A3
A2
A1
A0 B1
A3
A2
A1
A0 B2
A3
A2
A1
A0 B3
P7
P6
P5
P4
P3
P2
P1
P0
32-bit ALU
Product 64 bits
Control
ECE4680 ALU-II.21
2002-2-20
Start
1. Test Multiplier0
Multiplier0 = 0
Product 0000 0000 0010 0000 0001 0000 0011 0000 0001 1000 0000 1100 0000 0110
ECE4680 ALU-II.22
Multiplier Multiplicand(p256) 0011 0011 0001 0001 0000 0000 0000 0010 0010 0010 0010 0010 0010 0010
Done
2002-2-20
32nd repetition?
Yes: 32 repetitions
ECE4680 ALU-II.23
2002-2-20
Multiplicand 32 bits
32-bit ALU
Control
ECE4680 ALU-II.24
2002-2-20
Start
1. Test Product0
Product0=0
1a. Add multiplicand to the left half of the product and place the result in the left half of the Product register.
Product | Multiplier 0000 0011 0010 0011 0001 0001 0011 0000 0001 1000 0000 1100 0000 0110
ECE4680 ALU-II.25
ECE4680 ALU-II.26
2002-2-20
ALU with add or subtract gets same result in more than one way: 6 = 2 + 8 , or 0110 = 0010 + 1000 = 1110 + 1000 Replace a string of 1s in multiplier with an initial subtract when we first see a one and then later add for the bit after the last one. For example x + + +
ECE4680 ALU-II.27
shift (0 in multiplier) sub (first 1 in multiplier) shift (middle of string of 1s) add (prior step had last 1)
2002-2-20
end of run
Current Bit 1 1 0 0
middle of run
beginning of run
Example 0001111000 0001111000 0001111000 0001111000
0 1 1 1 1 0
Bit to the Right 0 1 1 0 Explanation Beginning of a run of 1s Middle of a run of 1s End of a run of 1s Middle of a run of 0s
Originally for Speed since shift faster than add for his machine Replace a string of 1s in multiplier with an initial subtract when we first see a one and then later add for the bit after the last one 1 + 10000 01111
ECE4680 ALU-II.28 2002-2-20
Booths Algorithm
1. Depending on the current and previous bits, do one of the following: 00: 01: 10: 11: a. Middle of a string of 0s, so no arithmetic operations. b. End of a string of 1s, so add the multiplicand to the left half of the product. c. Beginning of a string of 1s, so subtract the multiplicand from the left half of the product. d. Middle of a string of 1s, so no arithmetic operation.
2.As in the previous algorithm, shift the Product register right (arith) 1 bit.
ECE4680 ALU-II.29
2002-2-20
Booths Example: 2 x 7
Operation 0. initial value 1a. P = P - m 1b. 2. 3. 4a. 4b. Multiplicand 0010 1110 0010 0010 0010 0010 0010
Product|Multiplier 0000 0111 0 + 1110 1110 0111 0 1111 0011 1 1111 1001 1 1111 1100 1 + 0010 0001 1100 1 0000 1110 0
next? 10 -> sub shift P (sign ext) 11 -> nop, shift 11 -> nop, shift 01 -> add shift done
ECE4680 ALU-II.30
2002-2-20
Booths Example: 2 x 3
Operation Multiplicand
Product 0000 1101 0 + 1110 1110 1101 0 1111 0110 1 + 0010 0001 0110 1
next? 10 -> sub shift P (sign ext) 01 -> add shift P 10 -> sub shift 11 -> nop shift done
0. initial value 0010 1a. P = P - m 1110 1b. 2a. 2b. 3a. 3b. 4a 4b. 0010 0010 0010 0010 0010
0000 1011 0 + 1110 1110 1011 0 1111 0101 1 1111 0101 1 1111 1010 1
ECE4680 ALU-II.31
2002-2-20
Summary
Instruction Set drives the ALU design Shifter: success refinement from 1/bit at a time shift register to barrel shifter Multiply: successive refinement to see final design 32-bit Adder, 64-bit shift register, 32-bit Multiplicand Register Booths algorithm to handle signed multiplies There are algorithms that calculate many bits of multiply per cycle Whats Missing from MIPS is Divide & Floating Point Arithmetic: Next time the Pentium Bug
ECE4680 ALU-II.32
2002-2-20