Field- Programmable Gateway Array 22 Nov 2012

Meeting the design challenges of FPGA to increase speed, reduce power consumptions and optimize memory function to ensure best performance 08.30 Registration 09.0 Pre-training questionnaire & live polling

09.15 Identifying FPGA selection parameters that are best aligned with your project to enhance project performance Selecting the most appropriate device technology that aligns hardware to the project requirement Working out the DSP logic block estimation for reducing time constraints Optimizing memory function for smooth functioning of the device Identifying interface requirement to select most suitable programmable technology Accessing parameters necessary for device package selection Examining specialty features, previous experience, cost and availability before selecting programmable technology

10.30 Morning refreshments and networking 11.0 Meeting the porting challenges of transitioning from ASIC to FPGA Understanding basics of FPGA and comparing them to ASIC Using an target independent design methodology for FPGA projects Evaluating synopses design constraints for timing of FPGA device Writing generic RTL

Examining the benefits and challenges of using phase-lock loop or delay-lock

loop for special applications

12.30 Selecting most suitable design architecture to enhance performance and increase speed of FPGA device Understanding development flow of the hardware Using clock circuitries and Static terminal accesses Locating and correcting design bottlenecks Working out advanced timing constraints Synchronising circuit usage Identifying advanced options to improve performance

14.00 Lunch and networking

15.00 Evaluating different data path architectures to reduce power consumption whilst maintain or enhancing speed with memory Evaluating performance matrix of FPGA design with your project requirement Identifying and implementing optimisation techniques Evaluating various tolls that will help reduce the power consumption Examining most suitable debugging techniques and tools for software and hardware

16.00 Afternoon break and networking 16.30 Simplifying FPGAs for the software engineers to increase speed of the project and reduce time-to-market Learning more about pre-built FPGA embedded processor designs Understanding system Integration and support of required OS Identifying suitable methods of implementing next-generation system-onchip on design Maintaining connectivity through bridging and switching Understanding code conventions for editing, compiling, linking, and generating new libraries Creation of software application projects

17.30 Future of FPGA

Mapping the current national and international markets of FPGA to forecast the future opportunities and challenges Comparing different vendors products and their features to assess suitability in certain projects The way ahead for FPGAs after 20 years

18.00 Post-training live polling and calculating ROI of attending this training 18.15 Close of the FPGA Conference

Verification Methodologies for Next-Generation Designs 23 November 2012

Understanding the strengths of each language and universal verification methodology 08.30 Registration 09.00 Pre- training questionnaire 09.15 Improving the Verification Process Planning for the verification Automatic generation of test vectors Metrics to ensure comprehensive testing Using properties Testbench architecture Transaction-level modelling Class-based environments Standards and Verification IP

10.30 Morning refreshments and networking 11.00 Enhancements to VHDL Test benches Useful VHDL 2008 features Open-Source VHDL Verification Methodology (OS-VVM) Constrained-Random Vectors Functional Coverage

12.00 Creating Virtual Prototypes and Testbenches in SystemC Introduction to SystemC language and features Transaction Level Modelling Standard

 Use of basic protocol and generic payload Constrained-Random Transactions and Transaction Recording The Control, Configuration and Introspection (CCI) Standard for Verification IP 13.00 Lunch and networking 14.00 System Verilog features for Verification Transactions and Verification Components Using Interfaces to separate class-based verification environment from RTL Device-Under-Test (DUT) and associated test harness Specifying constraints Setting up functional coverage Writing properties and sequences

15.30 Afternoon break and networking 16.00 The Universal Verification Methodology (UVM) Overview of UVM class library and features Creating a UVM environment Writing a sequence to drive the DUT Setting up the environment for a specific test Use of the Register Layer

17.30 Conclusions and Closing Remarks Strengths and weaknesses of each methodology Selecting the most appropriate methodology for your design Mixed-language test benches Future Directions?

18.00 Post-training live polling and calculating ROI of attending this training 18.15 Close of the Verification workshop