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Example: T Flip-Flop

T flip-flop: Q(t+1) = T Q
T A > Q Q T > Q B

Example: D Flip-Flop
SI

T flip-flop: Q(t+1) = D

D Q 0 >

S3

D Q 1 >

S2

D Q 0 >

S1 SO

CP

CP

Flip-flop input functions:


TA = A B TB = (Ax)

A = TA A = (A B) A = B B = TB B = (A x) B output: y = ABx
ENEE244: Digital Logic Design

Serial Output SO(t) = S1(t) Serial Input S1(t+1) = S2(t) (Shift) Register S2(t+1) = S3(t) S3(t+1) = SI (t) CP What are the initial values of the flip-flops? What is the output sequence on input 11010100? What is SO(t+3)? Draw the state transition diagram.
ENEE244: Digital Logic Design

Mealy and Moore Models


Mealy model: outputs are functions of both present state and inputs.
E.g., the early examples with JK and T.

Mealy and Moore Models

Moore model: outputs are functions of the present state (outputs of the flip-flops) only.
This does not mean that output is independent of the inputs. Instead, the impact is through flipflops. E.g., the D example in the previous slide.
ENEE244: Digital Logic Design ENEE244: Digital Logic Design

Sequential Circuit Design


Given: system description Goal: logic diagram, Boolean function expression
1. 2. 3. 4. 5. 6. 7. System specification State table construction State reduction and assignment Flip-flop selection Excitation/output table derivation Function simplification Logic diagram drawing
ENEE244: Digital Logic Design

Excitation Table
characteristic table
S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Q 0 1 0 1 0 1 0 1 Q(t+1) 0 1 0 0 1 1 i.d. i.d. Q(t) Q(t+1) 0 0 1 1
ENEE244: Digital Logic Design

Excitation table: indicates


how we should change flipflop inputs to make the required state transition.

S 0 1 0 x

R x 0 1 0

0 1 0 1

Flip-Flop Excitation Tables


Q(t) Q(t+1) 0 0 1 1 0 1 0 1 S 0 1 0 x J 0 1 x x R x 0 1 0 K x x 1 0 Q(t) Q(t+1) 0 0 1 1 0 1 0 1 D 0 1 0 1 T 0 1 1 0

Example
A sequential circuit has two flip-flops, A and B; one input, x; and one output, y; with the following state diagram. Design the system with JK flip-flops.
Sequential Circuit Design
Given: system description Goal: logic diagram, Boolean function expression
1. 2. 3. 4. 5. 6. 7. System specification State table construction State reduction and assignment Flip-flop selection Excitation/output table derivation Function simplification Logic diagram drawing
ENEE244: Digital Logic Design

1/1 00 0/0 01 0/1 0/1 1/0 1/0 1/1 11 0/0 10

Q(t) Q(t+1) 0 0 1 1 0 1 0 1

Q(t) Q(t+1) 0 0 1 1 0 1 0 1

ENEE244: Digital Logic Design

ENEE244: Digital Logic Design

Build the Excitation Table


Current State A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 In x 0 1 0 1 0 1 0 1 Next State A 0 0 1 1 0 0 1 1 B 1 0 0 1 0 1 1 0 Flip-flop input functions JA 0 0 1 1 x x x x KA x x x x 1 1 0 0 JB 1 0 x x 0 1 x x KB x x 1 0 x x 0 1
Q(t) 0 0 1 1 Q(t+1) 0 1 0 1 J 0 1 x x K x x 1 0

Determine Flip-Flop Inputs


Current State A 0 0 0 0 B 0 0 1 1 0 0 1 1 In x 0 1 0 1 0 1 0 1 Next State A 0 0 1 1 0 0 1 1 B 1 0 0 1 0 1 1 0 Flip-flop input functions JA 0 0 1 1 x x x x KA x x x x 1 1 0 0 JB 1 0 x x 0 1 x x KB x x 1 0 x x 0 1

Bx A 00 01 0 x 1 x Bx A 00 01 0 x x 1 1 1 Bx A 0 1 Bx A 0 1 00 01 1 1 00 01 x x x x

11 1 x

10 1 x

1/1 00 0/0 01 0/1 0/1 1/0 1/0 1/1 11 0/0 10

11 10 x x

1 1 1 1

11 10 x x x x 11 10 1 1

JA = B JB =Ax+Ax = (Ax) KA = B KB =Ax+Ax = (Ax)


ENEE244: Digital Logic Design

ENEE244: Digital Logic Design

Determine the Outputs


1/1 Current In Next Out State State A B x A B y 0 0 0 0 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 0 1 1 0 1 1 0 1 0 0 1 Bx A 00 0 1 1 01 1 00 0/0 01 11 1 x 10 1 0/1 0/1 1/0 1/0 1/1 11
J

Draw Logic Diagram


1/1

Flip-flop input functions:


10 JA = B JB = (Ax) KA = B KB = (Ax) 00 0/0 01
CP

0/1 0/1 1/0 1/0

10 1/1 11 0/0

output:

y = ABx

0/0

>
K

Q Q

>
K

Q Q

B B

y
ENEE244: Digital Logic Design

y = ABx
ENEE244: Digital Logic Design

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