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The assign statement in Verilog allows two nets or ports to be connected to each other. In a netlist this occurs in one of two cases: An input port entering a module is directly connected to an output port without any logic in between: assign MonitorxSO = ControlInxSI A signal within a module is connected to one or more output ports directly. assign ScanOutxTO = DataxD assign DataOutxDO = DataxD
contains the defaults that will be used by encounter during startup. In this file, the command setDoAssign determines what will be done with assign statements in the netlist. setDoAssign on -buffer BUFX1_or_similar will instantiate a physical buffer (named BUFX1) to replace the assign statements. This removes all the assign statements, and the hierarchical netlist can easily be processed. Sometimes problems occur, especially when the input/output of such an assign buffer is optimized away, the assign buffer will still be kept. setDoAssign off will try to preserve the assign statements. In some cases the resulting netlist will have problems. In short neither of the solutions is foolproof. It would be better to minimize the number of assign statements as much as possible.
Once you have the netlist you can use the grep command to look for assign within the netlist. If the command returns you results you have assign statements. grep -i assign netlist.v