Low Noise Amplifier Design Project

EEL6328C Spring 2007 Wednesday, April 25th, 2007

Team members Fares Maarouf Manu Suryavansh Muhammad Rahman Sandip Nallani Chakravartula
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Table of Contents 1.Circuit description.3 2.Hand/Matlab analysis....4 2.1 Input matching...4 2.2 Output matching5 2.3 Parasitic extraction/estimation...7 3. Spice simulation results .9 4. Comparison between hand/Matlab analysis and simulation results..13 5. Variability analysis....15 6. Layout description and philosophies behind the layout 17 6.1 Transistor layout..17 6.2 Capacitor layout...17 6.3 Inductor layout.17 6.4 Overall layout...18 7. Bonding diagram of the IC....19 8. Instructions for how the circuit should be used.20 9. Conclusion/Summary21 List of Figures List of Tables Appendix

1. Circuit Description Our goal was to design a Low-Noise Amplifier that satisfied the specifications listed in Table 1. We assume the center frequency to be 2.44GHz. In order to isolate the outputmatching network from the input-matching network, we design our LNA as the cascode structure shown in Figure-1. The inductor LG is used to cancel out the input capacitance and the inductor LS is used to increase the input resistance looking into the gate of the common-source MOS transistor. The required specifications are shown in the Table-1.1. We then match the input to 50. For the input and output matching networks, we must consider all package parasitic capacitors and inductors. In the following section, we will show the initial hand/Matlab Analyses and compare the hand analyses results with the simulation results. Operating Frequency 2.4-2.48GHz Center Frequency 2.44GHz GT Greater than 12dB in Less than 10dB out Less than 10dB VDD 2.7 ~ 3.3V IIP3 Greater than 10dBm Noise Figure 50 Less than 2.5dB Table 1.1: LNA Specifications

Figure-1: Circuit Diagram 3

2. Initial Hand / Matlab Analysis

Using the S11 expression as shown below the an upper limit on the Qin was found. As shown in Figure-2.1 the component variations have been considered when calculating an upper bound on Q. Then we use the following equations to find the Cgs from Lg. Upon which the Gm of the cascade is found out. The Qin of the circuit is simply Q/2. Once we have the Gm we can compute the value of Ls. The resulting values found from hand analysis are shown in Table.2-1 1. S11=20*log10((Q*(w./wo-wo./w))./sqrt(4+Q*Q*(w./wo-wo./w)^2)); 2. Qin=Q/2 3. Lg=(2*Qin*Zo)/wo 4. Cgd1=Cgs/4 5. Cgs(1+gm1/gm2)Cgd1)=Lg*wo*wo 6. Gm=(gamma*4*Zo*Zo*Cgs*Cgs*wo*wo)/((NF-1)*Zo-rg) 7. Ls=(Zo-rg1)/(gm*N*Lg*wo*wo)

Figure-2.1 Input Matching

2.1 Output Matching

Figure-2.2 Output Matching For the output matching, let us consider the circuit shown in Fig 3. In this part, we include package inductor, Lpack, and the capacitors, Cpad and CGnd, associated with package. We also include the sheet resistances associated with MOS caps, C1 and C2, in the output matching network we will provide the sheet resistance associated with MOS caps later. For the collector inductor, Leff, we must solve the following equation.
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( L )Co 2 k L 2 L2 + 1 =

L QL R01

where C o = N * Cdb + N * Cgd We choose QL as 3. QL=2*QLoad, and assume kL to be 5.810-9. Now, we use the Smith chart to estimate R01. From Figure-2.3, we can see that we have to rotate load resistance, 50,from the origin on the Smith chart due to the shunt CGnd, series Lpack, shunt Cpad, shunt C1 and series C2. The impedance, R01, is 68 as shown in Figure-2.3, which is the intercept point on the real axis of Smith chart. Thus, we can derive the value of C1 to be 574fF. Using following equations, we can obtain the value of C2.
Bj 1 + =0 2 G +B C 2j
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R01 =

G = 68 G + B2
2

G=

1 LQ L

B=

L(Co + C L ) 2 1 , where C L = k L L L G2 + B2 = 973 fF B

Finally, C 2 =

Table-2 shows all the component values we calculated by hand/Matlab Analysis. The Matlab code is attached at the end of the report.

Figure-2.3 The Inductor at the drain

Component Name R01 LG LS L C1 C2 Ic Qin QL

Component Value 68 6.52 nH 0.7 nH 3.79 nH 574 fF 973 fF 7.9 mA 1.333 3

Table-2.1: Hand/Matlab Calculation Results

2.3 Parasitic extraction/estimation The parasitic elements have been computed shown below:

2.3.1 Common Gate NMOS Cdb2=Cjo*D*W+Cjwo*(2D)+Cjswo*(2W) D=1.2e-6m W=12e-6 m No of fingers N=30 Cjo =Cj/(1+Vdb/ b)mj =5.35e-4 F/m2 @Vdb=2.95V Cjswo=Cjsw/(1+Vdb/bsw)mjsw = 2.757e-10 F/m Cjswgo = Cjswg/(1+Vdb/bswg)mjsw =1.5249e-10 F/m Ctotal =N*Cdb2= 30*12 fF =360 fF Rg = .875

2.3.2 Common Source NMOS Cdb1=Cjo*D*W+Cjwo*(2D)+Cjswo*(2W) D=1.2e-6m W=12e-6 m No of fingers N=30 Cjo =Cj/(1+Vdb/ b)mj =8.05e-4 F/m2 @Vdb=0.37V Cjswo=Cjsw/(1+Vdb/bsw)mjsw = 3.153e-10 F/m Cjswgo = Cjswg/(1+Vdb/bswg)mjsw =1.744e-10 F/m Ctotal =N*Cdb1= 30*12 fF =490 fF Rg = .875

2.3.3 Inductors Lout= 2 nH Lg = 4nH RLout=Rs*L/W=.07*1920 um/16 um =8.4 Rg =.0255*L/W =.0255*3040/16=4.845 Cout= 184 fF Cg= 170 Ff

2.3.4 Capacitors Rs=1/3*1/2*1/2*1/N*(Rnw*L/W+Rpoly*W/L) Rsc1=1.01 ( C1 =356 pF) Rsc2= .87 (C2= 300 pF) 2.3.5 Pacakage Lead Inductance : 2 nH per pin Rlead =.02 Bond Wire inductance .82 pH/um Rbond =.12 m /um Bond wire Cap=.06 fF/um Bond Pad Capacitance 100 fF

2.3.6 Off-chip Components Cbypass =20 pF Parasitic Series inductance = .6 nH

3. SpectreS simulation results The schematic that was used for simulation is shown in Figure-3.1. Table 3.1 lists the simulation results for S11 (Figure-3.2), S22 (Figure-3.3), GT (Figure-3.4), NF (Figure3.5), and IIP3 (Figure-3.6). The simulation result for IIP3 is shown in the figure on the next page. We have included all parasitic components in our simulations, as shown in the Schematic (Figure-3.1). It is important to note that, the only external component is Cbypass. All other components are designed as on-chip components. Table-3.1 lists our simulation results for S11, S22, GT, and NF. We can see that the S11 and S22 are both below 10dB for the entire frequency range from 2.4GHz to 2.48GHz. In addition, the GT value is greater than 12dB and NF is smaller than 2.5dB, meeting the design specifications.

Operating Frequency Center Frequency

S11 S22 GT Greater than > 15 dB NF Less than 2.46 dB IIP3 -8 dBm Table-3.1: Simulation Results List

2.4-2.48GHz 2.44GHz Less than 10dB Less than 10dB

Figure-3.1 The schematic used for LNA simulations

Figure-3.2 Simulation results for S11 (Less than -10 dB) 10

Figure-3.3 Simulation results for S22 (Less than -10 dB)

Figure-3.4 Simulation results for GT (Greater than 15.5dB)

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Figure-3.5 Simulation results for NF (Less than 2.5 dB)

Figure-3.6 Simulation results for IIP3 (-8 dBm)

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4. Comparison between hand/Matlab analysis and simulation results We must adjust the component values in the input and output matching networks to optimize performance because we include all parasitic components in the simulation. Table-4.1 lists all the component values we used in simulation and compares each value with hand/Matlab calculation results. It shows the performance of GT, NF, and IIP3 as well. We increase the number of stripes to 30 because we want to effectively decrease NF caused by base resistance, rg.

Component Name LG LS L C1 C2 Ic VDD Qin QL

Component Value (hand/Matlab analysis) 6.52nH 0.6 nH 3.56nH 574 fF 973 fF 9mA 3V 1 3 12.5dB 2.5dB X

Component value (Simulation) 4.4nH 0.2nH 2nH 560fF 356fF 7.9mA X X X >15.5dB <2.46dB -8dBm

Performance Comparison GT NF IIP3

Table-4.1: Comparison between Hand/Matlab Analysis and Simulation Results

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5. Variability analysis Due to the variation of on-chip components C1 (Figure-5.1), C2 (Figure-5.2), W1 (Figure-5.3) which is the width of common-source MOSFET, W2 (Figure-5.4) which is the width of common-gate MOSFET, and VDD (Figure-5.5) by +/- 10%, the circuit experiences variability as shown in the respectively attached figures. The results of the e did the variability analysis were done using the Parametric Analysis in Candence.

Figure-5.1 Variability in C1

Figure-5.2 Variability in C2

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Figure-5.3 Variability in W1 (width of common-source MOSFET)

Figure-5.4 in W2 (width of common-source MOSFET)

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Figure-5.5 Variability in VDD

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6. Layout Description and Philosophies behind the Layout 6.1 Transistor Layout We have used Cascode topology for our LNA.It provides great isolation between input and output. And at the same time it does not reduce the Gain of the amplifier. Main Considerations of the Layout As mentioned earlier, in order to decrease the effect of Rg, the number of Fingers (N) set to 30 and hence we get an rg of one ohm. Through analysis of the effect of N on the transducer gain, GT, and noise figure, NF, we determined that placing 30 transistors in parallel for each stage of the cascode amplifier would provide the best performance. It also helps decrease the Cdb. Sizes of the both the common-gate and common-source NMOS transistors were set to W=350 um L=0.4um

6.2 Capacitor Layout We have integrated two on chip capacitors of 356 fF and 500 fF.Our capacitors are composed of two layers. The bottom layer is an n-Well and the top layer is a p-type polysilicon.We made fingers on that to reduce the resistance down to 1 ohm.

6.3 Inductor Layout Two on chip inductor of Lg= 4 nH and Lout=2 nH have been layed out with patterened ground shield to combat substrate resistance.Metal 3 is used to lower the parasitic capacitances of L .To achieve desired Q,desired resistances are achieved by shunting metal 3 and metal 4. Resistance are 8.4 and 4.8 ohm respectively. For Ls we are using down-bonds. For both the inductors, the lengths, areas, parasitic resistances/capacitances were computed using Matlab. These values of course matched the simulation results are shown in Table-6.1 . The Matlab codes have been attached at end of the report. Also, a protective ground shield (PGS) was laid out under each of the inductors to reduce the parasitic resistances and capacitances.

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Lg L

Width Spacing Turn w(um) s(um) N 16 4 3.25 16 2 2.25 Table-6.1 Inductor design

Dout (um) 296 256

6.4 Overall layout In the overall layout (showin in the following page), there are several things to be considered. First, all of the isolation layers should be connected to the ground to prevent crosstalk between two signal lines. The ground plane between the isolation must be large to reduce the parasitic resistance of the metal. Multiple down bonds to ground connected to the package ground reduce the bond wire inductance and resistance. Therefore, all of the vacant pads are connected to the ground using down bonds. For the arrangement of the pads, there should be ground pads between each signal pads to reduce the crosstalk coupling. The final layout is shown on the next page.

Figure-6.1 The overall layout on Virtuoso,Cadence

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7. Bonding diagram of the IC

Figure-7.1 The bonding diagram

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8. Instructions for how the circuit should be used A bypass capacitor of 100 pF has to be connected off-chip at the Vdd and Vbias.

Figure-8.1: LNA Pinout

1 2 3 4 5 6 7 8

Vbias V_Bias RF_in GND VDD No connection RF_out No connection Table-8.1 LNA Pinout

Figure-8.2 External/Off Chip components.

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9. Conclusion/Summary Using TSMC CMOS 35 um technology, a low noise amplifier was designed. It works in a frequency range of 2.4 to 2.48 GHz and meets all the required specifications. Initially, MATLAB/hand analysis was used to get a rough estimate of LNA parameters and other circuit elements. SpectreS was then used to simulate and test the performance of the circuit by iterating various component values. In addition to the circuit components, various parasitic elements were also considered in all the simulations. Similar results from MATLAB and SpectreS were obtained, which satisfied the specifications of the design. The pin-out and external connections for the LNA were then explained. Finally, the circuit was laid out on CADENCE-VIRTUOSO. No DRC errors were found except for the MOS capacitors (C1 and C2).

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List of Figures Figure-2.1 Input Matching...5 Figure-2.2 Output Matching6 Figure-2.3 The Inductor at the drain ...7 Figure-3.1 The schematic used for LNA simulations11 Figure-3.2 Simulation results for S11 (Less than -10 dB) 11 Figure-3.3 Simulation results for S22 (Less than -10 dB).12 Figure-3.4 Simulation results for GT (Greater than 15.5dB).12 Figure-3.5 Simulation results for NF (Less than 2.5 dB)..13 Figure-3.6 Simulation results for IIP3 (-8 dBm)...13 Figure-5.1 Variability in C1...15 Figure-5.2 Variability in C2...15 Figure-5.3 Variability in W1 (width of common-source MOSFET)..16 Figure-5.4 in W2 (width of common-source MOSFET)16 Figure-5.5 Variability in VDD...17 Figure-6.1 The overall layout on Virtuoso,Cadence..19 Figure-7.1 The bonding diagram...20 Figure-8.1: LNA Pinout 21 Figure-8.2 External/Off Chip components. ..21

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List of Tables Table 1.1: LNA Specifications 4 Table-2.1: Hand/Matlab Calculation Results8 Table-3.1: Simulation Results List..10 Table-4.1: Comparison between Hand/Matlab Analysis and Simulation Results ..14 Table-6.1 Inductor design..19 Table-8.1 LNA Pinout...21

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APPENDIX Matlab Code for LNA Paramaters/Design.

clear all; Zo=50; S11max=10; fo=2.4+0.04; wo=2*pi*fo*1e9; fb=0.04e9; w1=wo+2*pi*fb; w2=wo-2*pi*fb; Rv1=1.1; Rv2=0.9; Zov1=1.1; Zov2=0.9; Lv=0.9; Cv=0.9; R=50; Zov=50*Zov2 S11=10^(-12/20) var=1/(sqrt(Lv*Cv)) fact=(1-abs(var)) w=w1+wo*abs((1-var)) t=(w/wo)-(wo/w); Qsq=((R-Zov)^2-((R+Zov)^2*S11^2))/((S11^2-1)*t^2*R^2); Q=sqrt(Qsq); Qgs=Q; Qin=Qgs/2 Lg=(2*Qin*Zo)/wo Cgs1=2/(3*Lg*wo^2) tox=7.8e-9; eo=8.85e-12; eox=3.9; L1=0.35e-6; Cox=(eox*eo)/tox; Cgso=3.11e-10; W1=Cgs1/((2/3)*L1*Cox+Cgso) rg1=1;

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NF=0.6; F=10^(NF/10) gam=2/3; gm1=(gam*4*Zo^2*Cgs1^2*wo^2)/((F-1)*Zo-rg1) Ls=(Zo-rg1)/(gm1*Lg*wo^2) Qload=1.5; Ql=2*Qload; k=5.8e-9; UnCox=181.6e-6; Id1=gm1^2/(2*UnCox*(W1/L1)) Cdb2=1.7458e-013; Cgd2=1.0885e-013; Co=Cdb2+Cgd2; lamda=2.61; Id2=Id1; gm2=gm1; Ro2=1/lamda*Id2; Ro=gm2*Ro2^2; Lpack=2e-9; Point1=(j*wo*Lpack)/50; C1=0.44/(wo*Zo); Ro1=70; p1=-k*wo^2 p2=-Co*wo^2 p3=-sqrt(wo/(Ql*Ro1)) p4=1 p=[p1 p2 p3 p4]; r=roots(p); Le=r.^2 Leff=3.24e-9; Rs=(Leff*wo*Ql)/(1+Ql^2) Rls=Rs*(1+Ql^2) Rtot=Rls; k=5.8e-9; Cl=k*sqrt(Leff); Gt=4*gm1^2*Rs*Zo*Qin^2*Qload^2 Gtdb=10*log(Gt)

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Ctot=Co+Cl; Ztot=Rtot+1/(j*wo*Ctot)+j*wo*Leff G=1/(Leff*wo*Ql); B=(Leff*(Co+Cl)*wo^2-1)/(Leff*wo) C2=-(G^2+B^2)/(B*wo)

Matlab Code for the design of Inductor L (connected to the drain of CG MOSFET) beta=1.62e-3; dout=296;%um din=164;%um davg=(din+dout)/2;%um n=2.25;%number of turns s=4;%um w=16;%um a1=-1.21; a2=-0.147; a3=2.40; a4=1.78; a5=-0.03; l=(240*3+220*2+200*2+180*2); L=beta*(dout^a1)*(w^a2)*(davg^a3)*(n^a4)*(s^a5) res=(0.07*l/w) Ametal=w*(240*3+220*2+200*2+180*2)%um*um Cp=12*1e-18; C=0.5*Ametal*Cp Matlab code for the design of inductor LG (connected to gate of CS MOSFET) %% FOR L2=4.4nH, Rs=5ohms , Cp=200fF close all; beta=1.62e-3; dout=296;%um din=164;%um 26

davg=(din+dout)/2;%um n=3+.25+.17;%number of turns s=4;%um w=16;%um a1=-1.21; a2=-0.147; a3=2.40; a4=1.78; a5=-0.03; %Extra Length Calc %160um=0.25 of a turn(approx) => 1um=(0.25)/160th of a turn => %x*.25/160=0.17 => x=.17*160/0.25=108um l=3040+108; L=beta*(dout^a1)*(w^a2)*(davg^a3)*(n^a4)*(s^a5) res=(0.02*l/w) Ametal=w*(280*3+260*2+240*2+220*2+200*2+180*2+108)%um*um Cp=7*1e-18; C=0.5*Ametal*Cp

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