A110 MIDAS: Multi-standard Integrated Devices for broadband DSL Access and home powerline communicationS

. Objectives

www.medeaplus.org

Consortium &. Organization

To develop new wireline communication systems and architectures with increased bandwidth, capacity, security and QoS New DSL: ADSL2, ADSL2+, symmetric DSL (10MDSL, Ethernet over DSL) New broadband PLC for in-home networking To work on mechanisms, protocols and associated architectures for MAC, QoS, Security/Safety and user Privacy To develop and manufacture low-power and cost-effective components for wireline communication devices To develop wireline integrated platforms bridging xDSL and PLC and demonstrate these platforms in the field To participate to international standardization and promote the technologies and concepts developed in the project
Pisa

To work on the convergence of wireline communication technologies

Value . chain
Universities
KULeuven, LTH, KULeuven, ENS, IMSE-CNM IMSEAlgorithms, architecture concepts, Algorithms, feasibility studies

Research institutes
IMEC, France Telecom R&D

PCC

Project leader STM Belgium

16 partners Start date: 1 July 2003 End date: 30 June 2005 Budget : 177 person.years Countries involved: Belgium, France, Spain, Sweden

System requirements

System requirements

System Equipment Manufacturers

Alcatel, Thomson, Ericsson, Veyado, Seba service, Upzide Labs, LEA Labs, Feedback on System performances

Target

DS2

Alcatel

STM B

Thomson B

Test chips, chip sets System requirements and Specs Platforms and demonstrators

Enabling design methodologies & flexible SoC design tools

soft generation of analog IP blocks versatile Application Specific Signal Processor Fast prototyping

Next generation xDSL and PLC

Security/Safety & Quality of Service

security/safety issues related to life-line support, remote powering and maintenance network traffic models spectrum regulation and management bonding & inverse multiple access higher layer protocols

Building blocks & chipsets

line drivers high speed converters integrated analogue front-ends digital building blocks active splitters

Multi-standard platform demonstrators

integrated access platforms and gateways demonstration and tests Real time VDSL loop emulator based on digital techniques

next generation xDSL & PLC systems and architectures novel advanced DSP algorithms advanced error correction codes for improved performances

Design houses and chipmakers

DS2, Target, ST, Thomson

Operators
France Telecom

Co-emulation

. Activities in WP1

Enabling design methodologies and tools for the design of flexible Wireline IPs and SoC
Contributors: Contributors: Target (B), ST (B), ESAT-KUL (B), IMSE-CNM (SP), DS2 (SP) ESATIMSEResponsible: Responsible: Target (B) Activities: Activities: A.1.1: Methodologies and tools for soft generation of analog IP blocks A.1.2: Methodologies and tools for design of versatile Application Specific Signal Processor (ASSP) A.1.3: Methodologies and tools for fast-prototyping and co-emulation fastco-

Graphical debugger on host computer

API (Tcl/TK, C++) ISS kernel JTAG bit streams TCP/IP socket

JTAG ctrler

Hardware
Debug ctrler Target core

On chip debugging support . Activities in WP2

Co-simulation environment

Next generation xDSL and PLC, new advanced DSP algorithms and error correction codes for DSL and PLC improved performances
Contributors: Contributors: DS2 (SP), ST (B), Ericsson (Sw), France Telecom R&D (F), LTH (Sw), ENS (F), Thomson (B), LEA (F) Responsible: Responsible: DS2 (Spain) (Spain) Activities: Activities: A2.1: Study of next generation xDSL systems and architectures A2.2: Study of next generation PLC systems and architectures A.2.3: Study of new advanced DSP algorithms and advanced Error correction codes for DSL and PLC improved performances
8
dB

Tester Noise File Twisted copper wire Noise injection (ANSI norm) Noise Generator50 1k liaison SDSL Customer SDSL modem 120 1k

Impulsive noise injection for xDSL transmission

Data rate
[Mbits/sec]
60
25 SNR with RFI loop 54 30

20

15

VDSL ADSL2 ADSL ADSL

2
1 km 2 km

ADSL2+

10

5 24 48 dec24 130 140 150 160 170 tone 180 190 200 210

SHDSL
3 km 4 km 5 km

ADSL/R

0 120

RFI cancellation by powerfull PTEQ

In-home scenario for next generation PLC

STMicroelectronics Belgium N.V. Industriepark Keiberg Excelsiorlaan 44-46 B-1930 Zaventem, Belgium http://www.st.com MEDEA+ Forum 2004, 23-24 November, Paris, France

For further information, please contact Project Leader: Patrick Wouters patrick.wouters@st.com With thanks to all MIDAS partners