NXP LPC3250 Featuring ARM9 With Ethernet, USB, and LCD: EPC - Embedded Platform Concept

EPC Embedded Platform Concept
EPC-PROC02-NXP-LPC3250 Processor Module Featuring NXP LPC3250 ARM9 Processor
NXP LPC3250 featuring ARM9 with Ethernet, USB, and LCD

For multimedia devices and protocol converter supported by Linux or Windows Features of the NXP LPC3250 Processor Module EPC-PROC02-NXP-LPC3250 NXP LPC3250 Processor ARM926EJ-S core (up to 266MHz) Vector Floating Point coprocessor 10/100Mb Ethernet MAC USB Host / Device / OTG Interface TFT interface (routed to AddOn-Connector) SD-Card and NAND Flash Interface Up to 7 UART, SPI, IC, IS, PWM, and ADC 4MByte SPI Flash (bootable) 64MByte NAND Flash (bootable) 64MByte SDRAM National Semiconductors DP83848 Ethernet PHY ISP1301/2 USB PHY with 500mA USB power switch NXP UDA1380 IS Audio Interface (Headphone and Line-In) Introduction The NXP LPC3250 ARM9 Processor Module is built around NXPs latest ARM9 derivative, which perfectly combines a multi-interface ARM9 microcontroller approach, high performance architecture with floating point coprocessor and low overall system costs. Some of the most interesting interfaces are the 10/100 Mb Ethernet MAC, the USB Host/Device/OTG controller with dedicated PLL and the Display Controller supporting TFT and STN panels with up to XGA (1024 x 768) resolution. Each of these controllers provides a dedicated DMA controller for maximum efficiency of data transfer independently of the CPU. In addition, several serial interfaces are available seven UARTs (four with fractional baud rate generation, one with IrDA support, three with high-speed support, all with 64-byte FIFO), two SPI, two IC, two IS and two SSP controllers (also supporting 4-wire SSI, MicroWire and SPI). An appreciable number of these interfaces are available on the boards connectors. A major strength of LPC3250 is the flexible boot configuration, which auto-senses the available memories and boot ports. This includes NAND Flash, SPI memory, USB and UART. All these boot options are available on the Processor Module. The Processor Module supports several software options: Linux (royalty free from ARROW/Emlix) or Windows CE possible Low Level Drivers for use without OS (royalty free) Application Examples All components used on the board are available from Arrow.
ARROW Technical Marketing Rev. 2.0.1
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Table of Contents
1. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. LPC3250 PROCESSOR MODULE BLOCK DIAGRAM .............................................3 LPC3250 PROCESSOR MODULE BLOCK DIAGRAM .............................................3 OPERATIONAL DESCRIPTION.................................................................................6 PROCESSOR MODULE CONNECTORS...................................................................7 BOARD DESCRIPTION............................................................................................13 SCHEMATIC DIAGRAM ...........................................................................................14 LAYOUT....................................................................................................................23 PARTS LIST .............................................................................................................27 ORDERING INFORMATION.....................................................................................29 REVISION TRACKING .............................................................................................29 KNOWN ERRATA OF HARDWARE REVISION A3.................................................29
2010 by Arrow Author: Klaus Kohl-Schpe All rights reserved. No part of this manual shall be reproduced, stored in a retrieval system, or transmitted by any means, electronic, mechanical, photocopying, desktop publishing, recording, or otherwise, without written permission from the publisher. No patent liability is assumed with respect to the use of the information contained herein. While every precaution has been taken in the preparation of this document, the publisher and author assume no responsibility for errors or omissions. Neither is any liability assumed for damages resulting from the use of the information contained herein. All terms mentioned in this manual that are known to be trademarks or service marks are listed below. In addition, terms suspected of being trademarks or service marks have been appropriately capitalized. Arrow cannot attest to the accuracy of this information. Use of a term in this document should not be regarded as affecting the validity of any trademark or service mark.
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1.
LPC3250 Processor Module Block Diagram

NAND 64MByte SDRAM 64MByte SPI Flash 4MByte
Memory Interface
LPC3250 Processor Module
UDA1380 Codec DP83848 ETH. PHY ISP1302 USB PHY
Headphone Line-In Ethernet 10/100 USB OTG/Dev. UARTs LCD
Audio
Latch
LCD Interfac
PWM
T o p C o n n e c t o r
B o t t o m C o n n e c t o r
Ethernet 10/100 USB OTG UART

LED Reset Boot Option
LPC3250 Processor
Reset
SD-Card SPI IC IRQ0-2 QE Key 0-5 ADIN 0-4 Reset-Out 0-2 Reset-In
Keyboard
JTAG Debug Interface
TPS3838 (Reset)
Extension Board 0 Extension Board 1 Extension Board 2

Power 12V/5V/3.3V
1.2V
3.3V
ADP1710
Fig. 1: LPC3250 Processor Module block diagram Power Supply This module uses only 3.3V from the Base Board connector. The second voltage needed for the LPC3250 core is realized on-with an Analog Devices ADP1710 low drop linear regulator. One exception is the USB Host/OTG, which uses the 5V power line to supply the USB device with up to 500mA. Memory and boot options There are three different memories realized on this board: * 4MByte SPI Flash (Numonyx M25P(X)32) on SPI0 * 64MBye SDRAM (Micron MT48LC32M16) using dynamic CS0 * 64MByte NAND-Flash (Numonyx NAND512W3A2) on NAND interface Depending on boot configuration, it is possible to boot from serial interfaces or from on-board memory (first SPI Flash, then external static memory, then NAND Flash). In addition to the SDRAM memory, static memory placed on the Add-On Module on top of these Processor Modules may be used. All required signals, including CS0 and CS1, are routed to the top connector. Ethernet The LPC3250 Ethernet MAC is connected with the DP83848 National Semiconductors MiniPHYter. The output of these Ethernet PHYs is connected to the upper RJ45 Ethernet connector.
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EPC-PROC02-NXP-LPC3250 Processor Module Featuring NXP LPC3250 ARM9 Processor USB For USB Host and OTG an external USB PHY must be used for the LPC3250. On this board we realized the USB Host/Device/OTG interface with an ST/Ericson ISP1301/2 connected to the second USB Device/OTG connector on the Base Board. By using an adapter, USB Host can be realized. Because of the 50mA limit for the ISP1301/2, we add an external 500mA power switch controlled by the ISP1301/2. Audio Interface The audio interface is realized with a NXP UDA1380 Audio Codec connected to the IS and the IC1 interface of the processor (TWIM on EPC). Along with Line-In and Line-Out, it supports a stereo headphone output routed to the Base Board. TFT Interface The TFT interface is available on the Add-On Module connector. The processor supports up to 24 bits. The PWM output cannot be used at the same time because of pin sharing between LCD and PWM, but by controlling a latch it is possible to route this pin to Extension Board PWM lines. UART Three UARTs are used by the Embedded Platform: * UART5 (with handshakes) is normally connected to the RS232 connector on the Base Board * UART1 is normally connected to UART0 of the EPC Extension Boards * UART2 is permanently connected to UART1 of the EPC Extension Boards The system can be booted via the RS232 because UART5 is used by the boot loader. If the TFT interface is not used, then it is possible to access UART3 and 4 with our Add-On-Module. SPI The SPI0 interface is used for the Extension Board SPI. Chip selects for SPI come from GPO. We use three inverters for CS0, 1 and 3 because the default level of these pins is low and an external SPI device on the Extension Board may block the SPI boot loader which uses GPIO_05.
Function SPI_CS0 SPI_CS2 SPI_SS Port GPO_01 (with inverter) GPO_05 EMC_D[27] / Port P2 - Bit 8 Function SPI_CS1 SPI_CS3 Port GPO_04 (with inverter) GPO_11 (with inverter)
IC In revision A2 both IC interfaces are available. The system IC (TWIS - use IC2 interface) is routed to the IC hub on the Base Board. The module IC (TWIM - use IC1 interface) is directly routed to all Extension Boards. Pull-up resistors for the IC are on the Base Board. SD-Card The SD-Card interface is connected with the memory card (MS) interface of the processor. Up to 4 bits can be used. By closing two jumpers on the Base Board PWM7 can be connected with the CD pin and PWM6 with the WP pin of the SD-Card. But this feature only works if the PWM pins is used as input, Pull-downs for PWM6 and PWM7 are disabled, and the LCD/PWM latch is closed.
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Keyboard The Base Board keys are connected with GPI pins of the processor:
Function Key 0 (Up) Key 2 (Right) Key 4 (Enter) Port GPIO_07 GPIO_28 GPIO_18 Function Key 1 (Down) Key 3 (Left) Key 5 (Exit) Port GPIO_19 GPIO_16 GPIO_21
PWM By using a latch between LCD lines and the Extension Board PWM pins and connecting the PWM pins with spare lines on the memory data bus (EMC_D[19] D[26]), two different configurations can be used. To keep the PWM lines during reset at low level we add a 10KOhm pull-down to each line. The latch is controlled by GPO20 of the LPC3250. Standard configuration (use port lines LCD is usable) The latch between LCD and PWM is closed (default) and the LPC3250 - Port 2 [0...7] are switched to output. The LEDs on the Base Board directly reflect the status of the PWM ports.
Function PWM0 PWM2 PWM4 PWM6 Port P2_00 P2_02 P2_04 P2_06 Function PWM1 PWM3 PWM5 PWM7 Port P2_01 P2_03 P2_05 P2_07
Motor Control application (use PWM LCD is not active) The first 6 output pins of the EPC Extension Boards are connected with the LPC3250 Motor Control PWM. PWM6 and 7 are connected to PWM_OUT 1 and 2.
EPC PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 PWM MC0A MC0B MC1A MC1B MC2A MC2B PWM_OUT1 PWM_OUT2 Port P3_18 P3_16 P3_15 P3_13 P3_12 P3_10 PWM1_CTRL - Bit 30 PWM2_CTRL - Bit 30 Alternative LPCLP LPCENAB/LCDM LCDFP LCDDCLK LCDLE LCDPWR LCDVD[16] LCDVD[19]
Analog Input The LPC3250 has a 10bit A/D converter normally used for a touch screen. All five pins are directly routed to the analog inputs of the Extension Board.
EPC AIN0 AIN1 AIN2 AIN3 AIN4 LPC3250 ANIN0 / TS_XM ANIN1 / TS_YM ANIN2 / TS_AUX_IN TS_XP TS_YP
Warning: Delivers VddTS (no input) Warning: Delivers VddTS (no input)
Only three analog inputs (ADIN0-2) are available on the Extension Board. AIN3 and 4 are only usable for an external touch function. Because of the 3.3V system voltage these analog inputs should be in the range of 0.0V to 3.3V.
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EPC-PROC02-NXP-LPC3250 Processor Module Featuring NXP LPC3250 ARM9 Processor Reset Output and Interrupts The reset signals for three Extension Boards are realized by GPO lines (Default: Low):
Function GPO_14 GPO_17 GPO_23 Port Reset for EB0 Reset for EB1 Reset for EB2
Interrupt inputs from Extension Boards use GPI lines:

Function GPI_03 GPI_04 GPI_05 Port IRQ0 IRQ1 IRQ2
For the quadrature encoder inputs some lines from the upper memory data signals are used:
Function Port P2 - Bit 10 Port P2 - Bit 11 Port P2 - Bit 12 Port IRQA IRQB IRQC
The power enable pins on the Base Board (from DC/DC Module) are not used. Pull-up for these lines is realized on the DC/DC Board and not required on the Processor Module.
2.
Operational description
The board contains electrostatic sensitive devices. The User must observe all necessary precautions to prevent ESC damage to the board. Before touching the board, the user must use an earthed wrist strap.
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3.
Processor Module Connectors
On the Processor Module all signals are available on the top connectors. The bottom connectors retain only those signals required for the EPC Base Board, such as power supply, Ethernet, USB, and all Extension Module signals. To provide an overview of the pin descriptions of these in a single place, all the information is compiled in the separate PDF or Excel document entitled All Connectors for the Reference Platform Module (version as of 12/01/2009). CPU Left Connector Left Side (Bottom and Top)
Pin 159 157 155 153 151 149 147 145 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 107 105 103 101 99 97 95 93 91 89 87 85 83 81 79 77 75 73 71 69 67 65 Group Reset Reset Reset Reset Reset PWR AIN AIN AIN AIN AIN AIN AIN AOUT AOUT PWR PWM PWM PWM PWM PWM PWM PWM PWM QE PWR QE QE IRQ IRQ IRQ UART2 UART2 UART1 UART1 PWR UART0 UART0 UART0 UART0 Symbol BOOTM RESET_OUT_2 RESET_OUT_1 RESET_OUT_0 RESET_IN DGND AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 AGND AOUT1 AOUT0 DGND PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 QE_P2/IRQC DGND QE_P1/IRQB QE_I/IRQA IRQ2 IRQ1 IRQ0 UART2_RX UART2_TX UART1_RX UART1_TX DGND UART0_RTS UART0_CTS UART0_RX UART0_TX Dir (CPU) I O O O I PWR I or I/O I or I/O I or I/O I or I/O I or I/O I or I/O PWR O or I/O O or I/O PWR O or I/O O or I/O O or I/O O or I/O O or I/O O or I/O O or I/O O or I/O I PWR I I I I I I O I O PWR O I I O Description Boot Mode UART/SPI-Rom Reset to Extension Boards 2 Reset to Extension Boards 1 Reset to Extension Boards 0 Reset from Base Board GND reserved Not available on EPC-PROC02-NXP-LPC3250 Connected to touch screen controller TS_XP Connected to touch screen controller TS_YP Analog Input 2 (touch screen controller TS_AUX_IN) Analog Input 1 (touch screen controller TS_YM) Analog Input 0 (touch screen controller TS_XM) Analog Ground Analog Output 1, GPIO 9 Analog Output 0, GPIO 8 GND reserved PWM 7, GPIO 7 (PWM_OUT2 - optional SD-Card CD) PWM 6, GPIO 6 (PWM_OUT1 - optional SD-Card WP) PWM 5, GPIO 5 (MC2B) PWM 4, GPIO 4 (MC2A) PWM 3, GPIO 3 (MC1B) PWM 2, GPIO 2 (MC1A) PWM 1, GPIO 1 (MC0B) PWM 0, GPIO 0 (MC0A) Quadrature Encoder 2 Input (P2 - Pin 12) GND reserved Quadrature Encoder 1 Input (P2 - Pin 11) Quadrature Encoder Index (P2 - Pin 10) Interrupt to CPU from Extension Board 2 (GPI_05) Interrupt to CPU from Extension Board 1 (GPI_04) Interrupt to CPU from Extension Board 0 (GPI_03) UART2 Data from Base Board to CPU (UART2_RX) UART2 Data from CPU to Base Board (UART2_TX) UART1 Data from Base Board to CPU (UART1_RX) UART1 Data from CPU to Base Board (UART1_TX) GND reserved UART0 Ready To Send (UART3_TX) UART0 Clear To Send (GPIO_01) UART0 Data from Base Board to CPU (UART5_RX = Boot) UART0 Data from CPU to Base Board (UART5_TX = Boot)
PWR TWIM TWIM SPI
DGND TWIM_SDA TWIM_SCL SPI_CS3
PWR OC OC O
GND reserved IC Data for Ext. Module (I2C1_SDA) IC Clock for Ext. Module (I2C1_SCL) SPI Chip Select 3 for AddOn Module (inverted GPO_11)
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Pin 63 61 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 Group SPI SPI SPI SPI SPI SPI PWR SPI SPI DAUD0 DAUD0 DAUD0 DAUD0 DAUD0 DAUD0 DAUD0 PWR DAUD0 DGND TWIS TWIS PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR Symbol SPI_CS2 SPI_CS1 SPI_CS0 SPI_MISO SPI_MOSI SPI_SCK DGND SPI_SS /CSROM DAUD0_RP DAUD0_TP DAUD0_RS DAUD0_TS DAUD0_FSR DAUD0_FST DAUD0_CKR DGND DAUD0_CKT SYSPRG TWIS_SDA TWIS_SCL PWREN2 PWREN1 PWREN0 V033 V033 DGND DGND GND5 V050 GND12 V120 Dir (CPU) O O O I O I/O PWR I I Description SPI Chip Select for Ext. Module 2 (GPO_05) SPI Chip Select for Ext. Module 1 (inverted GPO_04) SPI Chip Select for Ext. Module 0 (inverted GPO_01) SPI Master In (SPI1_DATIN/MISO0) SPI Master Out (SPI_DATIO/MOSI) SPI Clock (SPI1_CLK/SCK0) GND reserved SPI Slave Select (EMC_D[26] / Port 2 - Bit 8) Chip Select from SPI-ROM (Boot Source - GPIO_05/SSEL0) Digital Audio Data Receive Primary (I2S1RX_SDA) Digital Audio Data Transmit Primary (I2S1TX_SDA) Not available on EPC-PROC02-NXP-LPC3250 Not available on EPC-PROC02-NXP-LPC3250 Digital Audio Receive Frame Sync (I2S1RX_WS) Digital Audio Transmit Frame Sync (I2S1TX_WS) Digital Audio Receive Clock (I2S1RX_CLK) GND reserved Digital Audio Transmit Clock (I2S1TX_CLK) GND on EPC-PROC02-NXP-LPC3250 TWI Data for system (I2C2_SDA) TWI Clock for system (I2C2_SCL) Not available on EPC-PROC02-NXP-LPC3250 Not available on EPC-PROC02-NXP-LPC3250 Not available on EPC-PROC02-NXP-LPC3250 3.3V - Processor Module supply (3.3V I/O and 1.2V core) 3.3V - Processor Module supply (3.3V I/O and 1.2V core) GND reserved GND GND (for 5V) 5.0V - only used to supply the USB device GND (for 12V) 12.0V - not used
PWR PWR OC OC
PWR PWR PWR PWR PWR PWR PWR PWR
CPU Left Connector Right Side (Top and Bottom)

Pin 160 158 156 154 152 150 148 146 144 142 140 138 136 134 132 130 128 126 124 122 120 118 Group AAUDIO AAUDIO AAUDIO AAUDIO AAUDIO PWR AAUDIO AAUDIO AAUDIO AAUDIO AAUDIO SDMMC SDMMC SDMMC SDMMC PWR SDMMC SDMMC SDMMC SDMMC SDMMC SDMMC Symbol MIC_IN_L MIC_IN_R GNDA LINE_IN_L LINE_IN_R DGND LINE_OUT_L LINE_OUT_R GNDA HDPH_OUT_L HDPH_OUT_R SDMMC_D2 SDMMC_D3/CS SDMMC_CMD/DI SDMMC_CLK/SCLK DGND SDMMC_D0/DO SDMMC_D1 SDMMC_D7 SDMMC_D6 SDMMC_D5 SDMMC_D4 Dir (CPU) I I PWR I I PWR O O PWR O O Description Not available on EPC-PROC02-NXP-LPC3250 Microphone Input Right Audio Ground (not connected to system ground) Audio Line In Left Audio Line In Right GND reserved Audio Line Out Left Audio Line Out Right Audio Ground (not connected to system ground) Headphone Output Left Headphone Output Right SD-Card Data Bit 2 (MS_DIO2) SD-Card Select (MS_DIO3) SD-Card Data Input (MS_BS) SD-Card Clock (MS_SCKL) GND reserved SD-Card Data Bit 0 (MS_DIO0) SD-Card Data Bit 1 (MS_DIO1) Not available on EPC-PROC02-NXP-LPC3250 Not available on EPC-PROC02-NXP-LPC3250 Not available on EPC-PROC02-NXP-LPC3250 Not available on EPC-PROC02-NXP-LPC3250
PWR
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Pin 116 114 112 110 108 106 104 102 100 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 Group Symbol Dir (CPU) Description
PWR
DGND
PWR
GND reserved
PWR
DGND
PWR
GND reserved
PWR
DGND
PWR
GND reserved
KEY KEY KEY KEY PWR KEY KEY
KEY5 KEY4 KEY3 KEY2 DGND KEY1/IRQK1 KEY0/IRQK0
I PWR I I
Push Button 5 (Exit key) (GPI_21) Push Button 4 (Enter key) (GPI_18) Push Button 3 (Left key) (GPI_16) Push Button 2 (Right key) (GPI_28) GND reserved Push Button 1, Rotary Encoder 1 (Down key) (GPI_19) Push Button 0, Rotary Encoder 0 (Up key) (GPI_07)
PWR
DGND
PWR
GND reserved
V033 V033 DGND DGND GND5 V050 GND12 V120
3.3V - Processor Module supply (3.3V I/O and 1.2V core) 3.3V - Processor Module supply (3.3V I/O and 1.2V core) GND reserved GND GND (for 5V) 5.0V - only used to supply the USB device GND (for 12V) 12.0V - not used
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EPC-PROC02-NXP-LPC3250 Processor Module Featuring NXP LPC3250 ARM9 Processor CPU Right Connector Left Side (SRAM interface only on top connector) Bottom connector supports only the second USB (OTG/Device) interface and all ground lines. In addition there is a SRAM interface with 24 address lines, 16 data lines, and two chip selects available at the top connector.
Pin 159 157 155 153 151 149 147 145 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 107 105 103 101 99 97 95 93 91 89 87 85 83 81 79 77 75 73 71 69 67 65 63 61 59 57 55 Group MPT MPT MPT MPT MPT PWR MPT MPT MPT MPT MPT MPT MPT MPT MPT PWR MPT MPT MPT MPT MPT PWR MPT Symbol MPT_D15 MPT_D14 MPT_D13 MPT_D12 MPT_D11 DGND MPT_D10 MPT_D9 MPT_D8 MPT_D7 MPT_D6 MPT_D5 MPT_D4 MPT_D3 MPT_D2 DGND MPT_D1 MPT_D0 MPT_CS1 MPT_CS0 MPT_RW/WR DGND MPT_/OE/RD Dir (CPU) I/O I/O I/O I/O I/O PWR I/O I/O I/O I/O I/O I/O I/O I/O I/O PWR I/O I/O O O O PWR O Description Memory Port Data Bit 15 Memory Port Data Bit 14 Memory Port Data Bit 13 Memory Port Data Bit 12 Memory Port Data Bit 11 GND reserved Memory Port Data Bit 10 Memory Port Data Bit 9 Memory Port Data Bit 8 Memory Port Data Bit 7 Memory Port Data Bit 6 Memory Port Data Bit 5 Memory Port Data Bit 4 Memory Port Data Bit 3 Memory Port Data Bit 2 GND reserved Memory Port Data Bit 1 Memory Port Data Bit 0 Memory Port Chip Select 1 (EMC_CS1) Memory Port Chip Select 0 (EMC_CS0) Memory Port Write Enable (EMC_WR) Memory Port Output or Read Enable (EMC_OE)
PWR
DGND
PWR
GND reserved
MPT MPT MPT MPT MPT MPT MPT PWR MPT MPT MPT MPT MPT MPT MPT MPT PWR MPT MPT MPT MPT MPT MPT MPT MPT
MPT_A23 MPT_A22 MPT_A21 MPT_A20 MPT_A19 MPT_A18 MPT_A17 DGND MPT_A16 MPT_A15 MPT_A14 MPT_A13 MPT_A12 MPT_A11 MPT_A10 MPT_A9 DGND MPT_A8 MPT_A7 MPT_A6 MPT_A5 MPT_A4 MPT_A3 MPT_A2 MPT_A1
O O O O O O O PWR O O O O O O O O PWR O O O O O O O O
Memory Port Address Bit 23 Memory Port Address Bit 22 Memory Port Address Bit 21 Memory Port Address Bit 20 Memory Port Address Bit 19 Memory Port Address Bit 18 Memory Port Address Bit 17 GND reserved Memory Port Address Bit 16 Memory Port Address Bit 15 Memory Port Address Bit 14 Memory Port Address Bit 13 Memory Port Address Bit 12 Memory Port Address Bit 11 Memory Port Address Bit 10 Memory Port Address Bit 9 GND reserved Memory Port Address Bit 8 Memory Port Address Bit 7 Memory Port Address Bit 6 Memory Port Address Bit 5 Memory Port Address Bit 4 Memory Port Address Bit 3 Memory Port Address Bit 2 Memory Port Address Bit 1
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Pin 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 Group MPT PWR CLK CLK Symbol MPT_A0 DGND SYSCLKI SYSCLKO Dir (CPU) O PWR I O Description Memory Port Address Bit 0 GND reserved System Clock Input System Clock Output
PWR
DGND
PWR
GND reserved
PWR USB1 USB1 USB1 USB1 USB1
DGND USB1_GND USB1_ID USB1_D USB1_/D USB1_VBUS
PWR PWR O I/O I/O PWR
GND reserved Second USB GND - connected to system ground Second USB ID - connected to ISP1301/2 Second USB Data - connected to ISP1301/2 Second USB /Data - connected to ISP1301/2 Second USB Bus Voltage - connected to power switch
CPU Right Connector Right Side (TFT interface only on top connector) Bottom connector supports only the first Ethernet interface (10/100MBaud) and all ground lines. In addition there is the LCD interface at the top connector.
Pin 160 158 156 154 152 150 148 146 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 Group PWR ETH0 ETH0 ETH0 ETH0 PWR ETH0 ETH0 ETH0 ETH0 ETH0 ETH0 ETH0 Symbol DGND ETH0_LED1 ETH0_LED0 ETH0_/D4 ETH0_D4 DGND ETH0_/D3 ETH0_D3 ETH0_/D2 ETH0_D2 ETH0_/D1 ETH0_D1 ETH0_TCT Dir (CPU) PWR Description First Ethernet LED1 (EMC_D[28] / Port 2 - Pin 9) First Ethernet LED0 - connected with DP83848 Not available on EPC-PROC02-NXP-LPC3250 Not available on EPC-PROC02-NXP-LPC3250 GND reserved Not available on EPC-PROC02-NXP-LPC3250 Not available on EPC-PROC02-NXP-LPC3250 TD- - connected with DP83848 TD+ - connected with DP83848 RD- - connected with DP83848 RD+ - connected with DP83848 Connected to 3.3V
PWR
PWR
DGND
PWR
GND reserved
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Pin 110 108 106 104 102 100 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 Group PWR VID0 VID0 VID0 VID0 VID0 VID0 VID0 VID0 VID0 PWR VID0 VID0 VID0 VID0 VID0 VID0 VID0 VID0 PWR VID0 VID0 VID0 VID0 VID0 VID0 VID0 VID0 VID0 PWR VID0 VID0 VID0 Symbol DGND VID0_D23 VID0_D22 VID0_D21 VID0_D20 VID0_D19 VID0_D18 VID0_D17 VID0_D16 VID0_D15 DGND VID0_D14 VID0_D13 VID0_D12 VID0_D11 VID0_D10 VID0_D9 VID0_D8 VID0_D7 DGND VID0_D6 VID0_D5 VID0_D4 VID0_D3 VID0_D2 VID0_D1 VID0_D0 VID0_DEN VID0_RST DGND VID0_CLK VID0_HS VID0_VS Dir (CPU) PWR O O O O O O O O O PWR O O O O O O O O PWR O O O O O O O Description GND reserved First Video Data 23 First Video Data 22 First Video Data 21 First Video Data 20 First Video Data 19 First Video Data 18 First Video Data 17 First Video Data 16 First Video Data 15 GND reserved First Video Data 14 First Video Data 13 First Video Data 12 First Video Data 11 First Video Data 10 First Video Data 9 First Video Data 8 First Video Data 7 GND reserved First Video Data 6 First Video Data 5 First Video Data 4 First Video Data 3 First Video Data 2 First Video Data 1 First Video Data 0 First Video Data enable (LCDENAB) First Video Reset (LCDPWR) GND reserved First Video Clock (LCDDCLK) First Video Horizontal Sync (LCDLP) First Video Vertical Sync (LCDFP)
PWR
PWR
DGND
PWR
GND reserved
PWR
DGND
PWR
GND reserved
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4.
Board Description
Add-On Module Connectors
JTAG Connector
LCD/PWM Latch SD-RAM 32M*16
Reset
LPC3250 Processor
NAND 512Mb
13MHz Inverter 32.768kHz
25MHz Ethernet PHY
Audio Capacitors
Audio Codec
USB Powerswitch
PWM6/7 Pull-Down Jumper
Serial Flash 4M*8
USB PHY
The pinning of all connectors to the Base Board and Add-On Module is listed above.
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LPC3250 Spoerle Processor Module (LPC32SPM-A3) EPC-PROC02-NXP-LPC3250

[1] [2] [3] [4] [5] [6] [7] [8] [9] Contents PSM Connectors BOT PSM Connectors TOP LPC3250 - Control, Peripherals, GPIO LPC3250 - SDRAM, LCD, NAND-Flash LPC3250 - Power SDRAM, NAND-Flash USB-OTG, Audio-Codec, Ethernet Power, Reset
This document may not be passed on, duplicated or its contents utilized, unless expressly permitted. Violating this stipulation will result in the liability to pay damages. All rights reserved in case of a patent registration or registered design.
A3 / 25.02.2010 / Ma
CONTENTS
Designed by Hitex Development Tools
+5V
+5V
X201
X200
PWREN0 PWREN1 PWREN2 I2S I2C2_SCL I2C2_SDA I2S1TX_CLK I2S1RX_CLK I2S1TX_WS I2S1RX_WS I2S1TX_SDA I2S1RX_SDA SSEL0
SPI0 SPI_SS
SCK0 MOSI0 MISO0 SPI_CS0 SPI_CS1 SPI_CS2 SPI_CS3 I2C1_SCL I2C1_SDA
U5_RX U5_TX U5_GPIO_CTS U5_GPIO_RTS 1K/0603 U1_RX U1_TX U2_RX U2_TX IRQ0 IRQ1 IRQ2 IRQA IRQB IRQC PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 R13
GND PWM[0..7]
ADIN0 ADIN1 ADIN2 ANIN3 ANIN4 RESET_N RESOUT_0 RESOUT_1 RESOUT_2 SERVICE_N
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160
USB_VBUS USB_DUSB_D+ USB_ID
KEY0 KEY1 KEY2 KEY3 KEY4 KEY5
MS_DIO1 MS_DIO0 MS_SCLK MS_BS MS_DIO3 MS_DIO2 VOUTRHP VOUTLHP VOUTR VOUTL VINR VINL VINM GND
+3V3
SD-CARD
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160
+12V
+12V
+3V3
+3V3
ETH0 RD+ RDTD+ TD-
AGND
LED/AN0 LED1_LNK
TYCO-1-5316562-1
TYCO-1-5316562-1
GND
GND GND12 GND5
GND12 GND GNDA GND5 This document may not be passed on, duplicated or its contents utilized, unless expressly permitted. Violating this stipulation will result in the liability to pay damages. All rights reserved in case of a patent registration or registered design.
A2 / 07.09.2009 / Ma
PSM Connectors BOT
+5V
+5V
X301
X300
PWREN0 PWREN1 PWREN2 I2S I2C2_SCL I2C2_SDA I2S1TX_CLK I2S1RX_CLK I2S1TX_WS I2S1RX_WS I2S1TX_SDA I2S1RX_SDA SSEL0
SPI0 SPI_SS
SCK0 MOSI0 MISO0 SPI_CS0 SPI_CS1 SPI_CS2 SPI_CS3 I2C1_SCL I2C1_SDA
U5_RX U5_TX U5_GPIO_CTS U5_GPIO_RTS U1_RX U1_TX U2_RX U2_TX IRQ0 IRQ1 IRQ2 IRQA IRQB IRQC PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7
PWM[0..7]
ADIN0 ADIN1 ADIN2 ANIN3 ANIN4 RESET_N RESOUT_0 RESOUT_1 RESOUT_2 SERVICE_N
TYCO-6-5316564-1
GND5
GNDA
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160
USB_VBUS USB_DUSB_D+ USB_ID
SYSCLKO
R300 SYSCLKI
22R/0603
EMC_A[0..23] KEY0 KEY1 KEY2 KEY3 KEY4 KEY5 EMC_A0 EMC_A1 EMC_A2 EMC_A3 EMC_A4 EMC_A5 EMC_A6 EMC_A7 EMC_A8 EMC_A9 EMC_A10 EMC_A11 EMC_A12 EMC_A13 EMC_A14 EMC_A15 EMC_A16 EMC_A17 EMC_A18 EMC_A19 EMC_A20 EMC_A21 EMC_A22 EMC_A23 EMC_CTRL EMC_CS_N EMC_D[0..15] SD-CARD MS_DIO1 MS_DIO0 MS_SCLK MS_BS MS_DIO3 MS_DIO2 VOUTRHP VOUTLHP VOUTR VOUTL VINR VINL VINM
EMC_OE_N EMC_WR_N EMC_CS0_N EMC_CS1_N EMC_D0 EMC_D1 EMC_D2 EMC_D3 EMC_D4 EMC_D5 EMC_D6 EMC_D7 EMC_D8 EMC_D9 EMC_D10 EMC_D11 EMC_D12 EMC_D13 EMC_D14 EMC_D15
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160
+12V
+12V
+3V3
+3V3
LCD_CTRL LCDFP LCDLP LCDDCLK LCDPWR LCDENAB LCDVD0 LCDVD1 LCDVD2 LCDVD3 LCDVD4 LCDVD5 LCDVD6 LCDVD7 LCDVD8 LCDVD9 LCDVD10 LCDVD11 LCDVD12 LCDVD13 LCDVD14 LCDVD15 LCDVD16 LCDVD17 LCDVD18 LCDVD19 LCDVD20 LCDVD21 LCDVD22 LCDVD23 LCDVD[0..23]
+3V3
ETH0 RD+ RDTD+ TD-
AGND
LED/AN0 LED1_LNK
TYCO-6-5316564-1
GND GND GND12 GND5 GND12 GND
GND
A2 / 07.09.2009 / Ma
PSM Connectors TOP
+3V3
+3V3
R400 10K/0603 U401

4 VCC E/D 1
10K/0603
+3V3 10K/0603
10K/0603
SYSCLKI U400CTRL
OUT 3 T17 R15 P16 P17 SYSX_IN SYSX_OUT RTCX_IN RTCX_OUT RESET_N RESOUT_N DBGEN ONSW SERVICE_N TST_CLK2 H17 H14 G18 J16 NC NC NC B17 U2 U17
C400 10P/0603
2 GND
10K/0603
+3V3
R1
R2
R3
10K/0603
R4
KC3225A-C3_13MHz R8 GND POR_N SERVICE_N TRST_N TCK TMS TDI
X1
1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20
+3V3
Q400 32.7KHZQ/S
M14 G14 C15
C3 100N/0603
G4 M15 C6
RESOUT_N
SYSCLKO
TRST_N TDI TMS TCK RTCK TDO RESET_N 10K/0603
JTAG_NTRST JTAG_TCK JTAG_RTCK JTAG_TMS JTAG_TDI JTAG_TDO
H18 J15
RTCK TDO
XSE_2X10_254 GND
LPC3250/B296 C401 12P/0603 GND C402 12P/0603 GND R5 GND I2S U400PERIPH U1_RX U1_TX U2_RX U2_TX U5_RX U5_TX USB U5_GPIO_RTS USB_I2C_SCL USB_I2C_SDA USB_DAT_VP USB_SE0_VM USB_OE_TP_N USB_ATX_INT_N MS_SCLK MS_BS MS_DIO0 MS_DIO1 MS_DIO2 MS_DIO3 I2S1TX_CLK I2S1TX_SDA I2S1TX_WS
K15 K16 K18 K17 F18 H15 J17 G16 E5 E6 D5 C5 D6 C4 B7 A6 A8 A7 B8 C8 A4 E7 B4 U1_RX U1_TX U2_RX/U3_DSR U2_TX/U3_DTR U5_RX U5_TX U3_TX U6_IRTX USB_I2C_SCL USB_I2C_SDA USB_DAT_VP USB_SE0_VM USB_OE_TP_N USB_ATX_INT_N MS_SCLK MS_BS MS_DIO0 MS_DIO1 MS_DIO2 MS_DIO3 I2S1TX_CLK/MAT3.0 I2S1TX_SDA/MAT3.1 I2S1TX_WS/CAP3.0 ENET_MDIO ENET_MDC ENET_CRS ENET_RXD0 ENET_RXD1 ENET_TXD0 ENET_TXD1 ENET_RX_CLK ENET_RX_DV ENET_RX_ER ENET_TX_CLK ENET_TX_EN ENET_TX_ER KEY_ROW1/ENET_TXD2 KEY_ROW2/ENET_TXD3 SPI1_CLK/SCK0 SPI_DATIO/MOSI0 SPI1_DATIN/MISO0 GPIO_05/SSEL0 I2C1_SCL I2C1_SDA I2C2_SCL I2C2_SDA C11 D9 D18 G15 F16 C17 C18 E16 B16 D17 F15 D16 E15 E14 F14 C9 B9 C10 E9 A5 B6 A3 E4
U400GPIO I2S1RX_SDA
C16 C14 F4 E13 N16 C7 D13 E12 B15 N17 J18 J14 F17 A12 A11 GPI_00/I2S1RX_SDA GPI_02/ENET_RXD3 GPI_03 GPI_04/SPI1_BUSY GPI_05/U3_DCD GPI_06/ENET_RXD2 GPI_07 GPI_09/ENET_COL GPI_19/U4_RX GPI_28/U3_RI GPI_16/U2_HCTS GPI_18/U3_RX GPI_21/U6_IRRX GPO_00/TST_CLK1 GPO_01 GPO_04 GPO_05 GPO_11 GPO_14 GPO_17 GPO_19 GPO_20 GPO_23/U2_HRTS C3 D4 D8 B3 E8 D3 N18 C2 B2 M16
ENET ENET_MDIO ENET_MDC ENET_CRS ENET_RXD0 ENET_RXD1 ENET_TXD0 ENET_TXD1 ENET_RX_CLK ENET_RX_DV ENET_RX_ER ENET_TX_CLK ENET_TX_EN ENET_TXD2 ENET_TXD3 SCK0 MOSI0 MISO0 SSEL0 I2C1_SCL I2C1_SDA I2C2_SCL I2C2_SDA ENET_RXD3 IRQ0 IRQ1 IRQ2 ENET_RXD2 KEY0 ENET_COL KEY1 KEY2 KEY3 KEY4 KEY5 SPI0 CODEC_RST_N U5_GPIO_CTS I2S I2S1RX_CLK I2S1RX_WS
SPI_CS2 RESOUT_0 RESOUT_1 FL_WP_N GPO20 RESOUT_2
ANALOG
OUTPUTS
INPUTS
SD-CARD
GPIO_00 GPIO_01 P0.0/I2S1RX_CLK P0.1/I2S1RX_WS
ADIN0/TS_XM ADIN1/TS_YM ADIN2/TS_AUX_IN
U15 T14 V16
ADIN0 ADIN1 ADIN2
B5 D7
I2S
LPC3250/B296 U402A SPI_CS0

7 1
GPIO
74HC3G04DP U402B SPI_CS1

5 3
LPC3250/B296 74HC3G04DP U402C SPI_CS3

2 6
U402P GND
74HC3G04DP GND This document may not be passed on, duplicated or its contents utilized, unless expressly permitted. Violating this stipulation will result in the liability to pay damages. All rights reserved in case of a patent registration or registered design.
A2 / 07.09.2009 / Ma
LPC3250 - CTRL,GPIO
VDD
+3V3
8
EMC_CLK U400EMC EMC_CKE EMC_CS_N EMC_CLK EMC_CLKIN EMC_CKE0 EMC_CS0_N EMC_CS1_N EMC_DYCS EMC_DYCS0_N EMC_A[0..23] EMC_A0 EMC_A1 EMC_A2 EMC_A3 EMC_A4 EMC_A5 EMC_A6 EMC_A7 EMC_A8 EMC_A9 EMC_A10 EMC_A11 EMC_A12 EMC_A13 EMC_A14 EMC_A15 EMC_A16 EMC_A17 EMC_A18 EMC_A19 EMC_A20 EMC_A21 EMC_A22 EMC_A23
L3 L4 M1 M2 M3 N1 N2 N3 M4 P1 P2 P3 N4 R1 R2 L1 K3 K4 K2 K1 J1 J2 J3 J4 T3 T4 U3 L2 U13 R11 T12 V15 R6 G1 EMC_CLK EMC_CLKIN EMC_CKE0 EMC_CKE1 EMC_CS0_N EMC_CS1_N EMC_CS2_N EMC_CS3_N EMC_BLS[0] EMC_BLS[1] EMC_BLS[2] EMC_BLS[3] EMC_DQM[0] EMC_DQM[1] EMC_DQM[2] EMC_DQM[3] U14 T13 R12 P12 R3 P4 T1 P5 T2 R5 H1 R4
ANIN3 ANIN4 LCD_CTRL EMC_DQM[0..1] EMC_DQM0 EMC_DQM1 EMC_CTRL EMC_RAS_N EMC_CAS_N EMC_OE_N EMC_WR_N EMC_D0 EMC_D1 EMC_D2 EMC_D3 EMC_D4 EMC_D5 EMC_D6 EMC_D7 EMC_D8 EMC_D9 EMC_D10 EMC_D11 EMC_D12 EMC_D13 EMC_D14 EMC_D15 PWM[0..7] PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 SPI_SS LED1_LNK IRQA IRQB IRQC LCDVD[0..23] LCDPWR LCDLE LCDDCLK LCDFP LCDENAB LCDLP LCDVD0 LCDVD1 LCDVD2 LCDVD3 LCDVD4 LCDVD5 LCDVD6 LCDVD7 LCDVD8 LCDVD9 LCDVD10 LCDVD11 LCDVD12 LCDVD13 LCDVD14 LCDVD15 LCDVD16 LCDVD17 LCDVD18 LCDVD19 LCDVD20 LCDVD21 LCDVD22 LCDVD23
R13 U16 E11 B12 B13 G13 A14 D10 D11
U400LCD
TS_XP TS_YP LCDPWR LCDLE LCDDCLK LCDCLKIN LCDFP LCDENAB/LCDM LCDLP
EMC_RAS_N EMC_DYCS0_N EMC_CAS_N EMC_DYCS1_N EMC_OE_N EMC_WR_N
EMC_D[0..15]
EMC_A[00] EMC_A[01] EMC_A[02] EMC_A[03] EMC_A[04] EMC_A[05] EMC_A[06] EMC_A[07] EMC_A[08] EMC_A[09] EMC_A[10] EMC_A[11] EMC_A[12] EMC_A[13] EMC_A[14] EMC_A[15] EMC_A[16] EMC_A[17] EMC_A[18] EMC_A[19] EMC_A[20] EMC_A[21] EMC_A[22] EMC_A[23]
EMC_D[00] EMC_D[01] EMC_D[02] EMC_D[03] EMC_D[04] EMC_D[05] EMC_D[06] EMC_D[07] EMC_D[08] EMC_D[09] EMC_D[10] EMC_D[11] EMC_D[12] EMC_D[13] EMC_D[14] EMC_D[15] EMC_D[16] EMC_D[17] EMC_D[18] EMC_D[19] EMC_D[20] EMC_D[21] EMC_D[22] EMC_D[23] EMC_D[24] EMC_D[25] EMC_D[26] EMC_D[27] EMC_D[28] EMC_D[29] EMC_D[30] EMC_D[31]
U4 R7 T5 U5 V3 V4 T6 R8 V5 U6 V6 T7 U7 V7 T8 U8 V8 R9 V9 U9 T9 V10 U10 T10 R10 V11 U11 T11 V12 V13 U12 V14
B14 D12 A15 A13 M17 M18 L15 L16 C13 C12 E17 E18 L17 L18 E10 G17 D14 H16 A16 D15 A9 A10 B11 B10
LCDVD[0] LCDVD[1] LCDVD[2] LCDVD[3] LCDVD[4] LCDVD[5] LCDVD[6] LCDVD[7] LCDVD[8] LCDVD[9] LCDVD[10] LCDVD[11] LCDVD[12] LCDVD[13] LCDVD[14] LCDVD[15] LCDVD[16] LCDVD[17] LCDVD[18] LCDVD[19] LCDVD[20] LCDVD[21] LCDVD[22] LCDVD[23]
LPC3250/B296
FL_CTRL U400FLASH FL_ALE FL_CLE FL_CE_N FL_RDY FL_RD_N FL_WR_N FL_IO0 FL_IO1 FL_IO2 FL_IO3 FL_IO4 FL_IO5 FL_IO6 FL_IO7
D2 F3 E3 D1 C1 F2 FLASH_ALE FLASH_CLE FLASH_CE_N FLASH_RDY FLASH_RD_N FLASH_WR_N
LPC3250/B296 PWM[0..7] PWM0 PWM1 PWM2 PWM3 4*10K/S1206 RA1B 4*10K/S1206 RA1C 4*10K/S1206 RA1D 4*10K/S1206
18 16 14 12
U500/1
OE_N 1
GPO20 LCDLP LCDENAB LCDFP LCDDCLK FL_IO[0..7]
2 4 6 8
RA1A
74AHC244PW U500/2
OE_N 3 5 7 19
H2 H3 F1 E1 H4 G2 G3 E2
FLASH_IO[00] FLASH_IO[01] FLASH_IO[02] FLASH_IO[03] FLASH_IO[04] FLASH_IO[05] FLASH_IO[06] FLASH_IO[07]
LPC3250/B296
+3V3
GND
PWM4
20
17 15 13 11
LCDLE LCDPWR LCDVD16 LCDVD19 This document may not be passed on, duplicated or its contents utilized, unless expressly permitted. Violating this stipulation will result in the liability to pay damages. All rights reserved in case of a patent registration or registered design.
PWM5
VDD
PWM6 4*10K/S1206 RA2B 4*10K/S1206 RA2C 4*10K/S1206 RA2D 4*10K/S1206 PWM7
U500/P
10
GND
74AHC244PW
B500
1 2 1 2
RA2A
A2 / 07.09.2009 / Ma
LPC3250 - EMC, LCD
B500 and B501 are closed by default.

GND
GND
GND
B501
Place caps as close as possible to LPC3250 +1V2 +3V3 +1V2 +3V3 +1V2 +3V3
G7 G9 G11 J7 J12 M7 M11 L12 M13 N14 N12 N13
100N/0603
100N/0603
100N/0603
100N/0603
100N/0603
C600 100N/0603
C601 100N/0603
100N/0603
C610 100N/0603
P13 G8 G10 G12 H7 K12 L7 M9 M10 M12 K5 L5 M5 N5 N6 P6 P7 P8 P9 P10 P11 K13 F6 F5 G5 H5 F10 F11 F12 H12
C602
C603
C604
C605
C606
C607
VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE
VDD_COREFXD VDD_COREFXD
VDD_FUSE
VDD_AD VDD_AD
GND GND
H13 J13 F8 F7 G6 H6 J5 F9 F13 J6 K6 K7 L6 M6 M8 N7 N8 N9 N10 N11 T18 T16 R17 P15 K14 L13 N15
L600 BLM11P600S AGND
VDD_IOA VDD_IOA VDD_IOB
VSS_AD VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_EMC VSS_EMC VSS_EMC VSS_EMC VSS_EMC VSS_EMC VSS_EMC VSS_EMC VSS_EMC VSS_EMC VSS_EMC VSS_IOA
1.8V or 3.3V
VDD_IOC VDD_IOC VDD_IOC VDD_IOC VDD_IOD VDD_IOD VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_OSC VDD_PLL397 VDD_PLLHCLK VDD_PLLUSB VDD_RTC VDD_RTCCORE VDD_RTCOSC
GND
1.2V
3.3V
1.8V, 2.8V or 3.3V
U400PWR LPC3250/B296
VSS_IOB
1.2V
VSS_IOC VSS_IOC VSS_IOC VSS_RTCOSC VSS_RTCCORE VSS_PLLUSB VSS_PLLHCLK VSS_PLL397 VSS_OSC VSS_IOD VSS_IOD VSS_IOD VSS_IOD
R14
PLL397_LOOP
120K/0603
R600
C608 150PS/50V/0603
C609 3900PS/25V/0603
GND
GND
P18 L14 R16 R18 T15 P14
GND
A2 / 07.09.2009 / Ma
LPC3250 - POWER
Place caps as close as possible to NAND-Flash +3V3 100N/0603 EMC_CLK +3V3 EMC_CLKIN 22R/0603 R700 Match lenght of EMC_CLKIN to longest EMC_Dx. Place resistor as close as possible to SDRAM. EMC_A[0..23] U700_SYS
38 37 19 18 17 16 CLK CKE CS# RAS# CAS# WE# BA0 BA1 DQMH DQML NC 20 21 39 15 40
100N/0603
10K/0603 R702
+3V3 2K/0603 R701
C703
EMC_CKE EMC_DYCS EMC_CTRL EMC_CLK EMC_CKE0 EMC_DYCS0_N EMC_RAS_N EMC_CAS_N EMC_WR_N EMC_A0 EMC_A1 EMC_A2 EMC_A3 EMC_A4 EMC_A5 EMC_A6 EMC_A7 EMC_A8 EMC_A9 EMC_A10 EMC_A11 EMC_A12
U701 EMC_A13 EMC_A14 EMC_DQM1 EMC_DQM0 EMC_D[0..15] FL_IO[0..7] EMC_D0 EMC_D1 EMC_D2 EMC_D3 EMC_D4 EMC_D5 EMC_D6 EMC_D7 EMC_D8 EMC_D9 EMC_D10 EMC_D11 EMC_D12 EMC_D13 EMC_D14 EMC_D15 EMC_DQM[0..1] FL_CTRL FL_CLE FL_ALE FL_CE_N FL_RD_N FL_WR_N FL_IO7 FL_IO6 FL_IO5 FL_IO4 FL_IO3 FL_IO2 FL_IO1 FL_IO0
H8 J6 D5 C4 C6 D4 C7 VDD VDD CL AL E_N R_N W_N VSS VSS VSS C5 K3 K8
GND
WP_N RB_N C3 C8
C704
FL_WP_N FL_CTRL
EMC_A[0..23]
FL_RDY
23 24 25 26 29 30 31 32 33 34 22 35 36
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53
J8 K7 J7 K6 K5 K4 J4 H4
I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
NAND512W3A2CZA
MT48LC32M16A2P-75IT
+3V3
to SDRAM C701 100N/0603 SPI0 MISO0
C700 +3V3 100N/0603 U700_PWR

1 14 27 3 9 43 49 VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VSS VSS VSS VSSQ VSSQ VSSQ VSSQ 54 41 28 6 12 46 52
+3V3
Place caps as close as possible
U702A RESOUT_N SCK0 MOSI0 SSEL0

7 3 HOLD# W# 2
6 5 1
C D S#
MT48LC32M16A2P-75IT GND GND
M25PX32VMW R703 10K/0603
+3V3
GND
VCC C705 100N/0603 This document may not be passed on, duplicated or its contents utilized, unless expressly permitted. Violating this stipulation will result in the liability to pay damages. All rights reserved in case of a patent registration or registered design.
U702P VSS
4
A2 / 07.09.2009 / Ma
SDRAM, NAND-FLASH
GND GND
+3V3 C800 4U7S/0805 U800_SYS CODEC_RST_N SYSCLKO I2S R800 47R/0603 I2S1TX_SDA I2S1TX_WS I2S1TX_CLK I2S1RX_SDA I2S1RX_WS I2S1RX_CLK I2C1_SDA I2C1_SCL
1 9 RESET SEL_L3_IIC SYSCLK RTCB 15 11
+3V3
C5 C6
0U47/0603 0U47/0603 SPKR_L L800
+3V3
C4
0U47/0603
SPKR_R/M
BMB2B0600RS2
C806 100US/T/6V/B GND

28
R802
8 7 6 5 4 3 12 14 13 DATAI WSI BCKI DATAO WSO BCKO VOUTRHP VOUTLHP VREF(HP) VOUTR VOUTL 17 19 18 21 23 27 29 31
0R/0603 0R/0603 47US/T/10V 47US/T/10V 47US/T/10V 47US/T/10V 47US/T/10V 10K/0603 GNDA R807 10K/0603 GNDA R806 R804 R805
VOUTRHP VOUTLHP 100R/0603 100R/0603 VINL VINR VINM

32
U800_PWR VOUTR VOUTL C807 100N/0603

30 VADCP
VDDD
C801
+
VSSD
10 VDDA(AD)
R803
C809
26
C802
+
VINL VINR L3MODE/A1 L3DATA/SDA VINM L3CLOCK/SCL
GNDA
C804
+
20
47K/0603
UDA1380HN
C805
+
C808 100N/0603
16
VDDA(HP) VREF
VDDA(DA)
22
GNDA C810 100N/0603 GNDA +3V3 GND 100K/0603 USB_PWR_ENB_N USB_VBUS USB_D+ USB_DUSB_ID C813 220N/0603 C814 100N/0603 R813
24
C803
VADCN
VSSA(AD)
100N/0603
+3V3
R801
GNDA
GNDA
VSSA(HP)
VSSA(DA)
10K/0603 U803
4 VCC E/D 1
GND
GND +3V3
C811 +3V3 10US/T/16V/B Place resistors and caps as close as possible to PHY +3V3 RESOUT_N
3 23 28 27 20
25
R814
UDA1380HN
C812 100N/0603
49R9/0603
49R9/0603
49R9/0603
10P/0603
2 GND
OUT
U801_SYS
RESET_N X1 X2 RBIAS 25MHZ_OUT PFBOUT PFBIN1 PFBIN2 21 19 16 30
C1 100N/0603 GND
49R9/0603
C2
100N/0603 GND
KC3225A-C3_25MHz GND ENET ENET_TX_CLK ENET_TX_EN ENET_TXD0 ENET_TXD1 ENET_TXD2 ENET_TXD3 ENET_MDIO ENET_MDIO ENET_MDC ENET_RX_CLK ENET_RX_DV ENET_CRS ENET_RX_ER ENET_COL ENET_RXD0 ENET_RXD1 ENET_RXD2 ENET_RXD3 4K87/0603
R14
R15
R16
R17
2K/0603 R810
1K5/0603
2 3 4 5 6 7 24 25 31 32 33 34 35 36 37 38 39
R6
TX_CLK TX_EN TXD_0 TXD_1 TXD_2 TXD_3 MDIO MDC
10K/0603
+3V3
RDRD+
11 12
RDRD+ TDTD+
10K/0603 N.M.R812
R808
ETH0
2K/0603
10K/0603 R811
U802
24 20 VCC_IO VCC AGND CPGND DGND 17 23 EXP
TDTD+
14 15
USB USB_I2C_SDA USB_I2C_SCL
R809
LED/AN0 RX_CLK RX_DV CRS/CRS_DV RX_ER COL RXD_0 RXD_1 RXD_2 RXD_3
22
LED/AN0
2 3 4 5 6 8 10 11 12 9 14 13
GNDA
C815
SDA SCL RESET_N INT_N
ADR/PSW VBUS DP DM ID
1 19 16 15 18
RESOUT_N USB_ATX_INT_N USB_D+

NC1 NC2 NC3 8 9 10
CR_INT SERVICE_N C_A SPKR_L SPKR_R/MIC RCV OE_N/INT_N C_B DAT/VP SE0/VM VREG
21
SPKR_L SPKR_R/M C816 C817 C818 10US/T/16V USB_OE_TP_N USB_DAT_VP USB_SE0_VM

+
DP83848TSQ
22 7
R815
100N/0603
100N/0603
GND GND GND +3V3 +3V3
GND
ISP1302HN
GND U801_PWR
1 26 18 IOVDD33 IOGND_1 IOVDD33 DAP DGND AVDD33 AGND AGND 40 DAP 29 13 17
C819 100N/0603 AGND
C820 100N/0603 GND
DP83848TSQ AGND This document may not be passed on, duplicated or its contents utilized, unless expressly permitted. Violating this stipulation will result in the liability to pay damages. All rights reserved in case of a patent registration or registered design.
GND
A2 / 07.09.2009 / Ma
USB,AUDIO,ETH
+5V
U903 TPS2041BDBV
5 4 GND VIN EN VOUT FAULT_N 1 3
USB_VBUS
USB_PWR_ENB_N C7 100N/0603
GND5
GND5
+3V3
+3V3
1K/0603 V900 TOPLED/GN
R900
U900
1 3 GND IN EN
ADP1710AUJZ-1.2-R7 TP900 GND +1V2 10K/0603 +3V3 R901 100K/0603 R902

4 3 OUT NC 5 4
C900 1US/0603
+1V2 C901 1US/0603 GND

2
GND
GND
GND
+3V3
U902
5 1 VDD RST_N CT MR_N GND
POR_N RESET_N
+3V3
TPS3838K33 GND
C902 100N/0603
C903 100N/0603
C904 100N/0603
C905 100N/0603
Viducials TOP
ADJ_1 ADJ_2 ADJ_3
GND
GND
GND
GND
Viducials BOT
U901 N.M.
3 VDD RST_N 1
MOUNTING-HOLE MOUNTING-HOLE
ADJ_4
ADJ_5
ADJ_6
MNH900
MNH901
GND
TPS3809K33
A2 / 07.09.2009 / Ma
POWER, RESET

6.
Layout
Top Parts
Page 23
17/06/2010

Top Layer
Page 24
17/06/2010

Bottom Layer
Page 25
17/06/2010

Bottom Parts
Page 26
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7.
Part U400 U402 U500 U700 U701 U702 U800 U801 U802 U900 U902 U903 V900 U401 U803 Q400 X1 X200 X201 X300 X301 R1 R2 R3 R4 R5 R13 R14 R15 R16 R17 R300 R400 R600 R700 R701 R702 R703 R800 R801 R802 R803 R804 R805 R806 R807 R808 R809 R810 R811 R812 R813 R814 R815 R900
Parts List
Supplier PN LPC3250/B296 74HC3G04DP,125 SN74AHC244PW MT48LC32M16A2P-75IT NAND512W3A2CZA M25PX32VMW UDA1380HN/N2,118 DP83848TSQ/NOPB ISP1302HN / ISP1301BS ADP1710AUJZ-1.2-R7 TPS3838K33 TPS2041BDBV ChipLed green LF SPXO025616 LF SPXO025165 LF XTAL003000 TST-110-01-G-D TYCO-1-5316562-1 TYCO-1-5316562-1 TYCO-6-5316564-1 TYCO-6-5316564-1 10K/0603 10K/0603 10K/0603 10K/0603 10K/0603 1K/0603 49R9/0603 49R9/0603 49R9/0603 49R9/0603 22R/0603 10K/0603 120K/0603 22R/0603 10K/0603 2K/0603 10K/0603 47R/0603 47K/0603 0R/0603 0R/0603 100R/0603 100R/0603 10K/0603 10K/0603 2K/0603 2K/0603 10K/0603 10K/0603 10K/0603 100K/0603 10K/0603 4K87/0603 1K/0603 Supplier NXP NXP TID Micron Numonyx Numonyx NXP NSC NXP ADI TID TID Any IQD IQD IQD Samtec Tyco Tyco Tyco Tyco Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Package TFBGA296 TSSOP8 TSSOP20 TSOP54-400 VFBGA63_9X11 SO8W HVQFN32 LLP40 HVQFN24 TSOT-5 SOT23-5L SOT23-3 CHIP-LED0603 CFPS-39IB 32X25 85SMX XSE_2X10_254 1-5316562-1 1-5316562-1 6-5316564-1 6-5316564-1 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 Comment Revision A1 3 Inverter PWM/IO gate SDRAM up to 133MHz NAND Flash 64MB 4MByte serial Flash Stereo Audio Codec Ethernet PHY ISP1301BS instead of ISP1302BS 150mA LDO 1.2V 1.8V Reset with manual input USB Power Switch ChipLED green SMD0603 Quarz-Osz. 13MHz 3.3V 3.2x2.5mm 25MHz Oszillator 3.3V 3.2x2.5mm Quarz 32.768KHz, SMD 8.5x3.8 JTAG Debug Connector (2*10, 0.1") Base Board Connector (male) Base Board Connector (male) Base Board Connector (female) Base Board Connector (female)
Page 27
17/06/2010

Part R901 L600 L800 C1 C2 C3 C4 C5 C6 C400 C401 C402 C600 C601 C602 C603 C604 C605 C606 C607 C608 C609 C610 C700 C701 C703 C704 C705 C800 C801 C802 C803 C804 C805 C806 C807 C808 C809 C810 C811 C812 C813 C814 C815 C816 C817 C818 C819 C820 C900 C901 C902 C903 C904 C905 Supplier PN 10K/0603 BLM11P600S BMB2B0600RS2 100N/0603 100N/0603 100N/0603 0U47/0603 0U47/0603 0U47/0603 10P/0603 12P/0603 12P/0603 100N/0603 100N/0603 100N/0603 100N/0603 100N/0603 100N/0603 100N/0603 100N/0603 150PS/50V/0603 3900PS/25V/0603 100N/0603 100N/0603 100N/0603 100N/0603 100N/0603 100N/0603 4U7S/0805 47US/T/10V 47US/T/10V 47US/T/10V 47US/T/10V 47US/T/10V 100US/T/6V/B 100N/0603 100N/0603 100N/0603 100N/0603 10US/T/16V/B 100N/0603 220N/0603 100N/0603 10P/0603 100N/0603 100N/0603 10US/T/16V 100N/0603 100N/0603 1US/0603 1US/0603 100N/0603 100N/0603 100N/0603 100N/0603 Supplier Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Package R0603 R0603 R1206 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0805 SMC_D SMC_D SMC_D SMC_D SMC_D SMC_B C0603 C0603 C0603 C0603 SMC_B C0603 C0603 C0603 C0603 C0603 C0603 SMC_C C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 Comment
Ferrite Bead 1206 600R 200mA
Changed from 100n to 220n
(yellow = Changes from Revision A1/A2)
Page 28
17/06/2010

8.
Ordering Information
Order Number: EPC-PROC02-NXP-LPC3250
9.
Revision Tracking
Initial release for hardware revision A1 with some errata:
Rev. 0.0.0
* NAND-Flash is not usable Processor data line 0...7 connect with Flash data line 7-0 (commands not recognized) Control lines wrong (nearly all) * EMC_OE_N from LPC3250 not connected with Add-On Connector (external SRAM memory may not work) * IC for the Extension Module is not used (IC-1 is used internally for audio codec) Rev. 1.0.0 Initial release for hardware revision A2 (10 prototypes)
* Description of all new features in revision A2 added: Latch between LCD interface (PWM) and Extension Board PWM outputs Inverter for some SPI chip select lines Additional available lines at the Extension Board (A/D, IC, Interrupt) ISP1301BS replaced by ISP1302HN with CARKIT function Rev. 2.0.0 Initial release for hardware revision A3 (Serial Production)
* Changes for hardware revision A3 added: Reset of ISP1301/2 connected to LPC3250 reset output Pull-down for PWM6 and PWM7 can be disabled (by opening two jumpers)
10. Known Errata of Hardware Revision A3

ISP1301BS used instead of ISP1302HN Because of the long lead time for ISP1302HN, the pin-compatible revision of ISP1301BS is used. There are four pins which are not compatible, and changes are required in hardware and software: * Pin 6 (CR_INT) is connected to USB_D+ (ISP1301: should be connected to pull-down) * Pin 8 (Service_N) uses a pull-up (ISP1302: should be connected to pull-down) The function of both pins can be corrected in the software. * Pin 10 (SPKR_L) is connected via capacitor to audio codec (ISP1301: should be open) * Pin 11 (SPKR_R) is connected via capacitor to audio codec (ISP1301: should be open) Removal of the capacitor will mean that the CARKIT function is not usable.
Page 29
17/06/2010

NXP LPC3250 Featuring ARM9 With Ethernet, USB, and LCD: EPC - Embedded Platform Concept

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NXP LPC3250 Featuring ARM9 With Ethernet, USB, and LCD: EPC - Embedded Platform Concept

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EPC Embedded Platform Concept

EPC-PROC02-NXP-LPC3250 Processor Module Featuring NXP LPC3250 ARM9 Processor