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This Data Sheet states AMDs current technical specifications regarding the Product described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
GENERAL DESCRIPTION
The Am29F016B is a 16 Mbit, 5.0 volt-only Flash memory organized as 2,097,152 bytes. The 8 bits of data appear on DQ0DQ7. The Am29F016B is offered in 48-pin and 40-pin TSOP, and 44-pin SO packages. The device is also available in Known Good Die (KGD) form. For more information, refer to publication number 21551. This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply. A 12.0 volt VPP is not required for program or erase operations. The device can also be programmed in standard EPROM programmers. This device is manufactured using AMDs 0.32 m process technology, and offers all the features and benefits of the Am29F016, which was manufactured using 0.5 m process technology. The standard device offers access times of 70, 90, 120, and 150 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE#), write enable (WE#), and output enable (OE#) controls. The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithman internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithman internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The system can place the device into the standby mode. Power consumption is greatly reduced in this mode. AMDs Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.
Am29F016B
BLOCK DIAGRAM
DQ0DQ7 VCC VSS RY/BY# RESET# State Control Command Register Sector Switches Erase Voltage Generator Input/Output Buffers
WE#
PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE# OE#
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0A20
21444D-1
Am29F016B
CONNECTION DIAGRAMS
This device is also available in Known Good Die (KGD) form. Refer to publication number 21551 for more information.
A19 A18 A17 A16 A15 A14 A13 A12 CE# VCC NC RESET# A11 A10 A9 A8 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A20 NC WE# OE# RY/BY# DQ7 DQ6 DQ5 DQ4 VCC VSS VSS DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3
21444D-2
A20 NC WE# OE# RY/BY# DQ7 DQ6 DQ5 DQ4 VCC VSS VSS DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
A19 A18 A17 A16 A15 A14 A13 A12 CE# VCC NC RESET# A11 A10 A9 A8 A7 A6 A5 A4
21444D-3
Am29F016B
CONNECTION DIAGRAMS
This device is also available in Known Good Die (KGD) form. Refer to publication number 21551 for more information.
NC NC A19 A18 A17 A16 A15 A14 A13 A12 CE# VCC NC RESET# A11 A10 A9 A8 A7 A6 A5 A4 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 NC 47 NC 46 A20 45 NC 44 WE# 43 OE# 42 RY/BY# 41 DQ7 40 DQ6 39 DQ5 38 DQ4 37 VCC 36 VSS 35 VSS 34 DQ3 33 DQ2 32 DQ1 31 DQ0 30 A0 29 A1 28 A2 27 A3 26 NC 25 NC
21444D-4
NC NC A20 NC WE# OE# RY/BY# DQ7 DQ6 DQ5 DQ4 VCC VSS VSS DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3 NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
NC NC A19 A18 A17 A16 A15 A14 A13 A12 CE# VCC NC RESET# A11 A10 A9 A8 A7 A6 A5 A4 NC NC
21444D-5
Am29F016B
CONNECTION DIAGRAMS
This device is also available in Known Good Die (KGD) form. Refer to publication number 21551 for more information.
NC RESET# A11 A10 A9 A8 A7 A6 A5 A4 NC NC A3 A2 A1 A0 DQ0 DQ1 DQ2 DQ3 VSS VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 VCC CE# A12 A13 A14 A15 A16 A17 A18 A19 NC NC A20 NC WE# OE# RY/BY# DQ7 DQ6 DQ5 DQ4 VCC
SO
21444D-6
PIN CONFIGURATION
A0A20 CE# WE# OE# RESET# RY/BY# VCC = = = = = = 21 Addresses 8 Data Inputs/Outputs Chip Enable Write Enable Output Enable Hardware Reset Pin, Active Low Ready/Busy Output DQ0DQ7 =
LOGIC SYMBOL
21 A0A20 DQ0DQ7 8
= +5.0 V single power supply (see Product Selector Guide for device speed ratings and voltage supply tolerances) = = Device Ground Pin Not Connected Internally
VSS NC
21444D-7
Am29F016B
Valid Combinations AM29F016B-75 (VCC = 5.0 V 5%) AM29F016B-90 AM29F016B-120 AM29F016B-150 EC, EI, FC, FI, E4C, E4I, F4C, F4I, SC, SI EC, EI, EE, FC, FI, FE, E4C, E4I, E4E, F4C, F4I, F4E, SC, SI, SE
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Am29F016B
Table 1.
Operation Read Write CMOS Standby TTL Standby Output Disable Hardware Reset Temporary Sector Unprotect (See Note)
VCC 0.5 V H L X X
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 0.5 V, X = Dont Care, DIN = Data In, DOUT = Data Out, AIN = Address In Note: See the sections on Sector Group Protection and Temporary Sector Unprotect for more information
Am29F016B
the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VIL, the device enters the TTL standby mode; if RESET# is held at VSS 0.5 V, the device enters the CMOS standby mode. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is 1), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and timing diagram.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when CE# and RESET# pins are both held at VCC 0.5 V. (Note that this is a more restricted voltage range than VIH.) The device enters the TTL standby mode when CE# and RESET# pins are both held at VIH. The device requires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data. The device also enters the standby mode when the RESET# pin is driven low. Refer to the next section, RESET#: Hardware Reset Pin. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. In the DC Characteristics tables, ICC3 represents the standby current specification.
Am29F016B
Table 2.
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A19 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A18 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
10
Am29F016B
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes (High Voltage Method) table. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the remaining address bits that are dont care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require VID . See Command Definitions for details on using the autoselect mode.
Table 3.
Description Manufacturer ID: AMD Device ID: Am29F016B Sector Group Protection Verification
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Dont care.
Table 4.
Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 A20 0 0 0 0 1 1 1 1
Am29F016B
11
the Temporary Sector Group Unprotect diagram (Figure 16) shows the timing waveforms, for this feature.
START
RESET# = VIH
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO . The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Write Pulse Glitch Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
21444D-8
Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up.
Notes: 1. All protected sector groups unprotected. 2. All previously protected sector groups are protected once again.
Figure 1.
12
Am29F016B
COMMAND DEFINITIONS
Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the AC Characteristics section. however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are dont care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins,
Am29F016B
13
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a 0 back to a 1. Attempting to do so may halt the operation and set DQ5 to 1, or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still 0. Only erase operations can convert a 0 to a 1.
command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Command Definitions table shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See Write Operation Status for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 3 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in AC Characteristics for parameters, and to the Chip/Sector Erase Operation Timings for timing waveforms.
START
Verify Data?
No
Yes No
Increment Address
Last Address?
Note: See the appropriate Command Definitions table for program command sequence.
Figure 2.
Program Operation
After the command sequence is written, a sector erase time-out of 50 s begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 s, the
14
Am29F016B
system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the DQ3: Sector Erase Timer section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. Note that a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to Write Operation Status for information on these status bits. Figure 3 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the AC Characteristics section for parameters, and to the Sector Erase Operations Timing diagram for timing waveforms.
dresses are dont-cares when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device erase suspends all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on DQ7DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See Write Operation Status for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence for more information. The system must write the Erase Resume command (address bits are dont care) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing.
Am29F016B
15
START
Data Poll from System Embedded Erase algorithm in progress No Data = FFh?
Notes: 1. See the appropriate Command Definitions table for erase command sequence. 2. See DQ3: Sector Erase Timer for more information.
Figure 3.
Erase Operation
16
Am29F016B
Table 5.
Cycles
First Addr RA XXX 555 555 555 555 555 555 XXX XXX Data RD F0 AA AA AA AA AA AA B0 30
Third Addr
1 1 4 4 4 4 6 6 1 1
55 55 55 55 55 55
90 90 90 A0 80 80
Legend: X = Dont care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20A16 select a unique sector. SGA = Address of the sector group to be verified. Address bits A20A18 select a unique sector group. 4. Address bits A20A11 are dont cares for unlock and command cycles, unless SA or PA required. 5. No unlock or command cycles required when reading array data. 6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data). 7. The fourth cycle of the autoselect command sequence is a read cycle. 8. The data is 00h for an unprotected sector group and 01h for a protected sector group.See Autoselect Command Sequence for more information. 9. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 10. The Erase Resume command is valid only during the Erase Suspend mode.
Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except when reading array or autoselect data, all bus cycles are write operations.
Am29F016B
17
START
DQ7 = Data?
Yes
No No
DQ5 = 1?
DQ7 = Data?
Yes
No FAIL PASS
Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5.
21444D-10
Figure 4.
18
Am29F016B
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 6 shows the outputs for RY/BY#. The timing diagrams for read, reset, program, and erase shows the relationship of RY/BY# to other signals.
The Write Operation Status table shows the outputs for Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit algorithm, and to the Toggle Bit Timings figure in the AC Characteristics section for the timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II.
Am29F016B
19
the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 5).
erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 6 shows the outputs for DQ3.
START
Read DQ7DQ0
Read DQ7DQ0
(Note 1)
No
DQ5 = 1?
Yes
(Notes 1, 2)
No
Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete
Notes: 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1. See text.
21444D-11
Figure 5.
20
Am29F016B
Table 6.
Operation Standard Mode Erase Suspend Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Erase Suspended Sector Reading within Non-Erase Suspended Sector Erase-Suspend-Program
Notes: 1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 2. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See DQ5: Exceeded Timing Limits for more information.
Am29F016B
21
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TC) . . . . . . . . . . .0C to +70C Industrial (I) Devices Ambient Temperature (TC) . . . . . . . . .40C to +85C Extended (E) Devices Ambient Temperature (TA) . . . . . . . .55C to +125C VCC Supply Voltages VCC for 5% devices . . . . . . . . . . +4.75 V to +5.25 V VCC for 10% devices . . . . . . . . . . . +4.5 V to +5.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
20 ns
20 ns
21444D-13
Figure 6.
Figure 7.
22
Am29F016B
1.0
50
1.0
40 60 1.0 1.0 0.8 VCC + 0.5 12.5 0.45
CMOS Compatible
Parameter Symbol ILI ILIT ILO ICC1 ICC2 ICC3 ICC4 VIL VIH VID VOL VOH1 VOH2 VLKO Parameter Description Input Load Current A9 Input Load Current Output Leakage Current VCC Read Current (Note 1) VCC Write Current (Notes 2, 3) VCC Standby Current (CE# Controlled) (Note 4) VCC Standby Current (RESET# Controlled) (Note 4) Input Low Level Input High Level Voltage for Autoselect and Sector Protect Output Low Voltage Output High Voltage Low VCC Lock-out Voltage VCC = 5.0 V IOL = 12 mA, VCC = VCC Min IOH = 2.5 mA, VCC = VCC Min IOH = 100 A, VCC = VCC Min 0.85 VCC VCC 0.4 3.2 4.2 Test Description VIN = VSS to VCC, VCC = VCC Max VCC = VCC Max, A9 = 12.5 V VOUT = VSS to VCC, VCC = VCC Max CE# = VIL, OE# = VIH CE# = VIL, OE# = VIH VCC = VCC Max, CE# = VCC 0.5 V, RESET# = VCC 0.5 V VCC = VCC Max, RESET# = VSS 0.5 V 0.5 0.7x VCC 11.5 25 30 1 1 Min Typ Max Unit A A A mA mA A A V V V V V V V
1.0
50
1.0
40 40 5 5 0.8 VCC + 0.3 12.5 0.45
Notes for DC Characteristics (both tables): 1. The ICC current is typically less than 1 mA/MHz, with OE# at VIH. 2. ICC active while Embedded Program or Embedded Erase algorithm is in progress. 3. Not 100% tested. 4. For CMOS mode only ICC3, ICC4 = 20 A at extended temperature (>+85C).
Am29F016B
23
TEST CONDITIONS
5.0 V 2.7 k
Table 7.
Test Specifications
All speed options Unit
Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels
21444D-14
Figure 8.
Test Setup
KS000010-PAL
24
Am29F016B
Chip Enable to Output High Z (Note 1) Output Enable to Output High Z (Note 1) Output Hold Time From Addresses CE# or OE# Whichever Occurs First RESET# Pin Low to Read Mode (Note 1)
tRC Addresses CE# tOE tOEH WE# HIGH Z Outputs RESET# RY/BY# Output Valid tCE tOH HIGH Z tDF Addresses Stable tACC
OE#
0V
21444D-15
Figure 9.
Am29F016B
25
RY/BY#
RESET# tRP
21444D-16
Figure 10.
RESET# Timings
26
Am29F016B
Am29F016B
27
AC CHARACTERISTICS
Program Command Sequence (last two cycles) tAS tWC Addresses 555h PA tAH CE# OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# tVCS VCC Status DOUT tRB tWPH tWHWH1 Read Status Data (last two cycles)
PA
PA
tCH
A0h
Note: PA = program address, PD = program data, DOUT is the true data at the program address.
21444D-17
Figure 11.
28
Am29F016B
AC CHARACTERISTICS
tWC Addresses 2AAh tAS SA
555h for chip erase
VA tAH
VA
CE#
tCH
tWPH
tWHWH2
tRB
21444D-18
Figure 12.
Am29F016B
29
AC CHARACTERISTICS
tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ7
High Z
VA
VA
tOE tDF
Complement
Complement
True
Valid Data
High Z
Status Data
Status Data
True
Valid Data
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
21444D-19
Figure 13.
tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ6/DQ2 tBUSY RY/BY#
High Z
VA
VA
VA
tOE tDF
Valid Data
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.
21444D-20
Figure 14.
30
Am29F016B
AC CHARACTERISTICS
Enter Embedded Erasing WE# Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete
DQ6
DQ2 Note: The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the erase-suspended sector.
21444D-21
Figure 15.
12 V
21444D-22
Figure 16.
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Notes: 1. Not 100% tested. 2. See the Erase And Programming Performance section for more information.
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Am29F016B
AC CHARACTERISTICS
555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase
Data# Polling PA
Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tCPH tDS tDH Data tRH
A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase
tAS tAH
tWHWH1 or 2
tBUSY
DQ7#
DOUT
RESET#
RY/BY#
Notes: 1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data. 2. Figure indicates the last two bus cycles of the command sequence.
21444D-23
Figure 17.
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Notes: 1. Typical program and erase times assume the following conditions: 25C, 5.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90C, VCC = 4.5 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then does the device set DQ5 = 1. See the section on DQ5 for further information. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the four-bus-cycle sequence for programming. See Table 6 for further information on command definitions. 6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Min Input Voltage with respect to VSS on I/O pins VCC Current Note: Includes all pins except VCC. Test conditions: VCC = 5.0 Volt, one pin at a time. 1.0 V 100 mA Max VCC + 1.0 V +100 mA
Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz.
DATA RETENTION
Parameter Minimum Pattern Data Retention Time Test Conditions 150C 125C Min 10 20 Unit Years Years
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PHYSICAL DIMENSIONS TS 04040-Pin Standard Thin Small Outline Package (measured in millimeters)
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PHYSICAL DIMENSIONS (continued) TSR04040-Pin Reverse Thin Small Outline Package (measured in millimeters)
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PHYSICAL DIMENSIONS (continued) TS 04848-Pin Standard Thin Small Outline Package (measured in millimeters)
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PHYSICAL DIMENSIONS (continued) TSR04848-Pin Reverse Thin Small Outline Package (measured in millimeters)
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Copyright 2000 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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