Topic04 Introduction To Input and Output (GPIO) With Freescale MC9S12X.

Topic Video 04
Introduction to Input and Output (GPIO)
Saturday, 29 August 2009
Input / Output (I/O)

Input refers to any information provided to the microprocessor from the outside world. Output is any information the microprocessor provides to the outside world. Without some form of I/O the processor is useless (blind, deaf, mute, and paralysed). The microprocessor must be able to receive information from the outside world (input). The microprocessor must also return the results of any calculations back to the outside world.
INPUT
OUTPUT
I/O
Microprocessors consist of many I/O subsystems. With two possible ways of accessing the them:
Ported I/O Access to the device is provided by a small port in the memory (generally through a GPIO port. Memory Mapped I/O The entire device including all its internal registers are mapped into consecutive memory locations in the memory map.
Memory Mapped I/O
I/O
$00
PORTA PORTB DDRA DDRB ....
...
$7FF
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There are two basic types of I/O:
Serial Serial devices generally use only one data pin on MCU. The data is transmitted via a shift register out of this pin one bit at a time. The data can be transmitted from the MSB to the LSB or the LSB to the MSB depending on the transmission characteristics. The rate a which the transmit and receive shift register operate depends on some prearranged clock frequency. The serial interface can either embedded the clocking information into the data or use a separate pin to pass the clocking signal.
I/O
Serial
RS232 RS232 is commonly referred to as asynchronous serial. This is the most common serial interface that is provided on many microprocessors and computers. Provides bit rates up to 115kbps. Clocking information is embedded into the data (3 pin interface: RX, TX, and GND). SPI SPI is a serial interface commonly found on microprocessors and microcontrollers. Provides bit rates up to 4Mbps and has a separate clock line (4 pin interface MISO, MOSI, SCLK, and GND. I2C I2C (I squared C) or Inter-Integrated Circuit is an interface found on some microprocessors. Provides speeds up to 100kbps and has a separate clock line ( 3 pin interface SDA, SCL and GND). CAN CAN or Controller Area Network is a differential serial system used in control applications. Can operate up to 1Mbps. Is robust against noise and has a 5 pin interface (RXCAN, TXCAN, and GND).
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Parallel
Parallel interfaces generally write whole bytes or words to the outside world at a time. These interfaces do not require complex hardware to transmit or receive the information and they do not require a clocking signal to reconstruct the information at the other end. These interfaces are simple and very quick to transmit information. However, parallel interfaces come at a large cost. They consume pins on the processor very quickly. An 8bit parallel interface would require 8 pins on the processor, whereas a serial interface requires at most only 4 pins. An example of a parallel interface is GPIO.
I/O
Communication with an I/O device can be achieved using three different methods:
Programmed I/O
Transfers take place under software control, the processor accepts and delivers data when the software dictates. Eg.
LDAA PTH ;Software tells processor to read from Port H.
STAA PORTA ;Software tells processor to write to Port A.
I/O
Interrupt
External events control when data is read or written from the I/O device, the program ow is halted to deal with the event. It is in fact the external I/O device that causes the processor to halt what it is doing and force it to service its request. The I/O device contains a control line called an interrupt line (INT/IRQ), when this line goes from high to low it signals an interrupt. The interrupt line of the device is connected to the microprocessor's interrupt pin. So when the I/O device's line goes low, it cause the processor to stop what it is doing and service the request of the device.
Driven I/O
I/O
Interrupt
Driven I/O Example
We have a RS232 serial subsystem that reads in serial information, it reconstructs the byte and makes it available in a data receive register. Because the serial data is constantly being piped into the serial system the processor will need to read the value in the data register before the next byte overwrites it. The RS232 subsystem can be set up so that is triggers an interrupt when there is new data to be read. Therefore the processor is forced to read the byte before it is overwritten by the next byte in the sequence, preventing the data from being lost.
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I/O
DMA
DMA allows devices to transfer data without subjecting the CPU to a heavy overhead. DMA consists of multiple channels. Each DMA channel has associated with it a 16bit address register and a 16-bit count register. To initiate a data transfer the device driver sets up the DMA channel's address and count registers together with the direction of the data transfer, read or write. It then instructs the DMA hardware to begin the transfer. When the transfer is complete, the device interrupts the CPU.
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Normal Single Chip Mode
I/O
The MC9S12XDP512 is capable of various modes of operations, the most common is single chip mode. In Normal Single Chip Mode the microcontroller is totally self contained, except for the need of an external clock source. In most situations single chip is more than adequate. All the resources required such as input/output devices, SRAM, EEPROM and Flash memories reside on a single IC and only a limited amount of specialized I/O circuitry is required for certain I/O devices.
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Programmers I/O Model
I/O
The MC9S12XDP512 contains numerous I/O possibilities, including parallel, serial and analog interfaces. All of the internal I/O subsystems are mapped to the lowest 2 kilobytes of the memory, from $0000 to $07FF.
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GPIO
The MC9S12XDP12 contains 12 8bit GPIO ports. The pins of each of these GPIO ports are shared with other I/O subsystems. If the device that shares the GPIO port is activated then the GPIO port is no longer available for use. On power up the GPIO ports are enabled by default (all other I/O subsystems are disabled). Port Name PORTA PORTB PORTJ PORTM PORTS PORTT PORTP PORTH PORTE PORTAD1 PORTAD0
Physical Pins H2:pins 1- 8 H2:pins 9 -15 H2:pins 40 - 47 H2:pins 40,21,39,38 H1:pins 4,3,2,1,32,34,5,48 H1:pins 6 - 13 H1:pins 14 - 21 H1:pins 35 - 42 H1:pins 33,32,34,46 H1:pins 22-29 H2:pins 22-29
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GPIO
The subsystem responsible for maintaining the GPIO ports is called the Port Integration Module. The port integration module is responsible for ensuring the GPIO and subsystems that share the pins of the processor do not conict. If a subsystem is activated then the GPIO that use the same pins as that subsystem is turned off.
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GPIO
The GPIO allows 8bit data to be driven on to the physical pins of the microprocessor and read from the pins via a data register. If the GPIO port is set up purely as output, then any value written to the GPIO's data register will appear on the 8 pins associated with that port. The value will appear on the corresponding pin as either 5 volts for logical '1' or 0 volts for logical '0'. So a logical '1' in the MSB of a GPIO data register will appear on the pin PX7 as 5 volts (replace 'X' for the port letter). If the GPIO is setup purely as input then any voltage driven to the external pins of the port will appear in the data registers. A '1' will appear in the data register where the corresponding pin had a voltage of 5volts applied.
1 1 1 0 0 1 0 1 OUTPUT
5V 5V 5V 0V 0V 5V 0V 5V
0V 5V 0V 0V 0V 5V 5V 5V
INPUT 0 1 0 0 0 1 1 1
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GPIO
The GPIO ports can act as 8bit input, 8 bit output or any combination in between. Top nibble input, bottom nibble output? The direction of each pin in the GPIO port can be dened to be either input or output. The Data Direction Register (DDR) allows the direction of each pin to be dened. So therefore each GPIO port has two registers associated with it: A data register, And a data direction register.
HS12
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GPIO
PTX7 PTX7
1
DDRX7
0
DDRX7
5V
5V
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GPIO
The registers of the GPIOs are memory mapped. There data registers and data direction registers can be set in the same way as writing a value to a memory location or a variable. You can access the registers either via their memory location or their name.
Data Direction Port Name Register Location PORTA PORTB PORTK PORTJ PORTM PORTS PORTT PORTP PORTH PORTE PORTATD1 PORTATD0 $002 (DDRA) $003 (DDRB) $0033 (DDRK) $0268 (DDRJ) $0252 (DDRM) $024A (DDRS) $0242 (DDRT) $025A (DDRP) $0262 (DDRH) $0009 (DDRE)
Data Register Location $0000 (PORTA) $0001 (PORTB) $0032 (PORTK) $026A (PTJ) $0250 (PTM) $0248 (PTS) $0240 (PTT) $0258 (PTP) $0260 (PTH) $0008 (PORTE)
See A/D Topic See A/D Topic
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GPIO
Examples
; Setup Port H as an 8bit output port. LDAA #$FF STAA DDRH ; Put the value $FF in DDRH. ; Write $AB to the pins of Port H. LDAA #$AB STAA PTH
; Setup Port K as an 8bit input port. CLR DDRK ; Read a value from PortK. LDAA PORTK
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GPIO
Examples
; Setup Port H[7:4] as a 4bit output port and ; H[3:0] as a 4 bit input port. MOVB #$F0,DDRH ; Put the value $F0 in DDRH.
Since only the 4 most signicant bits of port H are output, the lower 4 bits remain unchanged. So $A0 is only written to PTH. The entire 8 bits of port H are loaded into Accumulator A. The 4 lsb of the input as well as the last value written to the 4 msb.
; Write $AB to the pins of Port H. MOVB #$AB,PTH ; Read a value from Port H LDAA PTH
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Input and Output Pin Electronics
GPIO
Generally it is a good idea to set any unused input pins to either GND (0V) or VCC(5V). This will prevent the pins from causing unpredictable errors. It is also important to ensure that any unused output pins are left unconnected. If an unused output pin is connected to GND or VCC and an opposite logical value is written to the pin (pin tied to VCC and '0' written to the pin) then a phenomenon called latch up occurs. This will cause the processor to draw more current, which in turn will cause processor to get hot, which cause it to draw more current. This continues until the processor burns out.
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Input and Output Pin Electronics
GPIO
To ensure that latch up doesn't occur each GPIO pin has a pull-up resistor associated with it. This resistor limits the current on the pin and ensures the processor doesn't burn out. The the pull-up resistor ensures the safety of the processor. However, the pull-up resistor slows down the responsiveness of the GPIO pins and increases the power consumption of the processor. Therefore it is possible to turn on or off each of the pull-up resistors associated with a GPIO port using the Pull Device Enable Register (PER). By default the resistors are on and care must be taken if they are turned off.
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Input and Output Pin Electronics When driving devices connected to the GPIO, some devices require lots of current and yet some require only a little. Providing lots of current to a device ensure fast switch times for the GPIO pins, however consumes lots of power. By default the GPIO pins are set for high drive (current) operation. But, if a device doesn't need lots of current or it doesn't need fast switching then reducing the drive would reduce the power consumption. So if the processor was being used in a mobile application then each bit of power is important. So it is possible to turn off the high drive of a GPIO pin simply by putting that pin in reduced drive mode. Each GPIO port has a reduced drive control register associated with it.
GPIO
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GPIO
The MC9S12XDP512 has 12 8bit GPIO ports. Each port has A Data Register (PORTX / PTX), A Data Direction Register (DDRX), A Pull Device Enable Register (PERX) , And A Reduced Drive Control Register (RDRX).
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I/O Software
I/O
In I/O software there are three major components of the software:

Initialisation, Data input or Output, and Software Synchronisation.
The software must be synchronised with the reading and writing timing requirements of the connected device. Generally microprocessors are a lot faster than attached I/O devices, so the processor must be synchronised via software and hardware techniques. Possible techniques include:
Real-Time Synchronisation, Polled I/O, and Hardware Handshaking I/O.
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Timing Diagrams
Aside
Understanding the timing diagram is very important for successfully communication with an external I/O devices. The timing diagram illustrates visually the relationships between the I/O signals of an I/O device. The various signals of the I/O device are represented by square wave of varying periods. The relationship of each signal with respect to time can easily be seen in the timing diagram.
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Timing Diagrams: Simple Example
Aside
A timing diagram showing the changes in logic levels over time.
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Timing Diagrams: Not so Simple Example
Aside
A timing diagram showing the changes in logic levels over time, as well as timing dependencies
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Real-Time Synchronisation
I/O
Real-time synchronisation uses software delays to match the timing requirements of software and hardware. Using real-time synchronisation has it problems:
The delays are generated by instructions and therefore can not be exact, due to errors caused by instruction execution overheads. The execution of instructions is an integer multiple of the instruction cycle period, so delays smaller than the instruction cycle period can not be implemented.
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I/O
Common Delays
Small Delays
Delays of only a few instruction cycles (IC) can be done using sequential NOP instructions. Each NOP delays by one instruction cycle.
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I/O
Delays of less than 1021 instruction cycles

Delays of less than 1021 instruction cycles can be done using a looping structure. However the delays are multiples of 4 instruction cycles. LOOP: LDAA #X (1 IC delay) DECA (1 IC delay) BNE LOOP (1(F) or 3(T) IC delay)
Total Delay = ( 4 * X ) -1 Instruction Cycles.
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I/O
Delays of less than 262,141 instruction cycles
Delays of less than 262,141 instruction cycles can be done using a similar looping structure as above. The delays are still multiples of 4 instruction cycles. LDX #X (2 IC delay) LOOP: DEX (1 IC delay) BNE LOOP (1(F) or 3(T) IC delay) Total Delay = ( 4 * X ) Instruction Cycles.
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I/O
Delays greater than 262,140 instruction cycles
Delays of greater than 262,140 instruction cycles can be done using a nested loop structure. The delays are approximately multiples of 4 instruction cycles. OLOOP: ILOOP: LDY #Y LDX #X DEX BNE ILOOP DEY BNE OLOOP (2 IC delay) (2 IC delay) (1 IC delay) (1(F) or 3(T) IC delay) (1 IC delay) (1(F) or 3(T) IC delay)
Total Delay = ( 4 * Y ) + ( Y * ( 4 * X ) ) Instruction Cycles.
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I/O
Example
Assuming an instruction cycle of 125ns, generate the following waveform on the pin PH7.
PH7 750ns 2.5us 120ms
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I/O
Example (continued)
In order to produce the waveform on PH7. We will need to write a program that does the following: Writes '0' to PH7 Waits 6 Instruction cycles Writes '1' to PH7 Waits 20 Instruction cycles Writes '0' to PH7 Waits 960,000 Instruction cycles Writes '1' to PH7
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I/O
Example (continued)
BCLR NOP NOP NOP NOP NOP NOP BSET LDAA DECA BNE BCLR PTH,%10000000
PTH,%10000000 #5 ;( X*4 )-1 = 20 , X=5.25 rounded down. LOOP PTH,%10000000
LOOP:
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I/O
Example (continued)
OLOOP: ILOOP: LDY LDX DEX BNE DEY BNE BSET #10 #23,999 ILOOP OLOOP PTH,%10000000
Total Delay = ( 4 * Y ) + ( Y * ( 4 * X ) ) Instruction Cycles pick a value for Y, say 10 then solve for X. 960,000 =4 * 10 + (10 * 4 * X) = 40 + 40X X = (960,000 40 )/ 40 = 23,999
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Polled I/O
Because I/O devices operate a lot slower than the microprocessor. There needs to be mechanisms in place to cause the processor to wait, until the I/O device is ready before the microprocessor requests or sends information to the I/O device. An I/O device will generally a have a status register mapped into the memory of the microprocessor. The status register will contain bit sized ags to tell the microprocessor when the I/O device is ready to receive or send information. Therefore in order for the microprocessor to know when the device is ready, it needs to constantly check the status bit before communicating with the device. The act of continually checking a status bit is commonly referred to as polling.
I/O
I/O Device
Ready Status ag
Data
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Polled I/O
Assume our microprocessor is connect to an I/O device via two GPIO ports. The data to the device is provided via Port A and the status of the devices is read via PB7. Ready ag
('1' = RDY)
I/O
I/O Device Data

PB7 PA[7:0]
mainLoop: MOVB MOVB LDAA Wait: BRCLR STAA #$FF,DDRA #$7F,DDRB Data PORTB,%10000000,Wait PORTA
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Hardware Handshaking In situations were the processor is talking to an extremely slow device or it is extremely important that information is transferred correctly, then hardware handshaking may be used. Hardware handshaking consists of two devices talking to each other.
The rst system requests the information from the second system, The second system then noties the rst system when the information requested is ready to be read The rst system then reads the information and acknowledges that it has read the information.
I/O
I/O Device
Data
Request Data Flag
Acknowledge Flag
Read Ready ag
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Parallel I/O
Example
mainLoop: MOVB MOVB BSET NOP NOP BCLR BRCLR MOVB BSET NOP NOP BCLR BRA #$00, DDRA #$%11111101, DDRB PORTB, %00000001 PORTB, %00000001 PORTB,#%00000010,LOOP PORTA, Data PORTB, %00000100 PORTB, %00000100 Spin
Request Data Flag ('1' = RQD)
Read Ready ag
('1' = RDY)
I/O Device
Data PB0 PB1 PB2 PA[7:0]
LOOP:
Spin:
P
Acknowledge Flag ('1' = ACK)
Set Request Flag
Wait for Data
Read Data
Set Acknowledge Flag

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Topic Video 04

Introduction to Input and Output (GPIO)

Saturday, 29 August 2009

Input / Output (I/O)

Saturday, 29 August 2009

Saturday, 29 August 2009

Memory Mapped I/O

PORTA PORTB DDRA DDRB ....

Input / Output (I/O)

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Input / Output (I/O)

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STAA PORTA ;Software tells processor to write to Port A.

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Driven I/O Example

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Normal Single Chip Mode

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Programmers I/O Model

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See A/D Topic See A/D Topic

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Saturday, 29 August 2009

Saturday, 29 August 2009

Input and Output Pin Electronics

Saturday, 29 August 2009

Input and Output Pin Electronics

Saturday, 29 August 2009

Saturday, 29 August 2009

Saturday, 29 August 2009

In I/O software there are three major components of the software:

Saturday, 29 August 2009

Saturday, 29 August 2009

Timing Diagrams: Simple Example

A timing diagram showing the changes in logic levels over time.

Saturday, 29 August 2009

Timing Diagrams: Not so Simple Example

Saturday, 29 August 2009

Saturday, 29 August 2009

Saturday, 29 August 2009

Delays of less than 1021 instruction cycles

Total Delay = ( 4 * X ) -1 Instruction Cycles.

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Delays of less than 262,141 instruction cycles

Saturday, 29 August 2009

Delays greater than 262,140 instruction cycles

Total Delay = ( 4 * Y ) + ( Y * ( 4 * X ) ) Instruction Cycles.

Saturday, 29 August 2009

PH7 750ns 2.5us 120ms

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PTH,%10000000 #5 ;( X*4 )-1 = 20 , X=5.25 rounded down. LOOP PTH,%10000000

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I/O Device Data