Digital Logic And Computer Organization UNIT III 3.

0) Introduction
A microcomputer performs a task by reading and executing the set of instructions written in its memory. This set of instructions, written in a sequence, is called a program. Each instruction in the program is a command, in binary, to the microprocessor to perform an operation. This chapter explains in detail the basic instructions, their operations and addressing modes.

3.1) Objectives
In this Unit you will learn about: Introduction Computer Internals Types of Instructions Classification of Instructions Looping and Counting Interconnection of Units Internal working of CPU. Modes of Addressing Stacks and Queues Subroutines Parameter Passing

3.2) Content 3.2.1. Memory

The primary memory is the main storehouse of the computer. It stores programs, input values, output values and the intermediate results of processing. The primary storage locations are each identified by a unique address. The size of this storage location varies from computer to computer.

3.2.2. Registers
Besides the primary memory, the CPU has other special storage locations called the Registers. Registers may be defined as special purpose temporary storage locations in the CPU, which are distinct from the primary memory. Even though the primary memory storage locations and the registers of the CPU are both used for storing data or program instructions and are designed with the same elements of circuits, they are quite distinct from one another by usage. The primary memory locations

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are accessible to the user and the user may write program, data etc into it. The registers are accessible only to the control unit of the CPU and the user has no access to it. Information in a memory location is permanent, that is, once stored; information is not deleted unless it is explicitly done so by a program instruction. Information on the register, on the other hand, is temporary; it is automatically replaced with other information as per the requirements and directions of the control unit. General Registers Each of the 32-bit general registers of the 8086 architecture is accessible by different names, which specify parts of that register to be used. For example, the AX register can be accessed as a single byte (%ah or %al), a 16-bit value (%ax) or a 32-bit value (%eax). The figure below shows the names of these registers and their relation to the full 32-bit storage for each register:

Figure 5.1: General Registers Floating-Point Registers Register %st %st(0) - %st(7) Segment Register Register Description %cs code segment register %ss stack segment register %ds data segment register %es data segment register (string operation destination segment) %fs data segment register %gs data segment register

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Other Registers Register Description %cr0 - %cr3 control registers %db0 - %db7 debug registers %tr3 - %tr7 test registers Registers in the CPU A Register is a special purpose temporary storage location found within the CPU. There are a number of registers used for different purposes by the control unit. Registers can be of two types, operational and storage. Storage registers are used only for storage. They are made of circuits for storage such as flip-flops. An operational register consists of flipflops along with some combinational gates. These electronic circuits can do simple arithmetic operations and the resulting values are stored in the flip-flops in these registers. Some of the more important registers and their functions are given below: The Accumulator This is a very important register found in the ALU. It is an operational register. Arithmetic and logic operations are done on this register and the results of the operations can also be stored here till further action. Program Counter or Sequence Control Register This register holds the address of the instruction, which is to be executed. The control unit takes the address from this register, accesses that location and reads the instruction contained there for execution. The PC is automatically incremented by one as the instructions are kept sequentially in adjacent memory locations. If an instruction for jump or branch is encountered, the address of the instruction to which control is to be passed, is written on the PC by the control unit. From this value onwards the PC is again automatically incremented by one till another jump or halt instruction is executed. Current Instruction Register (CIR) All instructions are kept in memory. The particular instruction, which is to be executed by the control unit, is first moved from the memory to the Current Instruction Register (CIR). The control unit can interpret the instruction only when it is placed in the CIR. The memory is only a storage area. Memory Address Register This register always holds the address of the memory location, which is to be accessed (either for reading or writing). Any address, either of an instruction word or of an operand, has to be placed on this register. The control unit can accept addresses only from this register for accessing that location. Page 80

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Memory Data Register This register is also called the Memory Buffer Register (MBR). All data values, which are to be moved from one register or vice versa, pass through this Memory Data Register. Just as the MAR holds the address of the location to be accessed, MDR holds the data, which is to be written or read from that location. For example, if it is required to store the contents of the accumulator in the location x, then the address x is kept in MAR while the value found in the accumulator is put on MDR. The control unit accesses the address as given by the MAR and writes the value found on the MDR into it. All data are thus first lodged in the MDR before they are moved to their final destination. Besides these registers there are many other registers used by the control unit for the execution of instructions.

3.2.3. The Memory Word

A word of memory refers to one addressable storage locations. This word may contain data or a program instruction as both are kept in the same primary memory. Infact, no special areas are allocated within the CPU memory for programs and data. They may occupy any location within the CPU memory. Moreover, the contents of these words are also similar, both being strings of 0s and 1s. It is the responsibility of the programmer, to keep track of the contents of every location. When programs are written in high level languages, these are taken care of by the Operating System and the compiler and the programmer is not aware where each value is stored. The word storing data is identified as the DATA WORD and the word storing an instruction as the INSTRUCTION WORD. A Data word stores a data item and numeric and non-numeric data are kept in this word. The EBCDIC, BCD, ASCII and other codes are used for representing non-numeric data while numeric values are represented as their binary values in the signed magnitude form or twos complement form or in the normalized floating point representation. 0 1 1 0 01 10001011 11100.. 10001100 10010001

10001001

An instruction word normally stores one program instruction in machine language. Instructions in machine language are generally micro instructions as against the instruction in a high level language which are macro instructions. A macro instruction is a complex instruction which has to be broken down to several simple instructions of machine language. For instance, an instruction such as A = B+C 2 in a High Level Language will result in the following set of simple instructions in machine language. Clear the accumulator and add C Multiply the contents of the accumulator by C Add B to the contents of the accumulator = CLA C = MUL C = ADD B

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Store the contents of the accumulator in the storage = STO A Storage location A Even the simple microinstruction should specify what operation is to be done and on what data. Since they are kept in memory locations, the instruction will give the address of the locations and not the data value. Hence a typical Instruction consists of two parts; the instruction for operation and the operand address. Example ADD A SUB B ADD, SUB are the instructions and A and B are the symbolic address of the operands. Correspondingly an Instruction word has two fields: The operation code field called the Op-Code part. The operand address field called the Address part. OP-CODE 00110101 OPERAND ADDRESS 0000 0011011011011011

The number of bits in these two parts will be decided by the number of distinct instruction that the computer is expected to execute and the memory size of the computer. Suppose the instruction word of a machine is 32-bits long. Of these let 6 bits be allocated for the op-code and 26 bits for the operand address. Since the op-code has 6 bits it can represent 26=64 distinct combinations. Therefore, if each combination represents an instruction, the machine is capable of performing 64 instructions. The address part has 26 bits and therefore, the memory size can be atmost 226=216K words. If op-code is allocated a bit less and is allocated a bit more to the address part, then The no. of possible instructions Maximum memory size possible = 25 = 32 = 227 = 217 K words

The number of instructions that the computer is capable of executing is halved, while the maximum possible memory size is doubled. Both these can be simultaneously increased or decreased by increasing or decreasing the word size. The optimal values of the word size, the op-code size and the operand address size are decided at the time of designing the computer.

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Example Calculate the maximum possible memory that can be directly addressed by a 16-bit computer which has an instruction set of 32 instructions. No of instructions possible = 32 = 2^5 Therefore minimum op-code size = 5 bits Word size = 16 bits Therefore, maximum operand address size = 11 bits Therefore, maximum memory size possible = 2^11 words = 2 K words Addressing the I/O Devices In any microcomputer, the microprocessor will be connected to the memory and I/O devices. A microprocessor addresses any memory location. The method of connecting I/O devices to a processor is known as memory mapped I/O. However, it is also possible to treat I/O devices as distinct from the memory and assign them addresses that do not conflict with memory addresses. According to this scheme, an address such as 5 could be address of a memory location as well as an I/O device. This scheme is known as I/O mapped I/O. 3.2.4. Types of Instructions One instruction word has an op-code part and an operand address part. This is not necessarily the only format for an instruction. There are other formats, designed from time to time to suit the changing architecture of computers. The more common ones are: The four address instruction word The three address instruction word The two address instruction word The single address instruction word The zero address instruction word Four address instruction word This has an op-code part followed by four more fields each containing an address. OP-CODE Address 1 Address 2 Address 3 Address 4

The first two addresses give the addresses of the two operands on which the binary operation is to be done. The third address is the address where the result of the operation is to be stored. The fourth address gives the address of the memory word which contains the next instruction.

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Example Consider the instruction c = a + b ADD Add of A Add of B Add of C Add x of next instruction

Address 1 and 2 will give the addresses of a and b respectively. Address 3 will be the address of c while address 4 will be the address of the next instruction. The op-code will contain the code for addition. All the address fields may not be always used. Even though bigger instructions can be represented with this format, the 4-address instruction is not popular because of the following reasons: The execution of these instructions is very slow The word length is divided among five fields thus making each short. This is turn restricts the accessible memory size of the computer. The word size cannot be arbitrarily increased without adding other constraints in the design of a computer. The Three address instruction In this format, the op-code is followed by three addresses, the two operand addresses and the address where the result of the operation is to be stored. The address of the next instruction is not given. Then how does the computer know where to find the next instruction? Instructions are kept sequentially in adjacent memory locations and they are taken up one after the other automatically. OP-CODE ADD Add 1 A Add 2 B Add 3 C

The three address instruction format is only a small improvement over the four address format and suffers from all the drawbacks of the four address format. The Two address instruction In this type of instruction format, both the operand addresses are not given. One of the operands is made available on a register called the accumulator and its address is therefore not required. The operation code, the address of one operand and the address of the result are given. OP-CODE ADD Address of A A Address of C C

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The above instruction will add A to the contents of the accumulator and store in C. In this case before adding A & B, B has to be moved to the accumulator to achieve C = A + B. Hence the instruction is split into two smaller instructions. Move B to the accumulator Add A to accumulator and store in C Even though the number of instructions are more, due to the lesser number of fields, the lengths of each field is longer in an instruction word. Two-address instruction word format is widely used in large machines. The Single address instruction This is the most popular format among personal computers. Here the op-code is followed by operand address only. The other operand is made available on the accumulator by suitable instructions. The results of the operation are left in the accumulator itself. It is moved to the required location by another instruction. The instruction C = A + B will thus be split into: Move B to the accumulator Add A to the accumulator Move the contents of the accumulator to C Each instruction involves only one operand and one operation. Single address instruction format can provide more number of bits to the op-code and operand address. This means that they are capable of accessing a fairly big memory size for a given word size. However, the number of instructions in a program will be large as each instruction is a simple micro instruction. The Zero address instruction In this format no address is given, that is, the instruction consists of only the op-code.
Op _ code

The addresses of the operands as well as the locations where the results are to be stored are available in a stack in memory. These are of course special types of instruction and find use in special procedures in machine language programs. 3.2.5. Classification of Instructions For the convenience of programmers, the 8085 instructions have been classified into the following five groups:

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Data transfer group Arithmetic group Logical group Branch group Stack, I / O and Machine control group. Data Transfer (Copy) Operations One of the primary functions of the microprocessor is copying data, from a register (or I/O or memory) called the source, to another register (or I/O or memory) called the destination. In technical literature, the copying function is frequently labeled as the data transfer function, which is somewhat misleading. In fact, the contents of the source are not transferred, but are copied into the destination register without modifying the contents of the source. Several instructions are used to copy data. This section is concerned with the following operations. MOV MVI OUT IN : : : : Move Move Immediate Output to Port Input from Port Copy a data byte. Load a data byte directly. Send a data byte to an output device. Read a data byte from an input device.

The term copy is equally valid for input/output functions because the contents of the source are not altered. However, the term data transfer is used so commonly to indicate the data copy function. Apart from data copy instructions, the following machine control operations are also used in programs. HLT NOP : : Halt No operation Stop processing and wait. Do not perform any operation.

The following example illustrates various operations. Instructions. The data transfer instructions copy data from a source into a destination without modifying the contents of the source. The previous contents of the destination are replaced by the contents of the source. Opcode MOV Operand Rd, Rs Description Move This is a 1-byte instruction Copies data from source register Rs to destination register Rd Move Immediate

MVI

Rd, 8-bit

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This is a 2-byte instruction Loads the 8 bits of the second byte into the register specified OUT 8-Bit Port Address Output to Port This is a 2-byte instruction Sends (copies) the contents of the accumulator (A) to the output port specified in the second byte Input from Port This is a 2-byte instruction Accepts (reads) data from the input port specified second byte and loads into the accumulator. HLT Halt This is a 1-byte instruction The processor stops executing and enters wait state The address bus and data bus are placed in high impedance state. No register contents are affected. No Operation This is a 1-byte instruction No operation is performed Generally used to increase processing time or in place of an instructions. When an error occurs in program and an instruction needs to be eliminated, it is more convenient to substitute NOP than to reassemble the whole program. Example Load the accumulator A with the data byte 82H (the letter H indicates hexadecimal number) and save the data in register B. Instructions MVI A, 82H, MOV B, A

IN in the

8-Bit Port Address

NOP

substitute

The first instruction is a 2-byte instruction that loads the accumulator with the data byte 82H and the second instruction MOV B, A copies the contents of the accumulator in register B without changing the contents of the accumulator.

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Arithmetic Operations The microprocessor performs various arithmetic operations, such as addition, subtraction, increment and decrement. These arithmetic operations have the following mnemonics. ADD: Add ADI: Add Immediate SUB: Subtract SUI: Subtract Immediate INR: Increment DCR: Decrement Add the contents of a register.* Add 8-bit data. Subtract the contents of a register Subtract 8-bit data. Increase the contents of a register by 1. Decrease the contents of a register by 1.

These arithmetic operations are performed in relation to the contents of the accumulator. However, the Increment or the Decrement operations can be performed in any register. Addition The microprocessor performs addition with 8-bit binary numbers and stores the sum in the accumulator. If the sum is larger than eight bits (FFH), it sets the Carry flag. Addition can be performed either by adding the contents of a source register (B, C, D, E, H, L or memory) to the contents of the accumulator (ADD) or by adding the second byte directly to the contents of the accumulator (ADI). Subtraction The microprocessor performs subtraction by using the method of 2's complement. Subtraction can be performed either by using the instruction SUB to subtract the contents of a source register or the instruction SUI to subtract an 8-bit number from the contents of the accumulator. In either case, the accumulator contents are regarded as the minuend (the number from which to subtract). The microprocessor performs the following steps internally to execute the instruction SUB (or SUI). Step 1: Converts subtrahend (the number to be subtracted) into its 1's complement. Step 2: Adds 1 to 1's complement to obtain 2's complement of the subtrahend. Step 3: Adds 2's complement to the minuend (the contents of the accumulator). Step 4: Complements the Carry flag. These steps are illustrated in the following example. Features Of Arithmetic Operations The arithmetic operations implicitly assume that the contents of the accumulator are one of the operands. The results of the arithmetic operations are stored in the accumulator; thus the previous contents of the accumulator are altered. The flags are modified to reflect the data conditions of an operation. The contents of a register are not changed as a result of an arithmetic operation Page 88

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In the add operation, if the sum is larger than 8-bit CY is set. The subtract operation is performed by using the 2's complement method and CY is complemented after the subtraction. If a subtraction results in a negative number, the answer is in 2's complement and CY (the Borrow flag) is set. In unsigned arithmetic operations, the Sign flag (S) should be ignored. The instructions INR (Increment) and DCR (Decrement) are special cases of the arithmetic operations. These instructions can be used for any one of the registers and they do not set CY, even if the result is larger than 8-bit. Flags The flags are flip-flops that are set or reset after the execution of arithmetic and logic operations, with some exceptions. Flags are signs of data conditions. After an operation, one or more flags may be set and using Jump instructions, which will be described later, can use them to change the direction of the program sequence. However, the programmer should be alert for them to make a decision. If the flags are not appropriate for the tasks, the programmer can ignore them. The main features of flags are: If the programmer ignores the flag, it can be lost after the subsequent instructions. However, the flag can be ignored when the programmer is not interested in using it. The programmer may use one or more flags to make decisions or may ignore them if they are irrelevant. The CY flag has a dual function; it is used as a carry in addition and as a borrow in subtraction. Logic Operations A microprocessor is basically a programmable logic chip. It can perform all the logic functions of the hard-wired logic through its instruction set. The microprocessor instruction set includes such logic functions as AND, OR, Ex OR and NOT (complement). The opcodes of these operations are as follows: AND : AND Logically AND the contents of a register. ANI : AND Immediate Logically AND 8-bit data. ORA : OR Logically OR the contents of a register. ORI : OR Immediate Logically OR 8-bit data. XRA : X-OR Exclusive-OR the contents of a register. XRI : X-OR Exclusive-OR 8-bit data. All logic operations are performed in relation to the contents of the accumulator. The instructions of these logic operations are described below. The logic instructions implicitly assume that the accumulator is one of the operands. reset (clear) CY and AC flags. The instructions ANA and ANI in the 8085 and CMA are exceptions to this. Page 89

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modify Z, P and S flags according to the data conditions of the result. place the result in the accumulator. do not affect the contents of the operand register. Opcode ANA with the contents of the accumulator 8085. ANI contents of the accumulator 8085. ORA with the contents of the accumulator ORI of the accumulator XRA the contents of the accumulator XRI contents of the accumulator CMA Complement Accumulator This is a 1-byte instruction that complements the contents of the accumulator No flags are affected 8-bit Exclusive-OR Immediate with Accumulator This is a 2-byte instruction Exclusive-ORs the second byte with the R Logically Exclusive-OR with Accumulator This is a 1-byte instruction Exclusive-ORs the contents of register R with 8-bit OR Immediate with Accumulator This is a 2-byte instruction Logically ORs the second byte with the contents R Logically OR with Accumulator This is a 1-byte instruction Logically ORs the contents of the register R 8-bit AND Immediate with Accumulator This is a 2-byte instruction Logically ANDs the second byte with the Operand R Description Logical AND with Accumulator This is a 1-byte instruction Logically ANDs the contents of the register R

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Logic AND The process of performing logic operations through the software instructions is slightly different from the hardwired logic. The AND gate shown in Figure 5.7(a) has two inputs and one output. On the other hand, the instruction ANA simulates eight AND gates (Figure.5.1(b)). For example, assume that register B holds 77H and the accumulator A holds 81H. The result of the instruction ANA B is 01H and is placed in the accumulator replacing the previous contents as shown in Figure 5.1(b)

Figure 5.2: (a) AND Gate (b) Simulated ANA Instruction Figure 5.2(b) shows that each bit of register B is independently ANDed with each bit of the accumulator, thus simulating eight 2-input AND gates. To simulate one 2-input AND gate, all other bits can be masked or eliminated, as illustrated in the next program. OR, Exclusive-OR and NOT The instructions ORA (and ORI) simulates logic ORing with eight 2-input OR gates; this process is similar to that of ANDing, explained in the previous section. The instruction XRA (and XRI) performs Exclusive-ORing of eight bits and the instruction CMA inverts the bit of the accumulator. Example Assume register B holds 93H and the accumulator holds 15H. Illustrate the results of the instructions ORA B, XRA B and CMA The instruction ORA B will perform the following operation: (B) OR (A) = 0 0 0 1 0 1 0 1 ___________________________ (A) = 1 0 0 1 0 1 1 1 Page 91 (15H) (97H) = 1 0 0 1 0 0 1 1 (93H)

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Flag Status: S = 1, Z = 0, CY = 0 The result 97H will be placed in the accumulator, the CY flag will be reset and the other flags will be modified to reflect the data conditions in the accumulator. The instruction XRA B will perform the following operation. (B) X-OR (A) = 0 0 0 1 0 1 0 1 ___________________________ (A) = 1 0 0 0 0 1 1 0 Flag Status: shown. The instruction CMA will result in (A) CMA (A) = 1 1 1 0 1 0 1 0 (EAH) The result EAH will be placed in the accumulator and no flags will be modified. Features of Logic Operations Logic operations are performed in relation to the contents of the accumulator. Logic operations simulate eight 2-input gates (or inverters). The Sign, Zero (and Parity) flags are modified to reflect the status of the operation. The Carry flag is reset. However, the NOT operation does not affect any flags. After a logic operation has been performed, the answer is placed in the accumulator replacing the original contents of the accumulator. The logic operations cannot be performed directly with the contents of two registers. The individual bits in the accumulator can be set or reset using logic instructions. Branch Operations The branch instructions are the most powerful instructions because they allow the microprocessor to change the sequence of a program, either unconditionally or under certain test conditions. These instructions are the key to the flexibility and versatility of a computer. The microprocessor is a sequential machine; it executes machine codes from one memory location to the next. Branch instructions instruct the microprocessor to go to a different = 0 0 0 1 0 1 0 1 (15H) S = 1, Z = 0, CY = 0 (15H) (86H) = 1 0 0 1 0 0 1 1 (93H)

The result 86H will be placed in the accumulator and the flags will be modified as

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memory location and the microprocessor continues executing machine codes from that new location. The address of the new memory location is either specified explicitly or supplied by the microprocessor or by extra hardware. The branch instructions are classified in three categories. Jump instructions Call and Return instructions Restart instructions The Jump instructions specify the memory location explicitly. They are 3-byte instructions: one byte for the operation code, followed by a 16-bit memory address. Jump instructions are classified into two categories: Unconditional Jump and Conditional Jump. Unconditional Jump The microprocessor instruction set includes one unconditional Jump instruction. The unconditional Jump instruction enables the programmer to set up continuous loops. Opcode JMP memory address. However, the second byte specifies the loworder and the third byte specifies the high-order memory address. For example, to instruct the microprocessor to go to the memory location 2000H, the mnemonics and the machine code entered will be as follows: Machine Code C3 00 20 Mnemonics JMP 2000H Operand 16-bit Description Jump This is a 3-byt instruction The second and third bytes specify the 16-bit

Note the sequence of the machine code. The 16-bit memory address of the jump location is entered in the reverse order, the low-order byte (00H) first followed by the high-order byte (20H). The microprocessor is designed for such a reverse sequence. The jump location can also be specified using a label. While writing a program, the exact memory location to which a program sequence should be directed may not be known. In that case, the memory address can be specified with a label (or a name). This is particularly useful and necessary for an assembler. However, both a label and its 16-bit address should not be specified in a Jump instruction. Furthermore, the same label cannot be used for different memory locations. Page 93

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Conditional Jumps Conditional Jump instructions allow the microprocessor to make decisions based on certain conditions indicated by the flags. After logic and arithmetic operations, flip-flops (flags) are set or reset to reflect data conditions. The conditional Jump instructions check the flag conditions and make decisions to change or not to change the sequence of a program. Flags The microprocessor status register has five flags, one of which (Auxiliary Carry) is used internally. The other four flags used by the Jump instructions are Carry flag Zero flag Sign flag Parity flag Two Jump instructions are associated with each flag. The sequence a program can be changed either because the condition is present or because the condition is absent. For example, while adding the numbers the program sequence can be changed either because the carry is present (JC = Jump On Carry) or because the carry is absent (JNC = Jump On No Carry). Instructions All conditional Jump instructions in the microprocessor are 3-byte instructions; the second byte specifies the low-order (line number) memory address and the third byte specifies the high-order (page number) memory address. The following instructions transfer the program sequence to the memory location specified under the given conditions: Opcode JC 1) JNC JZ JNZ JP JM JPE JPO Operand 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit Description Jump On Carry (If result generates carry and CY = Jump On No Carry (CY = 0) Jump On Zero (If result is zero and Z = 1) Jump On No Zero (Z = 0) Jump On Plus (If D7 = 0 and S = 0) Jump On Minus (If D7 = 1 and S = 1) Jump On Even Parity (P = 1) Jump On Odd Parity (P = 0)

All the Jump instructions are listed here for an overview. The Zero and Carry flags and related Jump instructions are used frequently. They are illustrated in the following examples.

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Features of Jump Instructions The Jump instructions change program execution from its sequential order to a different memory location. The Jump instructions can transfer program execution ahead of the sequence (Jump Forward) or behind the sequence (Jump Backward). The unconditional Jump is, generally, used to set up continuous loops. The conditional Jumps are used for the decision-making process based on the data conditions in the accumulator (or of the result), reflected by the flags. Arithmetic and logic instructions modify the flags according to the data in the accumulator (or of the result) and the conditional branch instructions use them to make decisions. However, the branch instructions do not affect the flags. Looping and Counting The programming technique used to instruct the microprocessor to repeat tasks is called looping. Instructing the microprocessor to change the sequence of execution and perform the task again sets up a loop. This process is accomplished by using Jump instructions. In addition, techniques such as counting and indexing (described below) are used in setting up a loop. Loops can be classified into two groups: Continuous Loop repeats a task continuously. Conditional Loop repeats a task till certain data conditions are met Continuous Loop Using the unconditional Jump instruction shown in the flowchart sets up a continuous loop.A program with a continuous loop does not stop repeating the tasks until the system is reset. Typical examples of such a program include a continuous counter or a continuous monitor system.

Figure 5.3: Flowchart of a Continuous Loop

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Conditional Loop A conditional loop is set up by the conditional Jump instructions. These instructions check flags (Zero, Carry, etc.) and repeat the specified tasks if the conditions are satisfied. These loops usually include counting and indexing. Conditional Loop And Counter A counter is a typical application of the conditional loop. For example, how does the microprocessor repeat a task five times? The process is similar to that of a car racer in the Indy 500 going around the track 500 times. How does the racer know when 500 laps have been completed? The racing team manager sets up a counting and flagging method for the racer. This can be symbolically represented as in Figure 5.3(a). A similar approach is needed for the microprocessor to repeat the task five times. The microprocessor needs a counter; and when the counting is completed, it needs a flag. This can be accomplished with the conditional loop, as illustrated in the flowchart in Figure 5.3(b). The computer flowchart is translated into a program as follows: Counter is set up by loading an appropriate count in a register. Counting is performed by either incrementing or decrementing the counter. Loop is set up by a conditional Jump instruction. End of Counting is indicated by a flag. It is easier to count down to zero than to count up because the Zero flag is set when the register becomes zero. Conditional Loop, Counter and Indexing Another type of looping includes indexing along with a counter. (Indexing means pointing or referencing objects with sequential numbers. In a library, books are arranged according to numbers and they are referred to or sorted by numbers. This is called indexing.) Similarly, data bytes are stored in memory locations and those data bytes are referred to by their memory locations.

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Figure 5.4: Flowcharts to Indicate Number of Repetitions Completed 3.2.6. Interconnection of Units As all data to be processed by a computer has to be stored in memory, the characteristics of the interconnection paths are determined by the memory structure. In order to achieve reasonable speed, all the bits in a word are transmitted simultaneously. A set of wires, which carries a group of bits in parallel and has an associated control scheme is known as a bus. A bus, which carries a word to or from memory is known as a data bus. Its width will equal the word length (in bits) of the memory. In order to retrieve a word from memory it is necessary to specify its address. A Memory address bus whose width equals the number of bits in the MAR of the memory carries the address. Thus if a computers memory has 64KB, 32 bit words, then the data bus will be 32 bits wide and the address bus 16 bits wide. Besides buses to carry address and data, control signals are needed between the units of a computer. For instance, if a command to I-O units is to be sent, a control bus carries suchDAB signals. A system bus will thus MAB consist of a data bus, a memory address bus and a control bus. Figure 5.4 shows the processor memory interconnection.
DB

Figure 5.5: Processor Memory Interconnection

PROCESSOR
CB

DB

I-O UNITS I-O to Processor

Communication

CB

MEMORY

DAB DB

Device Address Data Bus

Bus

CB MAB

Control Bus Memory Address Bus

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One way of connecting I-O units to the computer is to connect them to the processor using a device address bus, a data bus and a control bus. Each device in a computer has a controller which controls the operation of the device. For example, a floppy disk controller controls the movement of the reading head, positioning of the head and detection of errors. The controllers are connected to the buses via an interface logic unit. The interface logic decodes the control commands received from the processor and sends them to the controller. It also buffers the flow of data from the device to the processor and vice versa. Figure 5.5 illustrates the details of one interface unit. With this connection of IO device to the processor, data from a device is transmitted to the memory through a register in the processor. This method of transfer of information is called Program Controlled Transfer. There is another method of data transfer to the processor which is more efficient. In this method a programmer estimates the time required to read the data from a specified device. The READ command is issued many steps ahead of the time it is actually required in computation. The processor must have enough of other instructions to carry out while the interface fills up the data buffer. When the interface buffer is full and is ready to send the data to the processor, the interface sends a signal to the processor informing it that the data is ready. This signal is known as an interrupt signal. When the processor receives the interrupt signal it knows that the data it asked for is ready. It suspends its current job and transfers the data from the interface data register to its own register.

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MEMORY

MAB

CB

DB DAB

Data ready Flip-flop

DC and DB

DEVICE AND CONTROLLER

PROCESSOR REGISTER
CB

Busy flip-flop INTERFACE

DATA REGISTER DB

MAB DB DAB CB DC

- Memory Address Bus - Data Bus - Device Address Bus - Control Bus - Device Control

Figure 5.6: Interface unit Interrupt Structures An interrupt signal is a signal sent by an I-O interface to the processor when the I-O is ready to send or receive data to or from memory. The processor completes the instruction it is processing and acknowledges the interrupt signal. It then preserves the information needed to resume the program it was executing and jumps to another program called an interrupt service routine to cater to the I-O read/write requirement. An interrupt servicing procedure consists of the following steps: Step 1: An interrupt signal is received by the processor. Step 2: The processor completes the present instruction being executed. Step 3: The processor stores the contents of the program counter and other register in the processor in a reserved area in memory. This information is required to enable the processor to resume the program it was executing. Step 4: The processor sends an interrupt acknowledge signal to the interrupting Page 99

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I-O interface. It suspends the current program it is executing and jumps to another program already stored in memory to service the interrupt. Step 5: The interrupt servicing program carries out the required transfer of information from or to the specified I-O device. The last instruction in the interrupt servicing program restores the contents of all the processor register including the program counter which was stored in the memory by the suspended program. Step 6: The suspended program is resumed. Interrupts caused by events occurring outside the processor such as I-O, power failure, high voltage, etc. are called external interrupts. There is another class of interrupts known as internal interrupts or traps which occur when there is a mistake in a users program. Common mistakes which lead to traps are: attempt to divide by zero, accumulator overflow or underflow and illegal operation code. When such an error is detected by the processor, it interrupts a users program and branches to a trap routine which usually prints out the value of PC and other registers when the trap occurred and a message giving the possible reason for the trap. The Internal Working of the CPU The CPU or the Central Processing Unit processes all data within the computer. The control unit fetches an instruction from the memory and executes it, then fetches the next instruction and executes it and so on in a rhythmic manner but at an incredibly high speed. An electronic clock within the CPU synchronizes these operations of the control unit. This clock emits pulses at regular intervals (of microseconds and less). These clock pulses control the cyclic rhythm of the control units. The Fetch and Execute Cycle Every instruction cycle of the CPU involves two cycles called the Fetch and Execute cycles. The Fetch Cycle The process of fetching an instruction from the memory to the CIR (Current Instruction Register) is known as the fetch cycle. During this cycle the control unit does the following operations: The address of the instruction is obtained from the Program Counter and placed on the MAR. The address given by the MAR is accessed and the instruction in it is fetched, that is, copied on to the memory data register. The instruction is moved from the MDR to the current instruction register.

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The PC is incremented by 1.

Figure 5.7: Fetch Cycle The Execute Cycle During this cycle, the instruction found in the CIR is interpreted and executed by the control unit. The following operations are involved in an execute cycle: The control unit moves the operand address from the instruction word and passes it on to the decoder. The decoder interprets the address (The address is not at all given directly in an instruction.) and puts the address of the operand on the MAR. The data from this address as given by MAR is fetched and moved to the MDR (if necessary). The control unit simultaneously interprets the op-code part of the instruction and the necessary operations is done by moving (if necessary) the data from the MDR to the accumulator.

Figure 5.8: Fetch Cycle

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Example
ADD STO A C

Instruction ADD A is kept in the location 512. A is the location 1326 and contains the value 5.3 in it. The following steps will be involved in the fetch cycle of executing this instruction. The address 512 will be available on the PC. This is passed to the MAR. The address 512 as given by MAR is accessed and the instruction ADD A is copied on MDR. The instruction ADD A from MDR is moved to the CIR. The PC is incremented to 513. During the Execute cycle, the following are done: The instruction in the CIR is interpreted. The operand address A is passed through the decoder to the MAR (1326 is written on MAR). The control unit looks into the MAR and fetches the address 1326 (of A) found in it. The data value 5.3 is moved from this location 1326 and written on the MDR. The op-code of the instruction ADD is interpreted and accordingly the value 5.3 from MDR is moved to the accumulator. The value 5.3 is added to the previous contents of the accumulator and the result left in it. Example Instruction STO is in the location 513 where C is the location 1046. During the fetch cycle The PC address 513 is written on the MAR. The MAR address 513 is fetched. The instruction STO C found in 513 is copied on the MDR. The instruction is moved to the CIR from the MDR. The PC is incremented to 514. During the Execute cycle The instruction in CIR is interpreted. The operand address 1046 of C is put on MAR through the decoder. The op-code is interpreted and the contents of the accumulator moved to MDR. The data given by MDR is written into the address given by MAR. 3.2.7. Modes of Addressing The manner in which the operand addresses are given in the address part of an instruction word is known as addressing.

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Let the word length of a hypothetical machine be 16 bits. If 6 bits are used by the op-code part, the operand address can be at most 10 bits long. With this 10-bit combination it is possible to access a maximum of 2^10 words of memory. The instruction set of the computer can be a maximum of 64 instructions. A larger word size would in turn mean lesser number of memory locations in the same memory. So it is not possible to arbitrarily increase the word size. However, it is possible and this is achieved by changing our mode of addressing. There are five commonly used modes of addressing. Direct addressing Extended addressing Indirect addressing Indexed addressing Immediate addressing Direct Addressing The type of addressing that is considered so far is direct addressing. In this mode, the actual address of the operand is given in the address part of the instruction word. 11010 ..10010101011

This instruction is ADD A. The address 1195 of A is given in binary in the address part of the instruction word. The control unit fetches the data from this location and adds it to the accumulator. Direct addressing is the simplest and the fastest to execute among the various types of addressing. But it suffers from some of the drawbacks discussed earlier. A memory, larger than that permitted by the word size cannot be accessed by this mode of addressing. Extended Addressing When more than one word is used for an instruction, it is known as extended addressing. When two words are used instead of the one 16-bit word shown in direct addressing, a 32bit instruction word results. Then a much longer memory can be easily accessed. The disadvantage is that, due to certain practical reasons, however, extended mode of addressing is not considered a viable alternative to direct addressing. Indirect Addressing In this method of addressing, the address part of the instruction word does not directly give the address where the operand is kept. Instead, it gives the address of another location, which in turn gives the address of the operand. For example, let the operand A(value 13.4) be in the location 1195. This address 1195 will not be given in the

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instruction. This address will be kept in another locations, say, 43 and the instruction word will contain this address 43. ADD 43 In indirect mode, this implies that the value in the location pointed by the location 43 is to be added to the accumulator.
43

1195

ADD

43 -13.4
1195

The advantage in this approach is that the number of bits available for the operand address is equal to 1 word (number of bits in the op-code). Hence, if the word size is 16 bits and op-code 5 bits, the address part can have 11 bits only. When a different location is used for giving the operand address, the full word of 16 bits is available for giving the address. Hence these sixteen bits can access a bigger memory of 216 K. Direct accessing can access a memory of only 211 words. This means that indirect addressing can access a memory 32 times bigger. Thus, indirect addressing mode provides for a much larger memory size for the same word length. At the same time, it is not achieved at no loss. The fetchexecute cycle will be longer, as each accessing actually involves accessing two memory locations. The overall processing time will therefore be much longer. To put it simply, such computer will be a slower machine. Most computer architecture permit both direct and indirect addressing. Then how does the control unit understand whether the addressing is in direct or indirect mode? The first bit (or the leftmost bit or the most significant bit) of the address part of the instruction word is used for indicating the mode of addressing. When this bit is 0, it means that the addressing is direct, when it is 1, it implies that the address following it is in the indirect mode. Indexed Addressing In this method also the address part of the instruction does not directly give the operand address. Instead, the contents of this part are added to the contents of another register called the index register. Thus, large numbers are obtained which permits the accessing of a bigger memory. However, the contents of the index register have to be first determined and loaded through appropriate instruction. It is a more complex process and also slows down the execution of the instruction.

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Op-code

operand address

Index bit 0 direct addressing mode 1 indexed addressing mode

As in indirect addressing, the first bit of the address part is reserved for indicating the mode of addressing. This bit is called the index bit. When it stores a 1 it indicates indexed addressing. When it stores a 0 the addressing is direct. Indexed addressing can be combined with indirect addressing, that is, we may have direct indexed addressing or indirect indexed addressing. Immediate Addressing When the value of the operand instead of the address where it is located, is given in the instruction, the mode of addressing is called immediate. ADD -13.4

The above instruction will instruct the control unit to add -13.4 to the accumulator. This is a very simple method of addressing, as data are readily available on the instruction word itself. However, the number of bits available for the data is more or less than a full word and hence only smaller value can be handled. Moreover, it is not always possible to know the value of the data at the time of writing the instructions. This method of addressing cannot, therefore, be adopted everywhere. Addressing modes are the ways how architectures specify the address of an object they want to access. An addressing mode can specify a constant, a register or a location in memory.
Addressing modes Register Immediate Displacement Register deffered Indexed Direct Memory deferred Autoincrement Example Instruction Add R4,R3 Add R4, #3 Meaning R4 <- R4 + R3 R4 <- R4 + 3 When used When a value is in a register For constants Accessing local variables Accessing using a pointer or a computed address Useful in array addressing: R1 - base of array R2 - index amount Useful in accessing static data If R3 is the address of a pointer p, then mode yields *p Useful for stepping through arrays in a loop. R2 - start of array d - size of an element

Add R4, 100(R1) R4 <- R4 + M[100+R1] Add R4,(R1) Add R3, (R1 + R2) R4 <- R4 + M[R1] R3 <- R3 + M[R1+R2]

Add R1, (1001) R1 <- R1 + M[1001] Add R1, @(R3) R1 <- R1 + M[M[R3]] Add R1, (R2)+ R1 <- R1 +M[R2] R2 <- R2 + d

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Autodecrement Scaled R2 <-R2-d R1 <- R1 + M[R2] Same as autoincrement. Both can also be used to implement a stack as push and pop Used to index arrays. May be applied to any base addressing mode in some machines.

Add R1,-(R2)

Add R1, 100(R2) R1<[R3] R1+M[100+R2+R3*d]

Notation: <- - assignment, M - the name for memory, M[R1] refers to contents of memory location whose address is given by the contents of R1. Table 5.1: The most common names for addressing modes Encoding of Addressing Modes How the addressing modes of operands are encoded depends on: the range of addressing modes. the degree of independence between opcodes and modes. For small number of addressing modes or opcode/addressing mode combinations, the addressing mode can be encoded in opcode. For a larger number of combinations, typically a separate address specifier is needed for each operand. The architect has to balance several competing forces when encoding the instruction set: The desire to have as many registers and addressing modes as possible. The impact of the size of the register and addressing mode fields on the average instruction size and hence on the average program size. 3.2.8. Stacks and Queues A stack is a storage device that stores and retrieves information using Last In First Out (LIFO) concept. The stack in digital computers is a memory unit with an address registers, that can count only after loading a initial value. The register that holds the address of the stack is called the stack pointer (SP). The two operations of a stack are PUSH for insertion and POP for deletion. As the items in the stack are inserted the stack pointer is incremented and when the items are retrieved, the stack pointer is decremented. The following figure shows the 64 word register stack. The stack pointer SP is currently pointing to the 3rd element. Removing the item, decrements the stack pointer. The data register DR holds the binary data to be written into or read from the stack. The stack during insertion is checked if it is full and during retrieval of items is checked if it is empty.

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Address

63

SP

3 2 1 0

DR

Figure 5.9: Block diagram of a 64-word Stack Memory Stack A stack can be implemented in a random-access memory attached to the CPU. The implementation of stack in the CPU is done by assigning a portion of memory to a stack operation and using processor register as a stack pointer. The following figure shows a portion of the computer memory partitioned into three segments namely program, data and stack. The program counter points at the address of the next instruction in the program. The address registers AR points at an array of data. The three registers are connected to the common address bus and either one can provide an address for the memory. PC is used during the fetch phase to read an instruction and AR is used to during the execute phase to read an operand. SP is used to PUSH or POP items into or from the stack.
1000 Address

PC AR

Program (Instructions) Data (Operands) Stack C B A

2000 3000

SP

3997 3998 3999 4000 4001

DR Figure 5.10: Memory with Program, Data and Stack segments

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Queues Similar to stack, queues are also implemented in RAM and work on the concept of First In First Out (FIFO). The items are inserted at the rear end of the queue and deleted from the front end. 3.2.9. Subroutines A set of common instructions written once and called many times in a program is called a subroutine. A subroutine consists of a self-contained sequence of instructions that carries out of a given task. Each time a subroutine is used in the main part of the program, a branch is executed to the beginning of the subroutine. After the subroutine has been executed, branch is made back to the main program. In the basic computer, the link between the main program and a sub-routine is the BSA instruction (branch and save return address). First memory location off each subroutine serves as a link between the main program and the subroutine. The procedure for branching to a subroutine and returning to the main program is referred to as a subroutine linkage. The BSA instruction performs an operation commonly called subroutine call. The last instruction of the subroutine performs an operation commonly called return. Many computers have multiple process registers and some of them are called index registers. An index register is usually used to implement a subroutine linkage. A branchto-subroutine instruction stores the return address in an index register. A return-fromsubroutine instruction is effected by branching to the address presently stored in the index register. 3.2.10. Parameter Passing When a subroutine is called, the main program must transfer the data it wishes the subroutine to work with. It is necessary for the subroutine to have access to data from the calling program and to return results to that program. The accumulator can be used for a single input parameter and a single output parameter. In computers with multiple processors, more parameters can be transferred this way. Another way to transfer data to a subroutine is through memory. Data is placed in the memory location following the call. The return address always gives the link information for transferring data between the main program and the subroutine. For example, consider a program that performs the logic OR operation. Two operands must be transferred to the subroutine and it must return the result of the operation. The accumulator can be used to transfer one operand and receive the result. The other operand is inserted in the location following the BSA instruction. The following program illustrates this example.

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Location 200 201 202 203 204 205 206 207 208 209 20A 20B 20C 20D 20E 20F 210 ORG 200 LDA X BSA OR HEX 3AF6 STA Y HLT HEX 7B95 HEX 0 HEX 0 CMA STA TMP LDA OR I CMA AND TMP CMA ISZ OR BUN OR I HEX 0 END / Load first operand into AC / Branch to subroutine OR / Second operand stored here / Subroutines return here / First operand stored here / Result stored here / Subroutine OR / Complement first Operand / Store in temporary location / Load second operand / Complement second Operand / AND complemented first operand / Complement again to get OR / Increment return address / Return to main program / Temporary storage

X, Y, OR,

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1. The CPU has special storage locations called the Registers. The Accumulator a very important register found in the ALU. 2. A word of memory refers to one addressable storage location. 3. The formats for instruction are the four-address instruction word, the three-address instruction word, the two-address instruction word, the single address instruction word & the zero address instruction word 4. The 8085 instructions have been classified into the following five groups, as Data transfer group, Arithmetic group, Logical group, Branch group & Stack, I / O and Machine control group. 5. The programming technique used to instruct the microprocessor to repeat tasks is called looping. 6. Indexing means pointing or referencing objects with sequential numbers. 7. The five common modes of addressing are Direct addressing, Extended addressing, Indirect addressing, Indexed addressing & Immediate addressing. 8. A stack is a storage device that stores and retrieves information using Last In First Out (LIFO) concept. 9. A Queue is a storage device that stores and retrieves information using First In First Out (FIFO) concept. 10. A set of common instructions written once and called many times in a program is called a subroutine.

3.4) Intext Questions

1. What is Opcode and Operand? 2. What is a Jump instruction? 3. What are the types of flags?

3.5) Summary
A microcomputer performs a task by reading and executing the set of instructions written in its memory. Registers are used to load data directly or to save data bytes. In data transfer (copying), the destination register is modified but the source register retains its data. The microprocessor transfers data from an input port to the accumulator (IN) and from the accumulator to an output port (OUT). The instruction OUT cannot send data from any other register. The microprocessor performs subtraction by using the method of 2's complement. A microprocessor is basically a programmable logic chip. The branch instructions are the most powerful instructions because they allow the microprocessor to change the sequence of a program, either unconditionally or under certain test conditions.

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The unconditional Jump is, generally, used to set up continuous loops.The conditional Jumps are used for the decision-making process based on the data conditions in the accumulator (or of the result), reflected by the flags. The programming technique used to instruct the microprocessor to repeat tasks is called looping The addressing modes of operands are encoded depends on -the range of addressing modes and the degree of independence between opcodes and modes

3.6) Terminal Exercises

1. 2. 3. 4. List the various jump instructions. What is looping? Describe the various addressing modes. Explain the encoding of instructions.

3.7) Supplementary Materials

Thomas C.Bartee, Computer Organisation and Architecture, TMH, 1991.

3.8) Assignments
Write a Detailed essay on Classification of Instructions.

3.9) Reference Books

V. Carl Hamacher, Z Vonko G.Vranesic, Safwat G.Zaky, Computer Organization, McGraw Hill International Edition, Fourth Edition, 1996.

3.10) Learning Activities

Find out how the modes of addressing differ in microprocessers and computers.

3.11) Keywords
Registers, Accumulator, Instruction formats for instruction are the four-address instruction word, the three-address instruction word, the two-address instruction word, the single address instruction word, the zero address instruction word, Looping, Indexing, Direct addressing, Extended addressing, Indirect addressing, Indexed addressing, Immediate addressing, Stack, Queue, Subroutine.

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