ECE 332 Spring 2008

Microprocessors Nios II Assembly Language Basics

ASM 1

NIOS II Processor System Architecture and Programming

Developing assembly language programs requires understanding the architecture of the system before one can start producing code. So, we will begin with a simplified view of the Nios II system. Processor Control Unit
PC = 0

Memory Address Space 0x0000 Instr 1 0x0010

Instr 2 Instr 3

Program Memory
0x00B0
Registers
r0 r4 r8 r12 r16 r20 r24 r28 r1 r5 r9 r13 r17 r21 r25 r29 r2 r6 r10 r14 r18 r22 r26 r30 r3 r7 r11 r15 r19 r23 r27 r31

0x00C0 Data 1 0x00D0

Data 2

Data 3

Data Memory

0x7FF0 0x8000

Figure 1. Simplified Nios II Microprocessor System Above is a simplified depiction of the Nios II microprocessor system. It contains a processor and attached external memory. The processor contains a control unit and general purpose registers. Within the control unit is a 32-bit value called the program counter (PC) that acts as a pointer into program memory. Memory can be viewed as an array of consecutive units that can be addressed individually or in groups. Each unit is a byte (8 bits) and has a unique address. The Nios II processor uses 32-bit addresses and therefore can address up to 232=4,294,967,296 bytes. Thus the address space is referenced at the byte level. This means that each address refers to a unique byte. The processor can only change data that resides in registers. For this reason the standard sequence of all assembly language programs is to first move data from memory to registers, perform operations on the data in registers and then move the resulting data in registers back to memory. Also using instructions that alter the sequence of operation will result in programs that cover the majority of all applications. For the purposes of this example we will consider four basic groups of instructions. These are instructions that move data from memory to registers (MR), move data from registers to memory (RM), operate on register values placing results back into a register (RR) and finally change the flow (FC) of the instruction sequence. When instructions from the first three groups (MR, RR, RM) are executed, the program counter (PC) is

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ECE 332 Spring 2008

Microprocessors Nios II Assembly Language Basics

ASM 1

incremented by 4 (next sequential instruction). The last group of instructions allows the sequence of instructions to be changed. There are several key elements needed to understand the system environment and the selection and placement of instructions and data in a program. The following sections provide an introduction to these elements, including registers and memory and how they interact, plus instructions and directives. Registers As shown in Figure 1, the Nios II processor has thirty-two 32-bit general purpose registers. Some of these registers are intended for a specific purpose as shown in Table 1, and have special names that are recognized by the Assembler. The purpose of these reserved registers will be covered in a later lab. Registers r2 through r23 are available for general use. Register r0 r1 r2 r3 . . . r23 r24 r25 r26 r27 r28 r29 r30 r31 Name zero at Function 0x00000000 Assembler Temporary

. . . et bt gp sp fp ea ba ra Exception Temporary Breakpoint Temporary Global Pointer Stack Pointer Frame Pointer Exception Return Address Breakpoint Return Address Return Address

Table 1. Special and general purpose registers in Nios II.

Program Counter Note PC=0 in the control unit shown in Figure 1. This indicates the program counter (PC) in Figure 1 is pointing to address 0 in program memory. With PC=0 the next instruction to be executed will be Instr 1. When a processor is reset the PC is set to the default value of the processor (usually zero). So this implies that the first instruction that is to be executed must be at this address. For now we will not worry about how to get the instructions loaded into memory, but will assume that they have been loaded into memory at the appropriate locations.

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ECE 332 Spring 2008 Instructions

Microprocessors Nios II Assembly Language Basics

ASM 1

All Nios II instructions are 32-bits long. In addition to machine instructions that are executed directly by the processor, the Nios II instruction set includes a number of pseudoinstructions that can be used in assembly language programs. The Assembler replaces each pseudoinstruction by one or more machine instructions. There are three possible instruction formats, as depicted in Figure 2: I-type, R-type and J-type. In all cases the six bits b50 denote the OP code. The remaining bits are used to specify registers, immediate operands, or extended OP codes. I-type Five-bit fields A and B are used to specify general purpose registers. A 16-bit field IMMED16 provides immediate data which can be sign extended to provide a 32-bit operand. R-type Five-bit fields A, B and C are used to specify general purpose registers. An 11-bit field OPX is used to extend the OP code. J-type A 26-bit field IMMED26 contains an unsigned immediate value. This format is used only in the Call instruction.
27 26 22 21 6 5 0

31

IMMED16 (a) I-type

OP

31

27 26

22 21

17 16

6 5

C (b) R-type

OPX

OP

31

6 5

IMMED26 (c) J-type Figure 2. Instruction formats

OP

Consult the Nios II Processor Reference Handbook section 3-14 Instruction Set categories and chapter 8 Instruction Set Reference for further information on the NIOS II instruction set. These reference sections are the most important references for the assembly programming portion of this course, and will be used in all the assembly programming labs. Be sure to review the following instructions: add ldw stwio addi stw ldwio movi br beg movia

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ECE 332 Spring 2008 Data Memory

Microprocessors Nios II Assembly Language Basics

ASM 1

Memory Address Space 0x0000 Instr 1 0x0010

Instr 2 Instr 3

Program Memory
0x00B0 0x00C0 Data 1 0x00D0
Data 2 Data 3

Data Memory

0x7FF0 0x8000

Figure 3. Memory Organization Figure 2 shows a typical memory arrangement where each row contains 16 bytes or 4 words of data. As previously noted, the address space is referenced at the byte level. Objects other than bytes may be accessed, but the address must still be a byte address. To access a word (32 bits), the byte address must be on a word boundary (divisible by 4), and to access a half word (16 bits), the address must be on a halfword boundary (divisible by 2). One feature of RISC processors is that the instruction lengths are constant and are usually 32 bits or 1 word in length. Additionally all assembler instructions must start on a word boundary (divisible by 4) and the PC value will also be a multiple of 4. In Figure 3, instruction 1 is at address 0, instruction 2 is at address 4 and so on. Instructions can read and write words, half words, or bytes (8 bits) of data. Reading or writing to an address that does not correspond to an existing memory or I/O location produces an undefined result. Since the assembler will generally locate the data for a program immediately after the last program instruction, the first data element will start on a word boundary. Just as the PC register serves as a pointer into program memory any of the general purpose registers can serve as pointers into data memory. So, in this way the registers can contain data or pointers (addresses) to data. It is the responsibility of the programmer to make sure that the register contains the appropriate data for the application. The instructions that make up the NIOS II processor can be categorized by type of addressing they utilize. There are five addressing modes provided:

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ECE 332 Spring 2008

Microprocessors Nios II Assembly Language Basics

ASM 1

Immediate mode a 16-bit operand is explicitly given in the instruction. This value may be sign extended to produce a 32-bit operand in instructions that perform arithmetic operations. (RR group) example: addi r2, r4, 16 The immediate value 16 is stored as a part of the addi machine instruction. When executed the 16 bit value is sign extended and added to the value contained in register 4 and the result is place in register 2. Register mode the operand is in a processor register (RR group) example: add r2, r4, r5 The contents of registers 4 and 5 are added an the contents for register 2 is replaced with the result. Displacement mode the effective address of the operand is the sum of the contents of a register and a signed 16-bit displacement value given in the instruction. (MR and RM groups) example: ldbu r2, 64(r4) The address of the byte to be loaded into register 2 is produced by sign extending the offset of 64 (16 bit immediate) and adding to the contents of register 4. The content of register 4 remains unchanged. Register indirect mode the effective address of the operand is the contents of a register specified in the instruction. This is equivalent to the displacement mode where the displacement value is equal to 0. (MR and RM groups) example: ldw r2, 0(r4) Register 4 contains the address of the word to be loaded into register 2. Absolute mode a 16-bit absolute address of an operand can be specified by using the displacement mode with register r0 (which always contains the value 0). (MR and RM groups) example: ldw r2, 0x20(r0) The word located at memory location 0x20 (32 decimal) is loaded into register 2. Memory locations beyond 0x7fff cannot be accessed via this mode.

Now lets look at the instructions in a little more detail. The MR, RR and RM instructions all increment the PC by 4 when executed.

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ECE 332 Spring 2008

Microprocessors Nios II Assembly Language Basics

ASM 1

Examples of RR instructions are add, sub, and, or, add, addi, sub, subi, mul, muli, div and, andhi, andi, or, ori, xor, xori, nor mov, movhi, movi, movia rol, roli, ror, sll, slli, srl, srli nop cmpxxx (as needed) To start with lets look at a few RR instructions.
Instruction: Operation: Syntax: add rC rA + rB Example: where and results

add r2, r4, r5

r4 = 0x00013440 (78912) r5 = 0x00018e92 (102034) r2 = 0x0002c2d2 (180946)

add rC, rA, rB

Instruction: Operation: Syntax:

and rC rA & rB

Example: where and results

and r2, r4, r5

r4 = 0x12345678 r5 = 0x0000f000 r2 = 0x00005000

and rC, rA, rB

Instruction: Operation: Syntax:

srli rC (unsigned) rA >> ((unsigned) IMM5)

Example: where results

srli r2, r4, 12

r4 = 0x12345678 r2 = 0x00012345

srli rC, rA, IMM5

Assembler Directives Assembler instructions that are processed at assembler time instead of at run time are called assembler directives. They assist the assembler in creating the binary file that is to be run on the target system. The Nios II Assembler conforms to the widely used GNU Assembler, which is software available in the public domain. Thus, the GNU Assembler directives can be used in Nios II programs. Following are a links that provides information on the GNU Assembler directives:
http://www.gnu.org/software/binutils/manual/gas-2.9.1/html_chapter/as_7.html

and / or
http://www.gnu.org/software/binutils/manual/gas-2.9.1/html_chapter/as_toc.html

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ECE 332 Spring 2008

Microprocessors Nios II Assembly Language Basics

ASM 1

All Assembler directives begin with a period. Refer to the GNU manual above to learn about directives, including the common directives listed below: .text this directive tells the assembler to place the following statements at the end of the code section. Marks the end of current assembly program. this directive tells the assembler to place the following statements at the end of the data section. this directive makes the symbol visible to the program loading instructions into memory. this directive set the value of a symbol. this directive is used to set the content of memory locations to the specified value.

.end .data

.global

.equ .word

Additional concepts such as symbols and labels should be understood. The Special Dot Symbol. The special dot symbol contains the address the assembler is currently assembling into. Following are some examples of its usage. Also referred to as current location counter. start: .word . .work .-start

# the current assemble address is stored in memory location # difference between address of start and current location counter

name: .ascii this is a string name_length: .word .-name

Following pages will show a couple of examples for instruction decoding and encoding.

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ECE 332 Microprocessors

Nios II Assembly Language Instruction Decoding

Spring 2008

Q. Assume that the following word is a Nios II machine instruction. Decode the instruction and show its assembly language equivalent. 0x1905883a Hexadecimal representation

A. To begin, re-write the instruction in its binary form. 1 9 0 5 8 8 3 A 0001 1001 0000 0101 1000 1000 0011 1010 hex value binary equivalent

Then re-group rightmost 6 bits to identify the opcode. 0001 1001 0000 0101 1000 1000 00 111010 0x3A regroup for opcode hex opcode

So, the opcode is a hex 0x3A. Now utilizing the opcode table from Instruction Set Reference manual we can find the instructions mnemonic.

This tells us that the instruction is an R-type instruction and requires further work to identify the instructions identity. R-type instructions have the following format with the OPX field to identify the operation. R-type

Further re-grouping to isolate the OPX bits shows that a hex 0x31 occupies these bits.

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ECE 332 Microprocessors

Nios II Assembly Language Instruction Decoding

Spring 2008

A B C OPX OP 00011 00100 00010 110001 00000 111010 0x3 0x4 0x2 0x31 0x3A

Utilizing the OPX Encodings table from the Instruction Set Reference manual reveals that the instruction is the add instruction.

add instruction format from Instruction Set Reference.

Instruction interpretation. A B C OPX OP 00011 00100 00010 110001 00000 111010 0x3 r3 0x4 r4 0x2 r2 0x31 add 0x3A R-type

Finally, with information from the Instruction Set Reference for the add instruction, we can show the assembly language representation of the machine instruction is

add r2, r3, r4

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ECE 332 Microprocessors

Nios II Assembly Language Instruction Encoding

Spring 2008

Q. Encode the following assembly language instruction to its equivalent machine value addi r17, r18, 28

A. Utilizing material from Instruction Set Reference for addi instruction, the following steps can be used to accomplish this task.

addi r17,r18,28 1. 2. 3. 1 r18 0x12 2 1 r17 0x11 1 0 0 1 28 0x1c c 0 addi 0x04 4

4. 1 0010

1 0001

0000 0000 0001 1100

00 0100

5. 1001 0100 0100 0000 0000 0111 0000 0100 6. 9 4 4 0 0 7 0 4

7. 0x94400704 is the machine code for addi r17,r18,28 Explanation of steps above: Step (1.) Using the addi instruction format diagram and the assembler syntax definition, arrange the instruction in the diagram order. (2.) Encode the instruction fields in hexadecimal format. (3.) Space the hexadecimal digits to allow expansion to binary format. (4.) Encode values into binary format. (5.) Re-group instruction fields into groups of four bits each. (6.) Translate each group of four bits into equivalent hexadecimal representation. (7.) Resulting values represent machine instruction. Page 10 of 10