Bulacan State University Sarmiento Campus San Jose del Monte, Bulacan

A Hand-out Research in Logic Design 133

Submitted by:

Arellano. Annielyn Cabacoy, May Ann Cobarrubias, Larrs Francisco, Ivan Kris Rellora, Rose Zarina
BSIT 1A2
Submitted to:

Engr. Mary Grace Hermogenes

Flip Flops

In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems. Flip-flops and latches are used as data storage elements. Such data storage can be used for storage of state, and such a circuit is described as sequential. When used in a finitestate machine, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal. Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edgetriggered); the simple ones are commonly called latches.[1] The word latch is mainly used for storage elements, while clocked devices are described as flip-flops.[2]

Implementation

A traditional latch circuit based on bipolar junction transistors Flip-flops can be either simple (transparent or asynchronous) or clocked (synchronous); the transparent ones are commonly called latches.[1] The word latch is mainly used for storage elements, while clocked devices are described as flip-flops. Simple flip-flops can be built around a pair of cross-coupled inverting elements: vacuum tubes, bipolar transistors, transistors, inverters, and inverting logic gates have all been used in practical circuits. Clocked devices are specially designed for synchronous systems; such devices ignore their inputs except at the transition of a dedicated clock

signal (known as clocking, pulsing, or strobing). Clocking causes the flip-flop to either change or retain its output signal based upon the values of the input signals at the transition. Some flip-flops change output on the rising edge of the clock, others on the falling edge. Since the elementary amplifying stages are inverting, two stages can be connected in succession (as a cascade) to form the needed non-inverting amplifier. In this configuration, each amplifier may be considered as an active inverting feedback network for the other inverting amplifier. Thus the two stages are connected in a noninverting loop although the circuit diagram is usually drawn as a symmetric crosscoupled pair (both the drawings are initially introduced in the EcclesJordan patent).

Flip-flop types
Flip-flops can be divided into common types: the SR ("set-reset"), D ("data" or "delay"[16]), T ("toggle"), and JK types are the common ones. The behavior of a particular type can be described by what is termed the characteristic equation, which derives the "next" (i.e., after the next clock pulse) output, , in terms of the input signal(s) and/or the current output, . Simple set-reset latches SR NOR latch

An SR latch, constructed from a pair of cross-coupled NOR gates (an animated picture). Red and black mean logical '1' and '0', respectively. When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of crosscoupled NOR logic gates. The stored bit is present on the output marked Q. While the S and R inputs are both low, feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R (Reset) is held low, then the Q output is forced high, and stays high when S returns to low; similarly, if R is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns to

SR latch operation[17]

Characteristic table

Excitation table

S R Qnext

Action

Qnext

S R

0 0

hold state

0 x

0 1

reset

1 0

1 0

set

0 1

1 1

not allowed

X 0

The R = S = 1 combination is called a restricted combination or a forbidden state because, as both NOR gates then output zeros, it breaks the logical equation Q = not Q. The combination is also inappropriate in circuits where both inputs may go low simultaneously (i.e. a transition from restricted to keep). The output would lock at either 1 or 0 depending on the propagation time relations between the gates (a race condition). In certain implementations, it could also lead to longer ringings (damped oscillations) before the output settles, and thereby result in undetermined values (errors) in high-frequency digital circuits. Although this condition is usually avoided, it can be useful in some applications. To overcome the restricted combination, one can add gates to the inputs that would convert (S,R) = (1,1) to one of the non-restricted combinations. That can be:

Q = 1 (1,0) referred to as an S-latch Q = 0 (0,1) referred to as an R-latch Keep state (0,0) referred to as an E-latch

Alternatively, the restricted combination can be made to toggle the output. The result is the JK latch. Characteristic: Q+ = R'Q + R'S or Q+ = R'Q + S.

SR NAND latch

An SR latch
This is an alternate model of the simple SR latch built with NAND (not AND) logic gates. Set and reset now become active low signals, denoted S and Rrespectively. Otherwise, operation is identical to that of the SR latch. Historically, SR-latches have been predominant despite the notational inconvenience of active-low inputs

SR latch operation

Action

Restricted combination

Q=1 Symbol for

Q=0

an SRNAND latch

No Change

R-S Flip Flop Circuit

- Two logic or digital circuits for an RS flip flop, one using NAND gates and the other R-S flip flop using NOR gates

R-S flip flops find uses in many applications in logic or digital electronic circuitry. They provide a simple switching function whereby a pulse on one input line of the flip flop sets the circuit in one state. Further pulses on this line have no effect until the R-S flip flop is reset. This is accomplished by a pulse on the other input line. In this way the R S flip flop is toggled between two states by pulses on different lines. Although chips are available with R-S functions in them, it is often easier to create an R-S flip flop from spare gates that may already be available on the board, or on a breadboard circuit using a chip that may be to hand. To make an R S flip flop, it simple requires either two NAND gates or two NOR gates. Using two NAND gates and active low R S flip flop is produced. In other words low going pulses active the flip flop. As it can be seen from the circuit below, the two incoming lines are applied, one to each gate. The other inputs to each of the NAND gates are taken from the output of the other NAND gate. It can be seen from the waveform diagram that a low going pulse on input A of the flip flop forces the outputs to change, C, going high and D going low. A low going pulse on input B then changes the state, with C going low and D going high.

An R S flip flop using two NAND gates

The circuit for the NOR version of the circuit is exceedingly similar and performs the same basic function. However using the NOR logic gate version of the R S flip flop, the circuit is an active high variant. In other words the input signals need to go high to produce a change on the output. This may determine the choice of integrated circuit that is used. Although the NAND gate version is probably more widely used, there are many instances where the NOR gate circuit is of value.

An R S flip flop using two NOR gates These circuits are widely used in many electronic logic circuit applications. There are also contained within many integrated circuits where they are a basic building block. As such the R S flip flop is an exceedingly popular circuit. One useful application for a simple R S flip flop is as a switch de-bounce circuit. When any mechanical switch makes or breaks contact, the connection will make and break several times before the full connection is made or broken. While for many applications this may not be a problem, it is when the switch interfaces to logic circuitry. Here a series of pulses will pass into the circuit, each one being captured and forming a pulse. Dependent upon the circuit this may appear as a series of pulses, and falsely triggering circuits ahead of time.

An R S flip flop used as a de-bounce circuit

It is possible to overcome this problem using a simple R S flip flop. By connecting the swich as shown below, the flip flop will change on the first sign of contact being made. Further pulses will not alter the output of the circuit. Only when the switch is turned over to the other position will the circuit revert to the other state. In this way a simple two gate circuit can save the problems of de-bouncing the switch in other ways.

JK latch
The JK latch is much less used than the JK flip-flop. The JK latch follows the following state table: JK latch truth table

Qnext

Comment

No change

Reset

Set

Toggle

Hence, the JK latch is an SR latch that is made to toggle its output when passed the restricted combination of 11. Unlike the JK flip-flop, the 11 input combinations for the SR latch is not useful because there is no clock that directs toggling.

Gated latches and conditional transparency

Latches are designed to be transparent. That is, input signal changes cause immediate changes in output; when several transparent latches follow each other, using the same clock signal, signals can propagate through all of them at once. Alternatively, additional logic can be added to a simple transparent latch to make it nontransparent or opaque when another input (an "enable" input) is not asserted. By following a transparent-high latch with a transparent-low (or opaque-high) latch, a masterslave flip-flop is implemented.

Gated SR latch

A gated SR latch circuit diagram constructed from NOR gates. A synchronous SR latch (sometimes clocked SR flip-flop) can be made by adding a second level of NAND gates to the inverted SR latch (or a second level of AND gates to the direct SR latch). The extra gates further invert the inputs so the simple SR latch becomes a gated SR latch (and a simple SR latch would transform into a gated SR latch with inverted enable). With E high (enable true), the signals can pass through the input gates to the encapsulated latch; all signal combinations except for (0,0) = hold then immediately reproduce on the (Q,Q) output, i.e. the latch is transparent. With E low (enable false) the latch is closed (opaque) and remains in the state it was left the last time E was high. The enable input is sometimes a clock signal, but more often a read or write strobe.

Gated SR latch operation

E/C

Action

No action (keep state) Symbol for a gated SR latch

The same as non-clocked SR latch

Gated D latch

A D-type transparent latch based on an SR NAND latch

A gated D latch based on an SR NOR latch

This latch exploits the fact that, in the two active input combinations (01 and 10) of a gated SR latch, R is the complement of S. The input NAND stage converts the two D input states (0 and 1) to these two input combinations for the next SR latch by inverting the data input signal. The low state of the enable signal produces the inactive "11" combination. Thus a gated D-latch may be considered as a one-input synchronous SR latch. This configuration prevents application of the restricted input combination. It is also known as transparent latch, data latch, or simply gated latch. It has a data input and an enable signal (sometimes named clock, or control). The word transparent comes from the fact that, when the enable input is on, the signal propagates directly through the circuit, from the input D to the output Q. Transparent latches are typically used as I/O ports or in asynchronous systems, or in synchronous two-phase systems (synchronous systems that use a two-phase clock), where two latches operating on different clock phases prevent data transparency as in a masterslave flip-flop. Latches are available as integrated circuits, usually with multiple latches per chip. For example, 74HC75 is a quadruple transparent latch in the 7400 series.

Gated D latch truth table

E/C

Comment

Qprev

Qprev

No change

Reset Symbol for a gated D latch

Set

The truth table shows that when the enable/clock input is 0, the D input has no effect on the output. When E/C is high, the output equals D.

Earle latch

Earle latch uses complementary enable inputs: enable active low (E_L) and enable active high (E_H) The classic gated latch designs have some undesirable characteristics.[20] They require double-rail logic or an inverter. The input-to-output propagation may take up to three gate delays. The input-to-output propagation is not constant some outputs take two gate delays while others take three. Designers looked for alternatives.[21] A successful alternative is the Earle latch.[22] It requires only a single data input, and its output takes a constant two gate delays. In addition, the two gate levels of the Earle latch can be merged with the last two gate levels of the circuits driving the latch.[clarification needed] Merging the latch function can implement the latch with no additional gate delays.[20] The Earle latch is hazard free.[23] If the middle NAND gate is omitted, then one gets the polarity hold latch, which is commonly used because it demands less logic.[23][24] However, it is susceptible to logic hazard. Intentionally skewing the clock signal can avoid the hazard.[24]

D flip-flop

D flip-flop symbol The D ip-op is widely used. It is also known as a data or delay flip-flop.[citation needed] The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as the rising edge of the clock). That captured value becomes the Q output. At other times, the output Q does not change.[25][26] The D flip-flop can be viewed as a memory cell, a zero-order hold, or a delay line.[citation needed]

Truth table:

Clock

Qnext

Rising edge

Rising edge

Non-Rising

('X' denotes a Don't care condition, meaning the signal is irrelevant) Most D-type flip-flops in ICs have the capability to be forced to the set or reset state (which ignores the D and clock inputs), much like an SR flip-flop. Usually, the illegal S = R = 1 condition is resolved in D-type flip-flops. By setting S = R = 0, the flip-flop can be used as described above.

Inputs

Outputs

>

Q'

4-bit serial-in, parallel-out (SIPO) shift register These flip-flops are very useful, as they form the basis for shift registers, which are an essential part of many electronic devices. The advantage of the D flipflop over the D-type "transparent latch" is that the signal on the D input pin is captured the moment the flip-flop is clocked, and subsequent changes on the D input will be ignored until the next clock event. An exception is that some flipflops have a "reset" signal input, which will reset Q (to zero), and may be either asynchronous or synchronous with the clock. The above circuit shifts the contents of the register to the right, one bit position on each active transition of the clock. The input X is shifted into the leftmost bit position.

Classical positive-edge-triggered D flip-flop

A positive-edge-triggered D flip-flop This clever circuit[27] consists of two stages implemented by SR NAND latches. The input stage (the two latches on the left) processes the clock and data signals to ensure correct input signals for the output stage (the single latch on the right). If the clock is low, both the output signals of the input stage are high regardless of the data input; the output latch is unaffected and it stores the previous state. When the clock signal changes from low to high, only one of the output voltages (depending on the data signal) goes low and sets/resets the output latch: if D = 0, the lower output becomes low; if D = 1, the upper output becomes low. If the clock signal continues staying high, the outputs keep their states regardless of the data input and force the output latch to stay in the corresponding state as the input logical zero remains active while the clock is high. Hence the role of the output latch is to store the data only while the clock is low. The circuit is closely related to the gated D latch as both the circuits convert the two D input states (0 and 1) to two input combinations (01 and 10) for the output SR latch by inverting the data input signal (both the circuits split the single D signal in two complementary S and R signals). The difference is that in the gated D latch simple NAND logical gates are used while in the positive-edgetriggered D flip-flop SR NAND latches are used for this purpose. The role of these latches is to "lock" the active output producing low voltage (a logical

zero); thus the positive-edge-triggered D flip-flop can be thought of as a gated D latch with latched input gates

Masterslave edge-triggered D flip-flop

A masterslave D flip-flop is created by connecting two gated D latches in series, and inverting the enable input to one of them. It is called masterslave because the second latch in the series only changes in response to a change in the first (master) latch.

A masterslave D flip-flop. It responds on the negative edge of the enable input (usually a clock)

An implementation of a masterslave D flip-flop that is triggered on the positive edge of the clock For a positive-edge triggered masterslave D flip-flop, when the clock signal is low (logical 0) the "enable" seen by the first or "master" D latch (the inverted clock signal) is high (logical 1). This allows the "master" latch to store the input value when the clock signal transitions from low to high. As the clock signal goes high (0 to 1) the inverted "enable" of the first latch goes low (1 to 0) and the value seen at the input to the master latch is "locked". Nearly simultaneously, the twice inverted "enable" of the second or "slave" D latch transitions from low to high (0 to 1) with the clock signal. This allows the signal captured at the rising edge of the clock by the now "locked" master latch to

pass through the "slave" latch. When the clock signal returns to low (1 to 0), the output of the "slave" latch is "locked", and the value seen at the last rising edge of the clock is held while the "master" latch begins to accept new values in preparation for the next rising clock edge. By removing the leftmost inverter in the circuit at side, a D-type flip-flop that strobes on the falling edge of a clock signal can be obtained. This has a truth table like this: D Q > Qnext

Falling

Falling

A CMOS IC implementation of a "true single-phase edge-triggered flipflop with reset"

Edge-triggered dynamic D storage element

An efficient functional alternative to a D flip-flop can be made with dynamic circuits as long as it is clocked often enough; while not a true flipflop, it is still called a flip-flop for its functional role. While the masterslave D element is triggered on the edge of a clock, its components are each triggered by clock levels. The "edge-triggered D flip-flop", as it is called even though it is not a true flip-flop, does not have the masterslave properties. Edge-triggered D flip-flops are often implemented in integrated high-speed operations using dynamic logic. This means that the digital output is stored on parasitic device capacitance while the device is not transitioning. This design of dynamic flip flops also enables simple resetting since the reset operation can be performed by simply discharging one or more internal nodes. A common dynamic flip-flop variety is the true single-phase clock (TSPC) type which performs the flip-flop operation with little power and at high speeds. However, dynamic flip-flops will typically not work at static or low clock speeds: given enough time, leakage paths may discharge the parasitic capacitance enough to cause the flip-flop to enter invalid states.

T flip-flop

A circuit symbol for a T-type flip-flop

If the T input is high, the T flip-flop changes state ("toggles") whenever the clock input is strobed. If the T input is low, the flip-flop holds the previous value. This behavior is described by the characteristic equation:

(expanding the XOR operator) and can be described in a truth table

T flip-flop operation[28]

Characteristic table

Excitation table

Comment

Comment

hold state (no clk) 0

No change

hold state (no clk) 1

No change

toggle

Complement

toggle

Complement

When T is held high, the toggle flip-flop divides the clock frequency by two; that is, if clock frequency is 4 MHz, the output frequency obtained from the flip-flop will be 2 MHz. This "divide by" feature has application in various types of digital counters. A T flip-flop can also be built using a JK flip-flop (J & K pins are connected together and act as T) or D flip-flop (T input and Qprevious is connected to the D input through an XOR gate). A T flip-flop can also be built using an edge-triggered D flip-flop with its D input fed from its own inverted output.

JK flip-flop

A circuit symbol for a positive-edge-triggered JK flip-flop

JK flip-flop timing diagram The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the S = R = 1 condition as a "flip" or toggle command. Specifically, the combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J = K = 1 is a command to toggle the flipflop, i.e., change its output to the logical complement of its current value. Setting J = K = 0 does NOT result in a D flip-flop, but rather, will hold the current state. To synthesize a D flip-flop, simply set K equal to the complement of J. Similarly, to synthesize a T flip-flop, set K equal to J. The JK flip-flop is therefore a universal flip-flop, because it can be configured to work as an SR flip-flop, a D flip-flop, or a T flip-flop. The characteristic equation of the JK flip-flop is:

and the corresponding truth table is:

JK flip-flop operation[28]

Characteristic table

Excitation table

J K Qnext

Comment

Q Qnext

J K Comment

0 0 Q

hold state

0 X No change

0 1 0

reset

1 X Set

1 0 1

set

X 1 Reset

1 1 Q Metastability

toggle

X 0 No change

Flip-flops are subject to a problem called metastability, which can happen when two inputs, such as data and clock or clock and reset, are changing at about the same time. When the order is not clear, within appropriate timing constraints, the result is that the output may behave unpredictably, taking many times longer than normal to settle to one state or the other, or even oscillating several times before settling. Theoretically, the time to settle down is not bounded. In a computer system, this metastability can cause corruption of data or a program crash, if the state is not stable before another circuit uses its value; in particular, if two different logical paths use the output of a flip-flop, one path can interpret it as a 0 and the other as a 1 when it has not resolved to stable state, putting the machine into an inconsistent state.[29]

Timing considerations Setup, hold, recovery, removal times

Flip-flop setup, hold and clock-to-output timing parameters Setup time is the minimum amount of time the data signal should be held steady before the clock event so that the data are reliably sampled by the clock. This applies to synchronous input signals to the flip-flop. Hold time is the minimum amount of time the data signal should be held steady after the clock event so that the data are reliably sampled. This applies to synchronous input signals to the flip-flop. Synchronous signals (like Data) should be held steady from the set-up time to the hold time, where both times are relative to the clock signal. Recovery time is like setup time for asynchronous ports (set, reset). It is the time available between the asynchronous signals going inactive and the active clock edge. Removal time is like hold time for asynchronous ports (set, reset). It is the time between active clock edge and asynchronous signal going inactive.[30] Short impulses applied to asynchronous inputs (set, reset) should not be applied completely within the recovery-removal period, or else it becomes entirely indeterminable whether the flip-flop will transition to the appropriate state. In another case, where an asynchronous signal

simply makes one transition that happens to fall between the recovery/removal time, eventually the asynchronous signal will be applied, but in that case it is also possible that a very short glitch may appear on the output, dependent on the synchronous input signal. This second situation may or may not have significance to a circuit design. Set and Reset (and other) signals may be either synchronous or asynchronous and therefore may be characterized with either Setup/Hold or Recovery/Removal times, and synchronicity is very dependent on the TTL design of the flip-flop. Differentiation between Setup/Hold and Recovery/Removal times is often necessary when verifying the timing of larger circuits because asynchronous signals may be found to be less critical than synchronous signals. The differentiation offers circuit designers the ability to define the verification conditions for these types of signals independently. The metastability in flip-flops can be avoided by ensuring that the data and control inputs are held valid and constant for specified periods before and after the clock pulse, called the setup time(tsu) and the hold time (th) respectively. These times are specified in the data sheet for the device, and are typically between a few nanoseconds and a few hundred picoseconds for modern devices. Unfortunately, it is not always possible to meet the setup and hold criteria, because the flip-flop may be connected to a real-time signal that could change at any time, outside the control of the designer. In this case, the best the designer can do is to reduce the probability of error to a certain level, depending on the required reliability of the circuit. One technique for suppressing metastability is to connect two or more flip-flops in a chain, so that the output of each one feeds the data input of the next, and all devices share a common clock. With this method, the probability of a metastable event can be reduced to a negligible value, but never to zero. The probability of metastability gets closer and closer to zero as the number of flip-flops connected in series is increased. So-called metastable-hardened flip-flops are available, which work by reducing the setup and hold times as much as possible, but even these cannot eliminate the problem entirely. This is because metastability is more than simply a matter of circuit design. When the transitions in the clock and the data are close together in time, the flip-flop is forced

to decide which event happened first. However fast we make the device, there is always the possibility that the input events will be so close together that it cannot detect which one happened first. It is therefore logically impossible to build a perfectly metastable-proof flipflop.

Propagation delay
Another important timing value for a flip-flop is the clock-to-output delay (common symbol in data sheets: tCO) or propagation delay (tP), which is the time the flip-flop takes to change its output after the clock edge. The time for a high-to-low transition (tPHL) is sometimes different from the time for a low-to-high transition (tPLH). When cascading flip-flops which share the same clock (as in a shift register), it is important to ensure that the tCO of a preceding flip-flop is longer than the hold time (th) of the following flip-flop, so data present at the input of the succeeding flip-flop is properly "shifted in" following the active edge of the clock. This relationship between tCO and th is normally guaranteed if the flip-flops are physically identical. Furthermore, for correct operation, it is easy to verify that the clock period has to be greater than the sum tsu + th. It is important to observe that in this circuit it is impossible to have the troublesome situation where S = R = 1. In the gated D latch, the output Q merely tracks the value of the input D while Clk = 1. As soon as Clk goes to 0, the state of the latch is frozen until the next time the clock signal goes to 1. Therefore, the gated D latch stores the value of the D input seen at the time the clock changes from 1 to 0. Figure 7.8 also gives the truth table, the graphical symbol, and the timing diagram for the gated D latch. The timing diagram illustrates what happens if the D signal changes while Clk = 1. During the third clock pulse, starting at t3, the output Q changes to 1 because D = 1. But midway through the pulse D goes to 0, which causes Q to go to 0. This value of Q is stored

when Clk changes to 0. Now no further change in the state of the latch occurs until the next clock pulse, at t4. The key point to observe is that as long as the clock has the value 1, the Q output follows the D input. But when the clock has the value 0, the Q output cannot change. In Chapter 3 we saw that the logic values are implemented as low and high voltage levels. Since the output of the gated D latch is controlled by the level of the clock input, the latch is said to be level sensitive. The circuits in Figures 7.6 through 7.8 are level sensitive. We will show in section 7.4 that it is possible to design storage elements for which the output changes only at the point in time when the clock changes from one value to the other. Such circuits are said to be edge triggered. At this point we should reconsider the circuit in Figure 7.3. Careful examination of that circuit shows that it behaves in exactly the same way as the circuit in Figure 7.8a. The Data and Load inputs correspond to the D and Clk inputs, respectively. The Output, which has the same signal value as point A, corresponds to the Q output. Point B corresponds to Q. Therefore, the circuit in Figure 7.3 is also a gated D latch. An advantage of this circuit is that it can be implemented using fewer transistors than the circuit in Figure 7.8a.

Registers and Counters

Registers
Each flip-flop is a binary cell capable of storing one bit of information. A Register is simply a group of flip-flops. An n-bit register has a group of n flip-flops. The basic function of a register is to hold information within a digital system so as to make it available to the logic elements during the computing process. Since a register consists a finite number of flip-flops and as each of those flip-flops is capable to store a single 0 or 1, there are a finite number of 0-1 combinations that can be stored into a register. Each of those combinations is known as state or content of that register. With flip-flops we can store data bitwise but usually data does not appear as single bits. Instead it is common to store data words of n bit with typical word lengths of 4, 8, 16, 32 or 64 bit. Thus, several flip-flops are combined to form a register to store whole data words. Registers are synchronous circuits thus all flip-flops are controlled by a common clock line. As registers are often use to collect serial data they are also called accumulators. There exist several types of registers as there are

Shift Registers
Information often comes bitwise i.e. one bit every clock pulse. To store such data shift registers are used. A shift register has one input. Every clock pulse one bit is loaded into the first flip-flop of the register while all the actual flip-flop contents are shifted and the oldest bit got dropped. If the outputs of all flip-flops (and therefore the registers complete content) are read from the lines Q1 to Qn the register is used as Serial In Parallel out (SIPO). A typical purpose for such a SIPO register is to collect data that is delivered bitwise and that is needed in n-bit data words (e.g. to convert the signals from serial ports of a computer: the line transports 1 bit a time, the computer uses 8, 16 or 32 bit data words). Shifting bits are important for mathematical operations: if the output of the whole register is interpreted as a dual number, shifting by one bit corresponds to multiplying or dividing by 2 (depends on which flip-flop is interpreted as MSB).

Cyclic Registers
Sometimes it is necessary to recycle the same values again and again. Thus the bit that usually would get dropped is fed to the register input again to receive a cyclic serial register

Parallel In-Serial Out

As there is a need for serial parallel conversion the inverse operation is equally required. It is done by a Parallel In Serial Out register (PISO) that allows loading data as whole data words and serial shifting. For this operation it needs two control lines: one to trigger the shifting and one to control when a new data word is loaded to the register . it is prepared by clearing allthe status of the flipflops output by using a clear function i.e. each flipflop is equals to 0 then shifting it by taking a single bit of the given input that input is shifts the present bits in the flipflop to the next flipflop.

Barrel Shifters
A barrel shifter is a digital circuit that can shift a data word by a specified number of bits in one clock cycle. It can be implemented as a sequence of multiplexers (mux.), and in such an implementation the output of one mux is connected to the input of the next mux in a way that depends on the shift distance. For example, take a 4-bit barrel shifter, with inputs A, B, C and D. The shifter can cycle the order of the bits ABCD as DABC, CDAB, or BCDA; in this case, no bits are lost. That is, it can shift all of the outputs up to three positions to the right (and thus make any cyclic combination of A, B, C and D). The barrel shifter has a variety of applications, including being a useful component in microprocessors (alongside the ALU). A common usage of a barrel shifter is in the hardware implementation of floating-point arithmetic. For a floating-point add or subtract operation, the significand of the two numbers must be aligned, which requires shifting the smaller number to the right, increasing its exponent, until it matches the exponent of the larger number. This is done by subtracting the exponents, and using the barrel shifter to shift the smaller number to the right by the difference, in one cycle. If a simple shifter were used, shifting by n bit positions would require n clock cycles

Cascade Shifters Counters

A counter is a sequential circuit that counts. That means it proceeds through a predefined sequence of states where the state of the circuit is determined by the states of all its flip flops. As every state of the circuit can be given a number we can say that a

counter produces a sequence of numbers. A commonly used approach is to interpret a circuits state as dual number, so if flip-flop A,B and C are all 0 the counters state is 0. if A is 1, B is 0 and C is 1 the counters state is 101 = 5 and so on. The most basic counters will simply increment by 1 with every clock pulse, so after state 100 it will go to 101; the next pulse will let it switch to 110 etc. It is possible to design counters with any needed counting sequence. Even though asynchronous sequential circuits are not subject of this course the asynchronous counter is presented here exceptionally to give a slight impression on how

Basically counters are of two types: 1. Asynchronous or ripple counter 2. synchronous counter

Asynchronous counter
For these counters a external clock signal is applied to one flip flop and then the output of preceding flip flop is connected to the clock of next flip flop.

Logic Gate Families

Real-Circuit Requirements on Logic Gates

You will be familiar with the principles of Boolean logic from your architecture class (es). However when we come to consider real logic circuits, we have to worry about nifty gritty details of current and voltage which were treated abstractly in your earlier work. Logic circuitry is constructed from active elements, for example and gates, connected together with conductors. With conventional binary logic, each conductor at a given time is conceptually in one of two given states, a high state or a low state. The terms "high" and "low", referring to a potential difference with ground, are used in preference to "true" and "false" because, while normally a high state corresponds to true and a low state corresponds to false, it is sometimes convenient to think in terms of "inverted logic" in which a high signal represents a false state and a low signal represents a true state. In tables which specify the behavior of a given logic circuit, high and low states are denoted by H and L respectively. Thus, commonly, a single logic variable is specified as a potential difference between a single conductor and ground, though if a signal is to be conveyed over a "long" distance, it is a good idea to have a logic variable specified as the potential difference between two lines devoted to that variable. However it is clearly impossible for high and low states each to be represented by exactly one voltage. Indeed, it is desirable that a system built out of logic gates should be rather tolerant of imprecision in the voltage-levels that represent a given logic-value. This is not just a matter of the fact that precision costs money - even more importantly it costs time. A good way of thinking about a conductor which connects two logic-gates is to compare it to a trough of water. The output of one gate A is connected to the trough, and an input of the other (gate B) is also connected. If the water in the trough is initially at low level, and gate A wants to raise it to a high level, it will dump a lot of water in the trough. As a result, the water in the trough will be initially quite rough - the initial water dumped by A will pass along the trough as a wave, eventually arriving at B. The wave may even be reflected off the end of the trough, and travel back to A. The water will continue to be disturbed for quite a long time after the original activation of A.

A conductor into which a logic gate is "pouring" charge will behave in an analogous way (though the analogy can be taken too far - the equations governing water waves are different from those governing electro-magnetic waves). A wave of charge will propagate along the conductor, and may reflect off the end. Thus it will inevitably take a significant time for a gate to establish a given voltage at a remote point in the circuit. Thus it is desirable merely from the point of view of speed of operation for logic gates to be happy to accept a range of input voltages. The behavior of an ideal inverter (logic NOT) is shown in the diagram.

Using a 5 volt supply (which is the most common), the gate changes its output state from a High value of +5 volts to Low of 0 volts when the input voltage exceeds a threshold of 2.5 volts. Any other such gate "looking" at this output will be guaranteed to "see" a correct value after a sufficient length of time has elapsed for the waves-ofcharge propagating along the conductor connecting them to have fallen to half their original amplitude. We can set a minimum value for this time if we remember that light in a vacuum travels roughly a foot (0.3 meters) in a nanosecond. The propagation of the signal along a conductor is slower than this - between 0.3 and 0.5 times the speed-oflight. Thus, if we consider the signals in an ordinary circuit board, we may reasonably expect that one gate B whose input is "looking" at the output of another gate A somewhere on the board will have a correct input signal within a few nanoseconds of A changing its output. To this must be added the time taken for gate B to modify its output in response to the change in input signal. This time ranges from 0.3ns for the very fastest logic available to 90ns for the slowest.

The Logic Gate as Amplifier: Potential Dangers

If we look at our transfer function, we observe that the slope of the curve which plots output voltage versus input voltage is very steep at the threshold, while being flat almost everywhere else. This means that a logic gate acts as a high gain amplifier around its threshold. For the correct functioning of digital circuits, it is important to minimize the amount of time that logic gates spend in the threshold region. The most important aspect of this need is to avoid leaving any input of a logic gate unconnected. For typically such an unconnected input will bias itself to around the threshold voltage, and in effect act as a tiny but effective antenna for responding to any signals present in the environment - a perfect recipe for creating a logic system that fails spasmodically.

Logic Families

Basic logic elements have been available integrated on a single chip of semiconductor material since the 1960's. Such integrated circuits are classified into "families". From the users point of view, a family of logic IC's offers interoperability. Provided the user obeys simple rules, all the chips in a given family can communicate freely. The most important kind of rule is that limiting "fan-out". Typically, in a given logic family, a given output can only drive a limited number of inputs, called the "fan-out" of the family. For the TTL family of logic, the fan-out is ten. The reasons that there isn't just one universal family of logic chips are historical and technological. Different technologies were developed at different dates, and today different technologies offer distinct advantages. The most important qualitative technological difference between logic families is whether bipolar transistors or field-effect transistors are used. The other qualitative difference is in the semi-conductor material used. The earliest logic families mostly used bipolar transistors. Of these, by far the most successful was the TTL family, where "TTL" stands for "Transistor -Transistor Logic". This family, as popularized by Texas Instruments, is usually known as the "74" series. With a given technology, variations of performance can achieve by trading off one characteristic against another. In logic circuitry, the most important trade-off is that of speed versus power-consumption. To fill up with charge the conductor connecting two gates in a short time requires power . Let us recall that the energy required to charge a capacitor of size C farads is V2C. Now a load for a logic gate output might be 20pF (including the capacitance of the conductor and of the inputs of any gates to which it is connected). So a state-change required to charge a conductor up to 5V will cost us 25*20 = 500 picojoules. This is not a lot of energy! But consider how much power is involved if we are to accomplish the state-change in a nanosecond - power = energy/time, and 500*10-12/10-9 come out at 500mW, for a single gate. This is a lot of power if we consider that even a small logic system might contain dozens of gates. However what we have calculated is the peak power necessary to achieve a statechange in a conductor. Most logic gates spend most of their time not undergoing transitions. So, from the point of view of system power consumption, the more important consideration is quiescent power consumption. It is in this aspect that bipolar logic is at a disadvantage, since the output state of a bipolar transistor (conducting/nonconducting) depends on there being a significant input current. Thus a bipolar logic gate

will always consume power at a rate which is a significant proportion of its maximum power capability Thus bipolar logic is subject to high quiescent power consumption. Within the general TTL family, various sub-families have been established which exploit a trade-off between speed and power. Also, a significant technological advance, the use of Schottky-clamped logic which avoids driving its transistors into saturation, allowed the development of TTL logic of superior performance - either faster (the 74S... series) or the low-power 74LS series. Further improvements on these are the 74AS and 74ALS series. The other major weakness of TTL logic is not so inherent in the use of bipolar transistors, but arises more from the early development of TTL. This weakness is that the logic threshold of TTL is rather low, typically at +1.3 volts, though the specifications state that it can vary between +0.8V and +2.0 volts. Given that the output of a TTL gate is not pulled all the way to ground, it is clear that the noise margin of TTL, that is the amount of electrical noise that TTL-based circuitry can tolerate without malfunction, is rather small. Along with this goes the fact that TTL logic gates have a low, and variable, input impedance. Of course, it would have been possible to design bipolar logic gates which did not exhibit these problems but at a cost of being able to get fewer devices on a chip, and perhaps of having slower devices. Incidentally, you should note that the logic high state of a TTL gate is around 3.5V.

CMOS Logic

CMOS logic makes use of field effect transistors arranged with a complementary pair of N-channel and P-channel FET's used to drive each signal. It has major advantages over TTL, though, being more complicated to fabricate, it has come to the market later. Its advantages include:

The quiescent current can be very small, making it suitable for micro-power devices such as wrist-watches and cameras. This low quiescent current arises from the fact that FET's have a near infinite input resistance. The outputs swing rail-to-rail. Logic high is thus the supply voltage, a logic low is ground. The logic threshold can be designed to be half the supply voltage. However the HCT family of CMOS logic has a lower threshold, since it is designed to be inter-

operable with TTL. It should be noted that there is significant variation in the logic threshold of actual CMOS chips whose nominal threshold is half the supply voltage. Horowitz & Hill state that this can vary from between one-third of the supply to two-thirds. Some CMOS families can be operated over a range of supply voltages (5-15V). This may improve immunity to ambient electrical noise, and also makes it easier to use them to drive power FET transistors for making things happen in the outside world. While early CMOS gates were very slow, modern families are competitive with the fastest TTL.

The only disadvantage of CMOS devices is that they are more readily damaged by static electricity than TTL devices, so that they need to be handled with care. They are normally supplied in anti-static packages, but you should be sure that you are grounded to the circuit you are working on before you handle them. An anti-static pad is available in the lab for holding CMOS chips prior to insertion. So, if you can easily get the functions you want, CMOS logic is the recommended choice. Horowitz and Hill recommend 74HC for general purpose use, combined with 74HCT where TTL compatibility is needed. Do not use the faster 74AC and 74ACT series unless you actually need the speed. The faster chips create more noise and so require more careful circuit design. Unfortunately it is still true that the TTL families are still somewhat more readily available.

NMOS Logic

NMOS was the first technology to be developed which supported Large Scale Integration - so all the original microprocessor chips were NMOS. It is distinguished from CMOS by the fact that only N-channel MOSFETS were used, thus making for easier fabrication. Generally, NMOS circuits have been replaced by CMOS equivalents which offer superior performance. NMOS was normally designed for TTL compatibility, though with feeble output drive capabilities.

Other Logic Families

Unless you need ultra-fast logic you will have no call to use other families. The fastest logic is based on gallium arsenide as a semiconductor, and can be clocked at 2.7 gigahertz. The fastest silicon-based logic family is ECL.

Input-output characteristics in more detail

While you can, to a large extent, connect up logic gates of a given family on a single board just by following some quite simple rules, if you want to interface between different logic families, or use logic gates to drive external circuitry, or conversely use external circuitry to provide inputs to logic gates, you will need to have a deeper understanding of the behavior of logic gates as electronic circuits. Firstly, let's consider what a logic input looks like. A CMOS input is fairly straightforward. At DC the impedance is nearly infinite across the whole range from ground up to the supply voltage. Above and below that range the input is "clamped" to the supply by diodes, whose role is partly to protect the circuit against static electricity damage during manufacture. However clamping is also useful to absorb energy from signals that go momentarily outside the legal-range because of a rapid transition. Of course, a CMOS input has capacitance which means in effect that it takes a minimum signal energy of a few pico-joules to operate such a gate. This capacitance would only be of concern if you wanted to design an embedded system which involved very fast input into CMOS logic. As the figure shows, the input behavior of a TTL gate is more complicated arising essentially from the fact that a bipolar transistor requires current to operate it.

A TTL input can be held at a logic high state with a small input current (never more than 20micro amps, usually less). However to keep a TTL input at a logic low state, the circuit that is driving it has to be able to sink nearly a milliamp, while keeping the input below

0.4 volts. So, for example, trying to drive a TTL gate from an emitter follower is a bad idea - current comes out of the input of the TTL gate, and can't go back the "wrong way" through the emitter of the resistor. Generally, a TTL input should be driven from some kind of switch to ground - a transistor switch will do, or a mechanical switch.

The Transfer Function of Logic Gates

Let us now consider the transfer function - the relationship between input voltage and output voltage. We have already seen a diagram showing the ideal behavior. The actual behavior of logic families is illustrated in the figure:

The "pure" CMOS gates behave (at least nominally) very close to the ideal curve we drew earlier. However, TTL behaves in a way that is quite asymmetric. The TTL high is normally around 3.5 volts (but may be lower for within the specifications), while the TTL low is as much as 0.2 volts. Moreover, as discussed earlier, the TTL threshold is between 0.8 and 2 volts, depending on family and on individual devices.

The Output Characteristics of Logic Gates.

If we want to make a logic gate do anything other than drive another gate of the same family, we also have to understand the output characteristics of the gate. Generally, logic gates can't directly do much in the outside world. Usually you need an amplifier external to the gate to achieve a big effect. However, careful choice of how you make a logic gate drive external components, based on an understanding of the characteristics of the gate, can lead to reliable, economic circuit design. The primary characteristics of a logic gate output are what its voltage level is when no current is passing through the output, and how that voltage varies with current being drawn. These characteristics are illustrated in the figure, redrawn from Horowitz and Hill. Not surprisingly, we find that the fastest logic families have the gentlest slopes (that is, they have a low output impedance), arising from the requirement upon them to deliver a lot of current to a conductor to raise or lower it fast.

The main points to note about this figure are the very poor current output capability of old-style CMOS, and the relatively poor current output capability of the low-power Schottky family of TTL. Also note that the logic low curves for most kinds of TTL are flatter than the logic high curves, or, to put it another way, most TTL is better at sinking current than sourcing it. So, if it's otherwise convenient, it's better to put a load between a TTL output and +5V, activating the load by a logic low, than it is to have the load between the output and ground.

Open Collector Outputs

Certain logic gates are available with open-collector outputs, in which the outputs are connected directly to the collector of a transistor in the chip. To use such a chip you need to install a pull-up resistor, typically of a few kilo ohms. Originally these chips were used for driving data-busses such as you might find in the backplane of a computer, but they are now obsolete for this purpose, since they rely on a passive pull-up resistor which is necessarily slow. However they can be quite handy for interfacing between logic circuits and other circuits. They are normally marked by an asterisk in schematics.