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Cockpit Display attitude steering Flight Management System attitude position velocity INU Satellite Antenna Steering aircraft attitude
Figure 66:
Integration of INU, Satellite Antenna and Flight Management System
14.1. Synchros
Until recently much of the instrumentation in the cockpit has been of electromechanical design, with the information being presented in the form of a rotating needle and a dial. In order to transmit rotational information electrically, devices called synchros were used. These are essentially rotating transformers and motors. A Transmitter A Receiver 26VAC 400Hz B C B C
Figure 67:
Wiring Diagram of Synchro Devices
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As shown above, each synchro consists of three static windings wound at 120 intervals, and a single rotor winding. As the name suggests, the static windings are fixed to the body of the synchro while the rotor winding is attached to a shaft which is free to rotate. When an excitation voltage (in aircraft usually 400 Hz, 26 Volts) is applied to the rotors, voltages are induced in each of the stator windings. The voltages are determined by the angle of rotation of the rotor. When a synchro receiver is connected as shown, its rotor will take up the same angle of rotation as the transmitter rotor. Thus the angular information has been transmitted via an electrical connection. Information available in this form includes: i) pitch, roll and heading from INU ii) altitude from an altimeter iii) relative bearing from an ADF antenna
14.1.2 Disadvantages
i) - relatively large and bulky ii) - require separate excitation voltage iii) - since they are mechanical, they are subject to wear and breakdown iv) - in mixed analogue/digital systems, synchro to digital and digital to synchro conversion modules are required and these are usually expensive. Ironically, since synchros are present in many current aircraft systems, new, all digital equipment may still produce information in synchro format by use of a digital to synchro converter. Some other all digital piece of equipment may provide for synchro input by means of a synchro to digital converter.
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sensor A/D
Figure 68:
Typical Digital Data Transfer
This does not appear to be much of an improvement, since 16 wires are required (1 bit/wire). However, it is possible to send the same information in a serial fashion in which case only two wires are needed. Note that, in the example given, the data rate would be reduced by a factor of 16, but the data rates can be increased to compensate. Example Signal byte with binary representation 010110102 is to be transmitted serially Tclock 0 1 0 1 1 0 1 0 parallel register 1 0 1 1 0 1 0 1 0 Txclock = 8 x Tclock 0 1 0 1 serial 1 0 shift 1 register 0 01011010 Rxclock Rclock 0 1 0 1 1 0 1 0 parallel register
Stop
Note: a shift register shifts its contents one bit for each clock pulse e.g.
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REGISTER 0 1 1 0 0 1 1 0 1 1
Output
Clock pulse 2
1 0
Time domain multiplexing of individual bits allows transmission on a single line. The data rate, however, is lower
In Figure 67. all 8 bits of the byte are clocked in to the parallel register, they are then copied to the serial shift register. Then the bits clocked from the serial shift register on to the transmission line.
5V
transmitted high or 1
0V
transmitted low or 0
Figure 70:
Illustration of Logic Levels
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0.4V
0.7V
Figure 71:
TTL Noise Margin
In this case the noise margin is 0.3V which means that the transmitted signal can be distorted by 0.3V before a false value is detected
14.2.2 Synchronization
One way by which a receiver can improve the probability of choosing the right value is to average the signal over the width of a bit. To do this, however, it must know where the boundaries of the bits are. If it were to average a signal over half a zero bit and half a one bit, the result would not be correct. Thus it is advantageous for the receiver to have a copy of the clock signal from the transmitter. This can be sent on a separate set of wires but, as we shall see, data can be sent using codes which are self-clocking in which case, only one set of wires is needed.
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14.3.1 Microprocessors
The manufacturing technology allows creation of devices containing ~ 109 (Intel Tukwila 2x109 announced 2 Feb 2008 ) transistors, but MIL spec, high reliability ICs are available only after a 5 - 10 year lag. Military/ avionics technology (MIL spec), therefore is conservative compared to the current consumer market technology
address register
ELEC4504 Avionics Systems Static Memory (SRAM) uses a bistable device (flip-flop) to store binary information
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DATA IN STROBE
DATA OUT
CK Q
Figure 73:
Static RAM Element
The data out is set to whatever data in is when the strobe pulse is received The flip-flop stores the information as long as power supply voltage is provided, but it dissipates power continuously causing high power consumption for large memories. Requires at least two transistors plus resistors and capacitors. (takes up a lot of space on the chip)
Figure 74:
Memory Element for DRAM
DRAM memory requires only one transistor for 1 bit of information. High capacity (Gbit) low power consumption memory uses DRAM technology.
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synchro bearing horizontal deviation ILS Receiver horizontal ag vertical deviation vertical ag course select synchro reference HSI
Figure 75:
Wiring for analog ILS receiver/HSI
Using data bus technology, the above function can be accomplished using two pairs of twisted, shielded wires.
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Two parallel wires and their terminations form a loop A changing magnetic eld into or out of the page will induce a voltage into the loop
If the wires are twisted, the loops alternate in orientation and the induced voltage tends to average out Figure 76:
Effect of Magnetic Field on Untwisted and Twisted Wire Pairs
The twisted wires are then shielded to reduce electrical coupling from outside sources (especially adjacent wires in a cable).
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Figure 77:
Bipolar Return to Zero Code
This is called bipolar because the ones and zeroes are represented by positive and negative values and is called return to zero because the signal returns to zero value during each bit interval. One advantage of this system is that it is self-clocking. i.e. by rectifying the bitstream, a clock can be generated. Note: this method is complicated by the fact that three levels are required to be decoded.
1 +1 0 -1
Figure 78:
Biphase Level (Manchester) Code
In this case, a one is indicated by the signal being positive in the rst half of the bit period while the zero in indicated by the signal being positive in the second half of the bit period. Self clocking is provided by the fact that a transition occurs in the middle of every bit period
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Figure 79:
ARINC 429 Data Word
The label describes the type of data in the word. Each parameter has a unique label e.g. x acceleration, altitude, temperature The source/destination identifies where the information is coming from (e.g. INS) and where is going (e.g. Flight management system) Up to 20 receivers can be accommodated by one transmitter. A modern aircraft such as a Boeing 767 may have as many as 150 data links to interconnect different units.
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Figure 80:
Typical ARINC 429 Topology
One disadvantage of Single Source/Single Sink system is the complexity involved in making changes to the system. This is also shown in Figure 78. The original connections are shown in solid lines while the additional connections required to add a fifth unit are shown in dotted lines. this shows a disadvantage of the single source/ multiple sink topology.
The code used in ARINC 429 is bipolar RTZ and the wiring is twisted shielded pair The electrical specification is shown below:
As can be seen in the diagram the noise margin is 2.5 V (9 - 6.5 or -6.5 - 9)
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Remote Terminal
Remote Terminal
Remote Terminal
up to 31 RTs
Figure 81:
MIL STD 1553 Data Bus Topology
Note that adding a unit to the bus is far less complicated than in the case of the ARINC 429 system The bus controller initiates all information transfers The bus monitor provides monitoring of bus activities
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the time required to transfer one data word from one RT to another is around 120 seconds which is rather an expensive overhead. If, however a maximum of 32 data words were transferred, the overheads would be the same but representing a much lower percentage of overall message time. The Allowed RT response time is 4 to 12 sec intermessage gap 4 sec timing watchdog (response time) 14 sec
RT up to 1 ft. RT
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14.4.8.2 Disadvantages
a) need to have additional units (bus controller and bus monitor)
14.5. Other Databusses in use today (primarily for general aviation and business aircraft) 14.5.1 Commercial Standard Data Bus
Developed by Collins Division of Rockwell International (a major avionics manufacturer) a) similar to ARIN 429 (unidirectional) b) two data rates - 12.5 kbits/sec or 50 kbits/sec
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14.6.1 Advantages
Fiber optic cable provides the possibility of data rates in the neighbourhood of 100 MHz Another advantage is the immunity to electromagnetic interference.
14.6.2 Disadvantages
Fiber optic cables connections require very accurate alignment and thus it is difficult to make reliable connectors. The requirement for fiber optic connectors in the vibration and shock environment of an aircraft is especially severe. Also, glass fibers are relatively fragile which makes them susceptible to breakage under aircraft conditions.
The first step in designing software for an new avionics system is to define the criticality category. This is done by assessing the systems application and all failures which could result from a system malfunction. The three categories are: i) flight critical ii) flight essential and iii) flight non-essential. A systems category is defined by its most critical function.
The next step is to translate the criticality of the system to the software. The levels adopted by DO 178A are Levels 1, 2 and 3 which correspond to flight critical, flight essential and flight non-essential respectively.
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- software functions - the criticality of each function and software level - hardware and software interfaces - microprocessor characteristics - built in test (BIT) and monitoring requirements - what functional losses would occur as the result of software failure - timing, test and partitioning requirements
Once written the software must be tested. This includes, module testing, module integration tests and software/ hardware integration tests
As an example, module testing includes logic and computational tests to determine if the module performs its intended function. Logic testing is used to detect illogical sequences and constructs such as halted execution, executions trapped in a loop and missing input data. Computational tests consider an algorithms reaction to data within, outside and on the border of a specified range.
For flight critical systems, all verification results must be retained and all problems logged For flight essential systems, only a Statement of Compliance is required as a summary of the testing process.
System validation is intended to show that the system function properly under adverse and failure conditions
14.7.3 Software Conguration Management (SCM) and Software Quality Assurance (SQA)
Any system incorporating software must undergo SCM and SQA. This requires the submission of an SCM plan which may be part of the overall SQA plan. This includes a description of how SCM will be implemented and followed throughout the certification process. It should also include how SCM will be applied during the service life of the equipment.
SCM should include documentation, identification and change control and status accounting. This involves any post-certification software change
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If the change does not affect interchangeability or the certification basis, it may be called a software status change. If it does affect interchangeability or certification, the system will require a new part number
To comply with current standards it is necessary to use top-down programming techniques. This technique requires that the overall function of the software be broken down into a hierarchy of levels with each level performing more and more specific tasks. Ideally the smallest unit, called the module above, performs only one function and has exactly specified inputs and outputs.
This structure allows testing to be done in a logical fashion starting with each module and progressing up the chain
Figure 83:
Top Down Software Configuration