K.

Raji Reddy
Mobile: +91 8050644305 karegamraji81@gmail.com

Career Objective:
Skilled in designing IC layout dimensions with knowledge of IC layout design methods and techniques. Looking for an opportunity to work as an IC layout engineer in a renowned organization.

Skill Set:
Layout tool Layout Verification tool Other tools Languages Operating system Automation Timing : : : : : : : Virtuoso. Cadence, Assura. Xilinx FPGAs (Spartan6), MATLAB. C, Verilog HDL. MSDOS, Windows, Linux. SKILL, PERL. Static Timing Analysis (STA).

Work Experience:
Organization Designation : : Sankalp semiconductors. Intern.

Objectives and Responsibilities: This internship program imparted hands-on experience in Mixed Signal physical design. The responsibilities as part of the training project: Taken a leading role in the development of Mixed Signal blocks as part of the project. Understanding of the requirements from the designer. Perform Floor Planning, Layout design, Layout Verification. Perform EMI checks, Antenna checks and additional checks based on flow. Understanding of the TSMC technology rules and the process variations. Knowledge of Prevalent matching techniques.

Project at Sankalp semiconductor:

Title 1 Tools used
Description: This Project involve the Floor planning, placement, routing and verification at the top chip level consisting all sub blocks, Row decoder, memory control, memory array, Band-gap reference and etc. My Role: Worked on Area estimations & floor plan within the team. Layout development and verification of Memory array Row decoder Memory control Also worked on the Top-level of BPM.

: :

Blood Pleasure Monitor (BPM) Virtuoso, Cadence.

Title 2 Tools used

Description:

: :

Phase Locked Loop(PLL).

Virtuoso, Cadence.

This Project involve the Floor planning, placement, routing and verification at the top chip level consisting all sub blocks, level shifters, differential amplifiers, Op-Amps, current Mirrors and biasing circuits etc. My Role: Worked on Area estimations & floor plan within the team. Layout development and verification of Phase Frequency Detector (PFD) Voltage Controlled Oscillator (VCO) CP Decoder Loop Filter, Standard Cells etc. Responsibilities: Layout design includes both analog as well as digital design. Run Physical verification checks like DRC, LVS. Dummies prevention is done for all sensitive analog sections. Mostly common centroid technique is used to satisfy critical matching and to get more precision. The issues Electro migration checks were done.

Educational qualifications:
M.TECH in Digital Electronics and Communication system (DECS), 2012 Gurunanak engineering college, JNTU Hyderabad. B.TECH in Electronics and Communication Engineering, 2008 JNTU Hyderabad.

Academic projects:
Software Defined Gps Receiver Using Verilog (M_Tech): GPS satellites transmit two low power radio signals, designated L1 and L2. Civilian GPS uses the L1 frequency of 1575.42 MHz in the UHF band. The signals travel by line of sight, meaning they will pass through clouds, glass and plastic but will not go through most solid objects such as buildings and mountains. Path Tracking Robotic Controller (B_Tech): The aim of this project is to follow the black tape. This is an embedded system project intended to design and implementation a PATH FOLLWER ROBOT.

Strengths:
Quick learner. Punctual and responsible. Able to interact with people. Self motivated determined. Hardworking.

Personal details:
Fathers Name Dob Current Address Email ID Contact No : : : : : Vittal Reddy .K 09- Jun - 1986 H.no: 21-2-2/A, kalian puri Hyderabad. karegamraji81@gmail.com +91-8050644305/9490215615.

Declaration:
I hereby declare that all my above information is true and correct to the best of my knowledge &belief.

Date: Place: (K. RAJI REDDY)