Project 1. Implementation and simulation of 64 bit ALU.

--------TOP LEVEL-------------library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity ALU_64 is
generic(n:integer:=8);
Port ( A : in STD_LOGIC_VECTOR (n-1 downto 0);
B : in STD_LOGIC_VECTOR (n-1 downto 0);
clk:in std_logic;
S:in std_logic_vector(3 downto 0);---carry in is bit S(0);
F : out STD_LOGIC_VECTOR (n-1 downto 0);

cout : out STD_LOGIC);

end ALU_64;

architecture Behavioral of ALU_64 is

component mux2
generic(n:integer:=8);
Port ( F1 : in STD_LOGIC_VECTOR (n-1 downto 0);
F2 : in STD_LOGIC_VECTOR (n-1 downto 0);
s3 : in STD_LOGIC;
clk:in std_logic;
Y : out STD_LOGIC_VECTOR (n-1 downto 0));
end component;

component logical_unit
generic(n:integer:=8);
Port ( A : in STD_LOGIC_VECTOR (n-1 downto 0);
B : in STD_LOGIC_VECTOR (n-1 downto 0);
s : in STD_LOGIC_VECTOR (2 downto 0);
clk : in STD_LOGIC;

F : out STD_LOGIC_VECTOR (n-1 downto 0));

end component;
component arith_unit
generic(n:integer:=8);
Port ( A : in STD_LOGIC_VECTOR (n-1 downto 0):=(others=>'0');
B : in STD_LOGIC_VECTOR (n-1 downto 0):=(others=>'0');
clk:in std_logic;
s: in STD_LOGIC_vector(2 downto 0);
F : out STD_LOGIC_VECTOR (n-1 downto 0):=(others=>'0');
cout :out STD_LOGIC);
end component;
signal f1:std_logic_vector(n-1 downto 0);
signal f2:std_logic_vector(n-1 downto 0);
signal s1:std_logic_vector(1 downto 0);
begin
s1<= S(1 downto 0);
u1: logical_unit port map(A,B,S(2 downto 0),clk,f2);
u2: arith_unit port map(A,B,clk,S(2 downto 0),f1,cout);

u3: mux2 port map(f1,f2,S(3),clk,F);

end Behavioral;
-------------------------------------------------------------------------------

Logical unit..
-------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_1164.all;
entity logical_unit is
generic(n:integer:=8);
Port ( A : in STD_LOGIC_VECTOR (n-1 downto 0);

B : in STD_LOGIC_VECTOR (n-1 downto 0);

s : in STD_LOGIC_VECTOR (2 downto 0);
clk : in STD_LOGIC;
F : out STD_LOGIC_VECTOR (n-1 downto 0));
end logical_unit;

architecture Behavioral of logical_unit is

signal A1:std_logic_vector(n-1 downto 0);
begin
A1<= (7=>A(7),others=>'0');
process(clk)
begin

case s is
when "000" => F<= A and B;
when "001" => F<= A or B;
when "010" => F<= A xor B;
when "011" => F<= A nand B;
when "100" => F<= not A;

when "101" => F<= '0'& A(n-1 downto 1);--shift right-when "110" => F<= A(n-2 downto 0)&'0';--shift left-when "111" => F<= ('0'& A(n-1 downto 1)) or A1;
when others=> NULL;
end case;
end process;
end Behavioral;

Arithmetic unit-----------------------------------------------------------------------------------------------library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity Arith_unit is
generic(n:integer:=8);
Port ( A : in STD_LOGIC_VECTOR (n-1 downto 0):=(others=>'0');

B : in STD_LOGIC_VECTOR (n-1 downto 0):=(others=>'0');

clk:in std_logic;
s: in STD_LOGIC_vector(2 downto 0);
F : out STD_LOGIC_VECTOR (n-1 downto 0):=(others=>'0');
cout : out STD_LOGIC);
end Arith_unit;

architecture Behavioral of Arith_unit is

signal a1:std_logic_vector(n downto 0);
signal b1:std_logic_vector(n downto 0);
signal f1:std_logic_vector(n downto 0);

begin
a1<= '0'& A;
b1<= '0'& B;
process(clk)
begin
case s is
when "000" => f1<=a1;
when "001" => f1<=a1 + 1;
when "010" => f1<=a1+ b1 ;
when "011" => f1<=a1+ b1 + 1;
when "100" => f1<=a1 - b1 - 1;
when "101" => f1<=a1 - b1;

when "110" => f1<=a1 - 1;

when "111" => f1<=a1;
when others => NULL;
end case;
F<=f1(n-1 downto 0);
cout<=f1(n);

end process;

end Behavioral;
---------------------------------------------------------------------------

MUX 2:1
---------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
entity mux2 is
generic(n:integer:=8);

Port ( F1 : in STD_LOGIC_VECTOR (n-1 downto 0);

F2 : in STD_LOGIC_VECTOR (n-1 downto 0);
s3,clk : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR (n-1 downto 0));

end mux2;

architecture Behavioral of mux2 is

begin
process(clk)
begin
case s3 is
when '0'=> Y<=F1;
when '1' => Y<=F2;
when others=> NULL;
end case;
end process;
end Behavioral;
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