A Greedy Algorithm for Wire Length Optimization

Yiming Li, Yi Li and Mingtian Zhou

School of Computer Science and Engineering University of Electronic Science and Technology of China ChengDu, China icyore163@hotmail.com
AbstractGiven a LB-compact floorplan, it is obvious that we can get other floorplans with the same topology and area but different wire length by the white space distribution. In this paper, a greedy algorithm is proposed for wire length optimization. We derive significant conditions to identify the moving ranges of movable blocks. The moving cost tree is constructed. The maximum reduction on total half-perimeter wire length (HPWL) and offset for each block can be evaluated. Experimental results show that the greedy algorithm is effectively.

Fig.1 (a) Original LB-compact floorplan, whose wire length is not optimal. (b) Floorplan with the same area and topology. (c) Floorplan with overflow the frame. (d) Floorplan with the moving range

In this paper, TCG is used to describe the topology of original floorplan for its simplicity. The wire length is I. INTRODUCTION measured in the half-perimeter metric. The circuits are fist In the physical design of Very Large Scaled Integration placed by a traditional floorplanner. We can further improve (VLSI) circuits, floorplanning is an important step. It plans the the original wire lengths by an average of 3.6% and 4.2% on locations of circuit blocks on a chip subject to many objectives. the MCNC and GSRC benchmarks. Some representative floorplanners are listed as below, The rest of this paper is organized as follows. Section II Normalized Polish Expression (NPE)[1], Sequence-Pair defines the problem of white space distribution. In Section III, (SP)[2], Bounded Slicing Grid (BSG)[3], O-Tree[4], B*we review the TCG representation and introduce our greedy Tree[5] and Transitive Closure Graph (TCG)[6]. Other algorithm. Section IV analyzes the time complexity of our floorplanning algorithms with new ideas are also proposed, approach. Experimental results are reported in Section V, such as [7-12]. The amount of researches on the topic reflects the importance of floorplanning, but all of them place blocks followed by concluding remarks in Section VI. to the lower-left (upper-right) corner and then evaluate the II. PROBLEM DEFINITION wire length. Although the compaction obtains minimum area, A floorplan F is given with a set of m rectangular blocks its wire length may not be the optimal. We can get other floorplans with different wire lengths by distributing the white B={b 1,b 2,,bm}, whose width and height are expressed by wj space, while the area and topology is maintained. We illustrate and h j, whose coordinate of the lower-left corner is denoted this problem with an example in Fig.1. The dimensions of the by ( xj , yj), j=1,2,,m , and with a set of n networks N = {N1, three blocks are b1(44), b 2(22) and b3(42). The nets are N2, ,Nn}, where Ni describes the connections between N1:{b 1, b2} and N2:{b2, b 3}. We define that net N1's weight blocks, i=1,2,,n. The geometric constraints between each l1=2 and N2's weight l2=1. The net weight is distinguished by pair of blocks are listed as: bj is on the left of bk xj + wj xk (1) the width of highlight line. bj is below b k yj + hj yk (2). Tang et al. propose an efficient minimum-cost flow-based We try to find a floorplan F with the same area and topology, approach named Min-Wire algorithm [13] and claim to solve so that the total wire length the problem optimally. However, some problems can be n detected. First, parts of original HPWL are waived in the liW ( Ni ) (3) network graph. Second, no edge is defined to denote the white i =1 space between blocks. Third, the HPWL is fixed, with or without the min-cost flow algorithm. The Min-Wire algorithm is minimized, where W(Ni) denotes the HPWL of net Ni and i may not be good to deal with the problem. In addition, the is Nis net weight. studies on white space reallocation mostly aim at other Let W and H be the width and height of the bounding box objectives, such as buffer planning [14-15], thermal-driven of F. Let us assume net Ni connects a set of z pins {pi1, p i2,, floorplanning [16] and routability driven placement [17]. Thus, we need to study the white space distribution problem.

978-1-4577-1846-5/11/$26.00 2011 IEEE

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of bj. Thus, we can get the value of djhmax (djhmax0), and 0 dxi djh max , 0 dyi djvmax. In Fig. 2, we can get W=6, H=6, hs_dist1 = 0, hs_dist2 = 4, hs_dist3 = 0, vs_dist1 = 0, vs_dist2 = 0, vs_dist3 = 4, ht_dist1 = 6, ht_dist2 = 2, ht_dist3 = 4, vt_dist1 = 6, vt_dist2 = 4 and vt_dist3 = 2. Thus, we can get d1hmax=0, d 2hmax=0, d3hmax=2, d 1vmax=0, d2vmax=2 and d3vmax= 0. The horizontal moving range of b 3 is closed interval [0, 2], as shown in Fig. 1 (d). The vertical moving range of b 2 is closed interval [0, 2]. C. Moving cost tree It is obvious that horizontal movements of blocks do not affect the y-coordinates of the pins, and vice versa. Thus, we will focus on the horizontal movement only. Consider the set of nets Q(bj) connecting bj. If bj is moved, the possible positions of the pins on b j affect the horizontal wire lengths of the nets in Q(bj). Let hmctj (vmctj) denote the relationship between the movement and its effect. hmctj is a segment tree structure and its leaf has two elements: the cost (summation of net weight) and the elementary interval. The moving range [0, djhmax] is split into segments by hmctj. The net weight and relevant interval are inserted into hmctj, with the interval dividing technique. The inserting net weight is plus to the existing costs of leaves between relevant interval. If the cost of a leaf is positive, the movement of the block will reduce the wire length. Otherwise, it will increase the wire length. We simply divide the pins into three types: Non-effect pins, Increscent pins and Decrescent pins. Non-effect pins: Pins can not be moved or the movements of them will not affect the wire length. We will insert nothing. Increscent pins: The movements of pins will increase the wire length. We will insert negative net weights and relevant intervals into hmctj. Decrescent pins: The movements of pins will decrease the wire length. We will insert positive net weights and relevant intervals into hmctj.

Fig. 2: (a) Gh; (b) Gv; (c) Horizontal key tree; (d) Vertical key tree.

piz}. Let (Li, Bi) and (Ri, Ti) refer to the lower-left and upperright corners of the bounding box of Ni. Let (pxik, pyik) be the coordinates of p ik and (rel_pxik(j), rel_pyik(j)) be its relative offset from (xj , yj) of bj. Thus, we have "k {1, 2,, z} Li xj + rel_pxik(j) (4) Ri xj + rel_pxik(j) (5) Bi yj + rel_pyik(j) (6) Ti yj + rel_pyik(j). (7) The problem (3) can be stated as
i =1 (8) subject to the set of constraints as stated in (4)-(7). Then problem (8) can be decoupled into two subproblems

min li ( Ri - Li + Ti - Bi )

min li ( Ri - Li )
i =1 n

subject to the constraints as stated in (1), (4) and (5), and

(9) (10)

min li (Ti - Bi )
i =1

subject to the constraints as stated in (2) , (6) and (7). Subproblem (9) and (10) can be solved separately. III. GREEDY ALGORITHM

A. Review of TCG TCG has two graphs named horizontal transitive closure graph G h(Vh, Eh) and the vertical Gv(Vv, Ev) to represent the geometric relations between blocks. Gh and Gv of the floorplan in Fig. 1 (a) are shown in Fig. 2. More details of TCG algorithm can be found in [6]. B. Moving range We assume that F is LB-compact floorplan. Let dxj and dyj be the offsets from original position of b j, horizontally and vertically. Let closed intervals [0, d jh max] and [0, djvmax ] denote the moving ranges of block bj, which prevents overflow of the outline. Let endpoint d jhmax (djvmax) be the maximum distance for which bj can be moved. Let hs_distj (vs_distj) denote the length of the longest path from the source s to node j in Gh (Gv). Let ht_distj (vt_distj) denote the length of the longest path from node j to the sink t. The value of endpoint djh max (djvmax) can be gotten from W- hs_distj - ht_distj (H- vs_distj- vt_distj). Summation of hs_distj + ht_distj represents the length of the path from the source s to the sink t, which may not be the longest. If bj is in the longest path, we can get W = hs_distj + ht_distj and d jhmax= 0. It means that b j is fixed. If bj is not in the longest path, we can get d jhmax= W- hs_distj - ht_distj > 0. hs_distj represents the widths summation of blocks at the left of bj. ht_distj represents the widths summation of blocks at the right

Consider a net Ni connecting a set of z pins {pi1, p i2,,piz}, and the z pins are in an ascending order in x-direction (0pxi1 pxi2pxiz). The movement of Li (Li = pxi1) or Ri (Ri= pxiz) will affect the horizontal wire length, but pik is on different blocks with various moving ranges. Let Limax (Rimax) denote the possible rightmost position of Li (Ri). We will insert corresponding elements into hmctj, when deciding the value of Limax (Rimax) for each net Ni. The simplest case is that pi1 and piz are fixed and Noneffect pins, we will insert nothing. Other four representative cases are shown in Fig. 3. With different insertions, we construct the final moving cost tree hmctj for each block. For the floorplan in Fig. 1 (a), b 1 and b 2 are fixed in Gh, and hmct1=hmct2=NULL. The movement of b 3 will reduce horizontal wire length of N2, and hmct3=2 [0,2]=1 [0,2]. b1 and b 3 are fixed in Gv, and vmct1= vmct3= NULL. The

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2) 3)

Build the moving cost tree structure for each block in G h and Gv. Travel the blocks in topological order, construct the key tree and evaluate the maximum improvement of the wire length to locate the positions of blocks. IV. TIME COMPLEXITY

Fig. 3: Four representations when searching for Limax and R imax. TABLE I. Test Cases apte xerox hp ami33 ami49 n10 n30 n50 n100 n200 n300 No. of Cells 9 10 11 33 49 10 30 50 100 200 300 INFORMATION OF THE TESTING CIRCUITS No. of Nets 97 203 83 123 408 118 349 485 885 1585 1893 No. of Pads 73 2 45 42 22 69 212 209 334 564 569 No. of Pins 264 696 214 480 931 179 511 841 1539 3035 3789 No. of Noneffect Pins
x-dir y-dir

Percentage 55.49% 58.18% 84.35% 54.69% 27.71% 37.15% 29.35% 26.34% 21.22% 33.53% 39.70%

128 477 117 280 237 65 124 247 239 1026 1463

165 332 244 245 279 68 176 196 414 1009 1546

In a floorplan F with m blocks and n networks, the time complexity of the greedy algorithm is consisted of three steps. The time complexity of step 1) is O (m2). The complexity of step 2) is complicated. We assume that the number of pins on b j is constant q on average, and q intervals will be inserted into hmctj in the worst case. The complexity of insertion to segment tree is O(qlog(q)). We assume the number of pins connected Ni is constant z on average and the total number of pins is nz (nz=mq). The complexity of step 2) is O (nzq log(q)) = O(n ). In step 3), the complexity of constructing b js key tree is O(m2). The complexity of the merge operation of two segment tree is O(q2log(q)) and there are m segment trees at most. The complexity of evaluating the maximum improvement is O(nz). Thus, the complexity of step 3) is O (m2+m*(mq2log(q )+nz)) = O (m2+n 2+mn ). Finally, the total complexity of the greedy algorithm is O(m 2+mn+n2). V. EXPERIMENTAL RESULT All programs are written in C++ and run on a PC with AMD 1.83GHz CPU and 1GB RAM. The MCNC and GSRC benchmark circuits are used as our test cases. The pre-placed original floorplans are obtained from TCG floorplanner[6] with minimum wire length option. It is ensure that all the original floorplans are well-optimized in terms of wire length. For all test cases, we use the original fixed location of pins and the location of IO pads are resized proportionally to the frame boundaries. Then we apply our approach to all of the original floorplans. Note that we assume i=O(1) for all nets. Detailed information of the original circuits and Non-effect pins are shown in Table I. There are about 21%-84% of the pins are Non-effect pins, which can be omitted in the computation. The summaries of the improvement in HPWL for MCNC and GSRC benchmarks are shown in Table II and Table III, respectively. The maximum improvements are about 3.6% and 4.2% on average. The runtimes are also shown in the tables. There is 3.6% and 4.2% reduction of wire length with about 7.38s on average. Fig.4 displays the results of original floorplan and improved floorplan for n300 circuit.

movement of b 2 will reduce vertical wire lengths of N1 and N2, and vmct2=1[0,1]+(-1)[1,2]+2[0,2]=3[0,1]+(-1)[1,2]. D. Key tree An edge (j, k) is said to be a reduction edge if there does not exist another path from bj to bk, except the edge (j, k) itself [6]. Consider the closure set of blocks R(b j) includes bk with reduction edge (j, k) and adjacent to b j, or bl with reduction edge (k, l) and adjacent to b k. The horizontal key tree of bj is consisted of blocks in R(bj) and corresponding edges. If bj is moved to the right, the blocks in R(b j) must satisfy the constraints (1), otherwise there will be overlapped. Thus, the movement of bj will change the position of bk and the wire length of nets connected to b k, bk R(bj). The key tree of floorplan in Fig. 1 (a) is shown in Fig. 2. E. Reduce the wire length We should know the maximum improvement of the horizontal wire length. We will travel the blocks in a topological order from left to right in x-direction. Given an arbitrary block b j, we construct its key tree and merge all of the moving cost trees of blocks in R(bj) into one. Then the maximum improvement, the value of dxj can be obtained and we will move blocks in R(bj) for distance dxj in x-direction.

We intend to compare our approach with the Min-Wire algorithm. Although we construct the same original For the floorplan in Fig. 1 (a), the travel order is b1, b 3, b2 floorplan in [13] and use the center of block as the location of in x-direction, and b 1, b2, b3 in y-direction. The maximum the pin, we get the wire length is 103.1mm for ami33 and horizontal improvement is 1 (2-0)=2. We can get dx1=0, 1179.1mm for ami49. The reconstruction is shown in Fig. 5. dx2=0 and dx3=2. The maximum vertical improvement is However, the wire lengths are claimed to be 60.0mm and 3(1-0)=3. We obtain dy1=0, dy2=1 and dy3=0. Thus, the 790.1mm in [13]. Thus, we do not list the results from Minfinal positions are x1 = 0, x2 = 4, x3 = 2, y1 = 0, y2 = 1 and y3 = 4. wire approach in Table II. Our greedy approach is divided into three steps. 1) Derive the moving range for each block in Gh and Gv. VI. CONCLUSION In this paper, we have proposed a novel greedy algorithm to optimize the wire length by distributing white space for

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wire length optimization. The experimental results show that our algorithm is effective as a post-floorplanning refinement.
TABLE II. Circuit apte xerox hp ami33 ami49 Average
x-dir

A SUMMARY OF THE IMPROVEMENT ON MCNC CIRCUITS After(mm)

x-dir y-dir total x-dir

Original Wire(mm)
y-dir total

Improve
y-dir total

Time( s) 0.05 0.08 0.06 0.09 0.21 0.10

190.1 223.4 117.3 27.2 402.5

214.7 171.0 48.7 35.0 454.1

404.8 394.3 166.0 62.2 856.5

177.0 211.7 111.9 26.4 391.2

212.2 164.4 48.3 33.9 440.2

389.2 376.1 160.2 60.3 831.3

3.2% 2.9% 3.2% 1.3% 1.3% 2.4%

0.6% 1.7% 0.3% 1.6% 1.6% 1.2%

3.9% 4.6% 3.5% 2.9% 2.9% 3.6%

TABLE III. Circuit n10 n30 n50 n100 n200 n300 Average
x-dir y-dir

A SUMMARY OF THE IMPROVEMENT ON GSRC CIRCUITS After( mm)

x-dir y-dir total x-dir

Original Wire( mm)

total

Improve
y-dir total

Time(s) 0.06 0.14 0.25 1.85 12.14 29.83 7.38

17.055 49.290 75.564 91.991 190.285 256.733

20.851 77.404 64.588 130.559 216.464 299.183

37.906 126.694 140.152 222.550 406.749 555.916

16.916 46.408 73.272 88.468 184.164 251.030

17.737 74.713 62.150 127.647 210.104 287.773

34.653 121.121 135.422 216.142 394.268 538.803

0.4% 2.3% 1.6% 1.6% 1.5% 1.0% 1.4%

8.2% 2.1% 1.8% 1.3% 1.6% 2.1% 2.8%

8.6% 4.4% 3.4% 2.9% 3.1% 3.1% 4.2%

Fig. 4 (a) Original floorplan (555.9mm)

(b) Improved floorplan (538.803mm)

Fig. 5(a) Reconstruction of ami33

(b) Reconstruction of ami49

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