Entity Instantiation - An easy way of Port mapping your components

In the earlier part of this blog I have given some common method of declaring and port mapping your components in the main module.This article is a continuation of that one.If you are not aware of any port mapping methods I recommend you to go through the old article here. The disadvantage with the older port mapping methods was that,you needed to copy your component declaration in your main modules.This can result in larger code size.With entity instantiation method you can save some extra length in the code. Let me show this method using the old fulladder-halfadder module.We are going to implement the following block diagram in VHDL.

The half adders are implemented as follows:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity halfadder is Port ( a : in STD_LOGIC; b : in STD_LOGIC; sum : out STD_LOGIC; carry : out STD_LOGIC ); end halfadder; architecture Behavioral of halfadder is begin sum <= a xor b; carry <= a and b; end Behavioral;
--The top module 'full adder' is given below:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; --top module(full adder) entity declaration entity fulladder is port (a : in std_logic; b : in std_logic; cin : in std_logic; sum : out std_logic; carry : out std_logic );

end fulladder; --top module architecture declaration. architecture behavior of fulladder is signal s1,c1,c2 : std_logic:='0'; begin --instantiate and do port map for the first half adder. HA1 : entity work.halfadder port map(a,b,s1,c1); --instantiate and do port map for the second half adder. HA2 : entity work.halfadder port map(s1,cin,sum,c2); carry <= c1 or c2; --final carry calculation end;
Note the lines starting with 'HA' in the above code.Here is where we port map the component 'half adder'.Note that 'work' is the default directory where all your project files will be compiled into.'halfadder' is the component name as defined in the first code. Remember to give the inputs and outputs in the same order as given in the definition of your component. If you don't want to give the inputs in any particular order then you can also port map in the following way:

--first half adder instantiation. HA1 : entity work.halfadder port map( a => a, b => b, sum => s1, carry => c1 ); --second half adder instantiation. HA2 : entity work.halfadder port map( a => s1, b => cin, sum => sum, carry => c2 );
The RTL schematic generated by the Xilinx XST is given below :

Note :- Use "Entity Instantiation" method as much as possible to port map your components.