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Computing with complex-valued networks of phase oscillators

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 May 2013
EPL, 102 (2013) 40007 www.epljournal.org
doi: 10.1209/0295-5075/102/40007

Computing with complex-valued networks of phase oscillators

M. Zanin1,2,3 , D. Papo1 and S. Boccaletti4
1
Center for Biomedical Technology, Technical University of Madrid, Campus Montegancedo
28223 Pozuelo de Alarcón, Madrid, Spain, EU
2
Faculdade de Ciências e Tecnologia, Departamento de Engenharia Electrotécnica, Universidade Nova de Lisboa
Lisboa, Portugal, EU
3
Innaxis Foundation & Research Institute - José Ortega y Gasset 20, 28006, Madrid, Spain, EU
4
CNR - Institute of Complex Systems - Via Madonna del Piano 10, 50019 Sesto Fiorentino, Florence, Italy, EU

received 1 March 2013; accepted in final form 14 May 2013

published online 10 June 2013

PACS 05.45.Xt – Synchronization; coupled oscillators

PACS 02.10.Ox – Combinatorics; graph theory
PACS 89.20.Ff – Computer science and technology

Abstract – A computational paradigm based on phase-locked states of oscillators embedded in

a complex-valued weighted network is introduced, and its efficiency and scalability in performing
single- and multiple-input Boolean and non-Boolean operations are demonstrated. The paradigm
introduces phase rotation mechanisms in each link of the network, without the need for
external control loops, or adaptive mechanisms. We show that the proposed computation allows
outperforming standard implementations of Boolean logic, by reducing the computational cost of
operations, and permitting the construction of memory elements with single dynamical units.

c EPLA, 2013
Copyright

Introduction. – Representing information and
computing by means of systems composed of dynamical
units has attracted huge attention in recent years in fields
as diverse as cellular automata [1], lattices of coupled
chaotic maps [2], chemical and neuronal diodes [3,4],
patterned neuronal cultures [5] and chaotic neurons [6],
or coupled non-linear systems [7,8]. The most promis-
ing methods are possibly those constructing Boolean
ports with chaotic circuits (the so-called chaos comput-
ing [2,9,10]), or using adaptive mechanisms [11,12]. How-
ever, the former requires an external control to force the
dynamics into a desired state, the latter implies a fast
timescale for adaptation which is not always easy to imple-
ment. On the other hand, how ensembles of oscillators
embedded in a (complex) network [13,14] collectively orga-
nize into a synchronized evolution has widely been studied
both theoretically and experimentally [15,16]. The use of
such synchronous states for computation is an issue of
the utmost importance, particularly due to their inherent
relevance to the understanding of processes taking place in
the brain, where the synchronization of groups of neurons
is one of the milestones of neural computation [17,18].
In this letter, we show how computation can naturally
be associated to phase-locked states of oscillators, once the
latter are the nodes of a complex-valued weighted graph,
i.e., when the interactions between oscillators are defined
as complex numbers. Classically, networked units interact
by means of real-valued coupling strengths. Here, instead,
the use of complex weights allows not only setting the
coupling by means of their moduli, but also introducing
phase rotations through their arguments. For oscillators
in a frequency-locked regime, such a coupling scheme
creates multiple stable phase-locked states, which can
codify information by means of the difference between the
oscillator’s phase and that of a global reference. We show
how such an information can be processed efficiently, and
how Boolean as well as non-Boolean (i.e., not restricted
to 0 and 1 states) representations can be constructed.
Description of the model. – Without loss of gener-
ality, we illustrate our findings for N Kuramoto-like oscil-
lators which, both for their simplicity and analytical
tractability, constitute a benchmark model for the study
of synchronization of networked phase oscillators. The
main difference with respect to the classical case [19]
is that here the network supporting the interactions is
complex-valued, i.e., each element of the weight matrix
wij is a complex number. The system under study is then
defined as


θ̇i = ω + λ |wji | sgn [sin (θj + arg wji − θi )]. (1)
j
=i

40007-p1
M. Zanin et al.
NOT gate
I -1 Output
Fig. 1: (Color online) Left: time evolution of the phase of
two oscillators, when the coupling weight between the master
(black solid line) and the slave (blue dashed line) is −1. After
an initial transient, both oscillators synchronize with a phase
difference of π. Right: schematic representation of the circuit
creating such a dynamics, that corresponds to a NOT Boolean
gate.
In eq. (1), θi is the phase of oscillator i (i = 1, . . . , N ),
ω is the natural frequency common to all oscillators, λ
is a global coupling parameter, and |wji | and arg wji are,
respectively, the module and the argument of the weight
of the link connecting node j to node i. Notice that the
sgn function discretizes to either 1 or −1 the value of the
output of the sin function.
The functioning of complex-valued coupling can be
illustrated for two oscillators i and j with different initial
phases and arranged in a master-slave configuration. The
argument of the sin function in eq. (1) explicitly contains
the argument of the complex weight wji . If arg wji = 0, the
stable phase-locked state only corresponds to equal phases
of oscillators i and j. More generally, such a phase-locked
state, for which no coupling force is generated, is defined
by θj − θi = − arg wji . For instance, when wji = −1, the
slave oscillator eventually synchronizes with the master,
but with a phase difference of π. Figure 1 illustrates this
scenario.
In the following, we describe the way the multiple
phase-locked states that may be produced via eq. (1)
can conveniently be exploited for computing. Performing
computation requires a reliable mean of representing
information, so that it can be stored, retrieved, and
manipulated efficiently; for instance, in the standard
Boolean logic used in microprocessors, the information is
represented by means of two electrical states, 0 and 1.
We start by encoding information in the phase difference
between oscillators in the frequency-locked state. The 1
state is defined by the dynamics of a reference pacemaker
oscillator; on the other hand, the 0 state is given by the
signal rotated by an angle π with respect to the 1 state.
In fact, the example with two oscillators connected with
a weight of −1 is fully equivalent to a NOT gate (see again
fig. 1). Given a generic input, the output is always rotated
by an angle π, and is therefore always the result of a
NOT Boolean operation on the input: when the oscillator i
generates the reference signal (i.e., the 1 state), the output
of node j is the logical state 0, and vice versa.
40007-p2
Performing higher-level Boolean operations requires
building a NOR gate, one of the two universal Boolean
gates, from which any other static Boolean function can
be derived [20,21]. The NOR gate has two inputs and
one output; the output value is 1 only when both inputs
are at a logical state 0, and 0 otherwise. Figure 2 shows
the representation of the NOR gate (where reference and
input signals are all entering the computing oscillators
with weights −1), together with the corresponding time
evolutions of all signals involved in it. Three different
dynamics can emerge from this configuration. Due to the
π phase shift introduced by each incoming link, when both
inputs are 0, the computing node is driven toward the 1
dynamics, and the reference signal is unable to block the
expression of this state. However, inputs in opposite states
(1 − 0 or 0 − 1) cancel out, as their coupling forces push
in opposite directions; the reference signal with weight
w = −1 then drives the computing node toward the 0 state.
Finally, if both inputs are 1, the computing node is driven
toward 0. In summary, the 1 state will only be expressed
if both input dynamics are in the 0 state (see the time
evolution of the signals reported in fig. 2).
While in fig. 2, for the sake of clarity, all coupling
strengths have been set to 1, it should be noticed that
this requirement can easily be relaxed. As previously
explained, in order to have both inputs cancel out when
they have opposite states, i.e., 1 − 0 or 0 − 1, their corre-
sponding coupling strengths should be equal, so that the
only input effectively acting over the oscillator is the refer-
ence state. In this case, any positive strength will be
enough for the reference state to lock the oscillator into the
desired dynamics. On the other hand, when both inputs
have the same state, i.e., 0 − 0 or 1 − 1, their combined
signals should be greater than the one corresponding to
the reference state. Summing up, if we define the strength
corresponding to the two inputs as σ, the emergence of the
correct computation is guaranteed as long as the strength
of the reference state is in the (0, 2σ) range.
It must be noticed that the value of σ, and more
generally of the coupling strengths, determines the time
required to reach the phase-locked state. In principle,
the higher such strengths, the smaller the convergence
time. Yet, since the value of the coupling is introduced
in the oscillator dynamics through the sign of the sine
of phases difference (and not just though the sine, as in
the standard Kuramoto equation), strong couplings may
introduce oscillations of the phase around the phase-locked
state; this, in turn, can introduce noise in the output
signal, which may propagate through all computation
elements. Therefore, when high computation velocity is
required, both the strengths and the integration time step
should be chosen accordingly.
Figure 3 shows the connection patterns corresponding to
some other important Boolean gates. To obtain a NAND
gate (the second universal Boolean gate), one only needs to
modify the NOR configuration, and change to 1 the weight
of the reference signal input. Furthermore, changing the
 Computing with complex-valued networks of phase oscillators

NOR gate
R
-1
I1 -1 Output
I2
-1

Fig. 2: (Color online) Left: computation of a NOR function. From top to bottom, time evolutions refer to: the reference oscillator
(used to represent 1 bits), the 0 reference signal (created with a NOT gate applied to the reference oscillator), the two inputs
signals, and the output signal. Black solid lines represent a 1 status, while red dashed lines represent 0 bits. Right: schematic
representation of the connections required to construct the NOR gate.

NAND gate AND gate Majority gate

R R R
+1 -1 I1 +1 +0.5
I1 -1 Output I1 +1 Output I2 +1 Output
I2 I2 I3 +1
-1 +1
…

Fig. 3: Schematic representations of the connections required to construct the NAND, AND and majority Boolean gates.

sign of all weights of the NAND gate results in the couplings representing interactions between them; the
complementary AND gate. A first important conclusion state of each spin then codifies a Boolean value. Yet,
can be drawn: a complex-valued directed network of phase the most important advantage of the proposed frame-
oscillators, in which weight moduli are set to 1, already work is represented by the possibility of breaking away
allows performing any Boolean operation (in the sense from the classical 2-state Boolean information processing.
of a Turing machine), with each specific operation (i.e., In the previous examples, the 2-state representation was
combination of NAND and NOR gates) corresponding to constructed by starting from a reference signal, represent-
a given motif of the network [22]. ing a 1 state, and rotating the phase by π to obtain the
Several further noticeable advantages result when the logical 0 value. The idea can, in fact, be extended to repre-
oscillators are embedded in a fully weighted network, sent information with  states, if the signal corresponding
i.e., by no longer imposing that the weights’ modulus be to each state is obtained by rotating the reference signal
unitary. The first is to drastically reduce the complexity by 2
πk (with k = 0, . . . ,  − 1).
of some Boolean operations. One example is the config- The ability to codify multiple states has many impor-
uration associated to the majority gate (the third gate tant consequences. For instance, it allows considering the
of fig. 3), a circuit whose output is 1 if the majority of signal as a number in base , so that each node encodes
the inputs are equal to 1, and zero otherwise. Remark- an integer number between 0 and  − 1. By appropriately
ably, while our method only requires one oscillator to connecting nodes, various numerical operations can be
perform the majority operation, independently of the performed. In fig. 4 the simple case of the increment (the
number n of inputs, in standard Boolean logic the major- addition of 1 to the input number) is achieved for  = 4,
ity gate is known to have a complexity of O(n5.3 ), and by rotating the phase of the input signal by an angle of
π
cannot be computed by AC0 circuits of sub-exponential 2 . Once again, while standard Boolean logic requires at
size [23]. least 7 gates to build an increment operation with three
bits [20,21], our method only requires one oscillator. This
n-state computation. – At this point, it should be advantage becomes increasingly conspicuous the larger the
noticed that most of the proposed results can be obtained value of , as here only one oscillator is required indepen-
by means of other discrete physical systems. For instance, dently of the number of states that need to be unitarily
oscillators may be substituted by Ising spins [24], with incremented.

40007-p3
M. Zanin et al.

Boolean memory Four-state memory

Increment 0 1
Set 1
1
πi Output 1/2 π i
e 2
Reset
Output
I -1 π
-1
3/2 π -i

Fig. 4: (Color online) Left: schematic representation of the Fig. 6: Schematic representations of a Boolean (left) and a
increment circuit. The Kuramoto oscillator is synchronized multi-state (right) memory circuit.
with the input signal, but with a phase rotation of π/2: in a
representation with base  = 4, this is equivalent to increment
the number by one. Right: representation of the dynamics of
the coupling mechanism. The green small circle represents the
phase of the input signal; green arrows depict the resulting
coupling forces.

Median value
R
-0.5
+1
I
+1 Output
I
+1
I
…

Fig. 5: (Color online) Top: schematic representation of the

median value circuit. Bottom: examples of the coupling forces
for two different sets of 4 inputs (represented by the small
green circles). Solid green arrows indicate the coupling force Fig. 7: (Color online) Robustness to noise of the computa-
resulting from each input, while the red dashed arrows indicate tional paradigm. Black solid and blue dashed lines respectively
the resulting coupling force. An additional input, represented represent the robustness to noise of a NOR gate and of a circuit
by a small blue square and connected to the reference time composed of a NOR gate followed by 4 NOT gates in a linear
series with weight w = −0.5, is used to resolve tied situations. chain configuration. Top: mean squared error of the output.
Bottom: number of erroneously codified bits for a Boolean
NOR gate, for different standard deviations of a white Gaussian
Figure 5 shows another operation on multiple inputs noise added to the gates’ inputs.
(the calculation of the median value) that we can perform
with just a single unit. Each of the inputs, with coupling
the most important of which being a memory. Figure 6,
strength 1, attracts the oscillator toward its corresponding
phase value: the output phase, therefore, will represent left, depicts the circuit associated to a Boolean set reset
the median of the distribution of inputs. Notice that an flip-flop. When the set (reset) input has a value of 1,
auxiliary input is connected with strength −0.5 to the the dynamics of the unit is attracted toward the 1 (0)
reference value R, i.e., the signal corresponding to the state; afterwards, when all inputs have a 0 value, they
numerical value 0: this is used to resolve tied situations cancel out, and the oscillator can follow its own dynamics
when the number of inputs is even. —effectively maintaining the previously imposed state. It
is worth noticing that no feedback loop is required, as the
Dynamical gates. – So far, we concentrated on motifs dynamics of the oscillator in the free regime is already a
representing static gates, where the output solely depends function of its own past. Figure 6, right, expands this idea
on the actual status of the inputs. Yet, our paradigm to the case of multiple states (namely, for  = 4). When
can easily be expanded to encompass dynamical gates, one of the four inputs has a value of 1, the dynamics of

40007-p4
 Computing with complex-valued networks of phase oscillators

the oscillator is forced towards the state represented by ∗∗∗

that input (from top to bottom, 0, 1, 2 and 3); when all
four inputs are set to 0, the unit maintains memory of its Work supported by the BBVA-Foundation within the
previous state. Isaac-Peral program of Chairs. Authors acknowledge
Robustness against noise. – As a last topic, we Ruedi Stoop for many useful discussions, and the usage of
discuss the issue of robustness of the system against the resources, technical expertise and assistance provided
noise contamination, due to its relevance for real-world by supercomputing facility CRESCO of ENEA in Portici
applications. Equation (1) represents the noiseless case (Italy).
of identical oscillators (ω = ω1 , ω2 , . . . , ωN ), for which it
is well known that the phase-locked state is a point
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