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Advanced Digital Design

Lecture 13: Datapath Component: Multiplier Architecture

Multiplication by repeated shift and add Digital multiplication flow Partial product generation Partial product reduction schemes

Contents of this Lecture

Booth Recoding Multiplication with a constant

Carry Save Reduction Scheme Dual Carry Save Reduction Scheme Wallace Tree Reduction Scheme Dadda Tree Reduction Scheme

A simple Shift and Add Multiplier


N Prod shift_reg B

N
N-bit Adder

N
0 mux 1

0 A N Reg_A

Example of Multiplication (by shift and add)

Partial Product is accumulated and shifted right at each step

Signed Multiplier

Carry Save Adder

Digital multiplication flow


N-bit inputs operands (N = 4)

Partial Product Array Generation

shifted binary numbers

=N

Partial Product Array Reduction = reduction to 2 binary numbers

Final addition = 2n-bit final product

Major parts of a Multiplier


Multiplier Multiplication

Formation of Partial Products

Addition of Partial Products (Reduction)

Final Addition Stage

Product

Reducing the Partial Product Matrix

1 1 1 1

1 1 1

Partial product generation for 6-bit by 6-bit multiplication multiplier a5 a0 multiplicand b5 b0

ppij

columns to be added

Use an array of AND gates to produce partial products in parallel

Partial Product Generation

Array Multiplier

What do we need to realize Array Multiplier? AND gates = ? FA = ? HA = ?

Array Multiplier (contd)

Partial Product Generation in Verilog


define WIDTH = 6 module multiplier (a, b, prod); input [WIDTH-1:0] a,b; output [2*WIDTH-1:0] prod; reg [WIDTH-1:0] pp [0:WIDTH-1]; always@(a or b) for(i=0; i<WIDTH; i=i+1) pp[i] = a & {WIDTH { b[ i ] } };

Dot Notation
M ultiplicand
y[3] y[2] y[1] y[0]

x[ 0]

M ultiplier

Partial Products
y[3] y[2] y[1] y[0]

x[ 1]

Partial Product Reduction


Level n

Level ( n+1)

sum carry

sum carry

(Full Adder)

(Half Adder)

No action

Partial Product Reduction


Three dots are shown Each symbolizes a partial product Using FA reduces these to two bits One has the weight of 20(sum) The other has the weight of 21(carry) This type of reduction is known as 3 to 2 reduction or carry saves reduction The two dots are reduced to 2 using a HA

Partial Product Reduction Schemes for high speed multipliers


Carry Save Reduction Scheme Dual Carry Save Reduction Scheme Wallace Tree Reduction Scheme Dadda Tree Reduction Scheme

12x12 Carry Save Reduction Scheme

Level 1

HA

FA

FA

FA

FA

FA

HA

P0

Level 2

HA

FA

FA

FA

FA

FA

HA

P1

Level 3

HA

FA

FA

FA

FA

FA

HA

P2

Level 4

HA

FA

FA

FA

FA

FA

HA

P3

PC10

PS9 PC9

PS8PC8

PS7PC7

PS6PC6

PS5PC5

PS4 PC4

PS3

Free product bits

Carry Save Array

Dual Carry Save Reduction

In dual carry save reduction scheme, the partial products are divided into 2 equal size groups The carry save reduction scheme is applied on both the groups simultaneously This results into two partial product layers in each group

Wallace Tree Multipliers


One of the most commonly used multiplier architecture Wallace Tree multiplier falls in the category of log time array multiplier The number of adder levels increases logarithmically as the partial product rows increase

Wallace Tree Multipliers


Grouping the partial products into groups of three carries out the reduction Unlike linear time arrays, these partial product groups are reduced simultaneously through carry save addition technique Each partial product row spits out two rows These rows then, with other rows from other partial product groups, form a reduced matrix This process continues until only two rows are left At this stage, no further reduction is done The final rows are added together for the final product

Adder Levels in Wallace Tree Reduction Scheme


Number of partial Products 3 4 5n6 7n9 10 n 13 14 n 19 20 n 28 29 n 42 43 n 63 Number of full adder Levels 1 2 3 4 5 6 7 8 9

6 x 6 Wallace tree

Dada Tree Reduction

Also a member of the log time array multipliers since it is a modified version of the Wallace tree Dadda tree works exactly the same as the Wallace tree Requires the same number of adder levels It uses less number of computational elements as compared to Wallace tree

Dada Tree Reduction

In the previous example of a 12x12 partial product array, Wallace tree takes 99 full adders 33 half adders to reduce it to two Dadda tree uses 96 full adders 13 half adders to reduce the same matrix to two rows

Dada Tree Reduction

To understand the working logic of Dadda tree, consider the following sequence from Wallace Tree reduction scheme table 2, 3, 4, 6, 9, 13, 19, 28, Each number represents the number of partial products remaining at each level of addition The sequence says that 2 partial products can be obtained from at the most 3 partial products 3 can be obtained from 4 4 from 6 and so on

Dada Tree Reduction


In a 12x12 array, need not reduce 12 partial products to 8, as being done in Wallace Reduced it to 9, since 9 is as good as 8 partial products as far as the number of logic levels are concerned Following this scheme would result in optimally low number of computational elements

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