6.

IO Data Transfer Techniques

8 July 2013

Module 1
Basics of 8085:

I/O Data Transfer Techniques

Mapping techniques I / O mapped I / O and memory mapped I / O.

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I/O Data Transfer Techniques

BASIC INTERFACING CONCEPTS 1) Input port 2) Output port

I/O Data Transfer Techniques

2) Output port : It is used to send data to Output device from MP. When MP wants to send the data to the output device, it puts the data on the data bus & activates the clock signal of the latch .
Data from I/p device (keyboard)

Output port
D0-D7
(Latch)

1) Input port : The data transfer between MP & Input device is done with the help of Input port. When MP wants to read data from input, it sends control signal that activates the buffer (Enable) & the data from Input device is available on the data bus.
Input Port
D0-D7
(Tristate buffer)

From 8085
CLK

To output device (display)

From 8085

To 8085

Enable

From 8085

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6. IO Data Transfer Techniques

8 July 2013

I/O Interfacing Techniques

1) I/O mapped I/O 2) Memory mapped I/O

I/O mapped I/O

In this method 8085 uses IO/ M signal to distinguish between I/O read , write and Memory read , write operations. It has two instructions IN and OUT for I/O data transfer. In this, higher address bus duplicates the content of lower address bus, when 8085 executes IN or OUT instructions.

Ex:- The device address is 80H

A7 A15 1 A6 A14 0 A5 A13 0 A4 A12 0 A3 A11 0 A2 A10 0 A1 A9 0 A0 A8 0

Device address Device address

80H

IN Instruction (IN 80H)

T1
A15

OUT Instruction (OUT 81H)

T1 T2 T3
A15

T2

T3

T4

T1

T2

T3

T1

T2

T3

T2

T3

T4

T1

T2

T3

T1

A8

PC H PC L

UNSPECIFIED

PC H PC L
81H

PORT ADDRESS 81H

A8 AD7 AD0 ALE

PC H

UNSPECIFIED

PC H PC L
80H

PORT ADDRESS 80H

AD7 AD0

OPCODE

P.A.81H

DATA TO O/P PORT

PC L

OPCODE

P.A.80H

I/P PORT DATA

ALE IO / M IO / M RD RD MEMR MEMR WR

IOR

IOW

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6. IO Data Transfer Techniques

8 July 2013

INPUT Interfacing Using I/O mapped I/O

I/O Device Selection (Steps)

1) Decode the address to generate unique signal corresponding to the device address on the bus. 2) When device address & control signal (IOR or IOW) both are low, generate device select signal. 3) Use device select signal to activate the interfacing device (I/O Port)
Step 1

5V

S0

D0

Tri state buffer

D A T A B U S

S7
A0

Step 2 A B C G1 G2 G3 A7

OE

D7

A1 A2 A3

A4 A5 A6

7 4 L S 1 3 8 Y0

IO / M

IOR
RD Step 3

Check weather S1 is pressed Or not.

INPUT Interfacing Using I/O mapped I/O

5V

OUTPUT Interfacing Using I/O mapped I/O

5V 74LS373 D0

S0

D0

Tri state buffer

D A T A
IO / M

D7

S7
A0

OE
A B C G1 G2 G3 A7

D7

B U S

LE

OE 74LS373 OCTAL LATCH

A1 A2 A4 A5 A6 A3

7 4 L S 1 3 8 Y0

IO / M

A0 A1 A2 A3 A4 A5 A6

IOW
A B C G1 G2

IOR
RD

Check weather S1 is pressed Or not. IN 80H ANI 02H JZ NEXT

A7 G3

7 4 L S 1 3 8

WR

Y1

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6. IO Data Transfer Techniques

8 July 2013

I/O Interfacing using I/O mapped I/O OUTPUT Interfacing Using I/O mapped I/O
Address of the output port :A7 A6 A5 A4 A3 A2 A1 A0 D0 Tri state buffer
RD

5V S0 D0

IOR
IO / M

D7 OE D7 S7 5V

To glow the LEDs L1, L2, L6, the accumulator contents are :WR

1
PROGRAM:MVI OUT

1
A0

IOW

D0

OCTAL LATCH

A1 A2

A , B9 H 81 H

A4 A5 A6

A3

A B C G1 G2

A7

G3

7 4 L Y0 S 1 3 8 Y1

D7

LE

OE

I/O Interfacing using memory mapped I/O

RD IO / M WR

5V S0

Comparison between Memory mapped I/O & I/O mapped I/O Memory mapped I/O I/O mapped I/O
1] I/O devices are treated as I/O and memory as memory. address.

D0 MEMR Tri state buffer D7 MEMW

A0

D0

1] I/O devices & memory are treated as memory.

D7 S7 5V

OE

A1 A2 A3 A4 A5 A6 A8 A9 A10 A11 A12 A13 A14 A15

A B C G1

A7

G3 G2

7 4 L Y0 S 1 3 8 Y1

2] Address is 16 bit i.e. A0-A15 are 2] Address is 8-bit.thus A0-A7 or A8-A15 used to generate device address lines are used to generate device address. 3] MEMR & MEMW control signals 3] IOR and IOW control signals are used are used to control I/O read, write to control I/O read, write operations. operations. 4] Instructions available are LDA addr., STA addr., LDAX Rp, STAX Rp, MOV R,M, CMP M etc. 4] Instructions available are IN and OUT.

D0

OCTAL LATCH

D7

LE

OE

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6. IO Data Transfer Techniques

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Comparison between Memory mapped I/O & I/O mapped I/O Memory mapped I/O
5] Data transfer is between any register and I/O devices. 6] Max. No. of I/O devices are 65,536.

University Questions (Electronics)

May-2013
1) Explain different I/O mapping techniques. Give suitable example. (10 Marks)

I/O mapped I/O

5] Data transfer is between accumulator and I/O devices. 6] Max. No. of I/O devices are 256.

Dec-2012
2) Differentiate between I/O mapped I/O and memory mapped I/O. (10 Marks)

7] Execution speed using LDA addr. 7] Execution speed is 10 T-states. is 13 T-states & 7-states for MOV M, R. 8] Decoding 16-bit address may require more hardware. 8] Decoding 8-bit address may require less hardware.

May-2012
3) Write a short note on Memory mapped I/O and I/O mapped I/O. (05 Marks)

9] Arithmetic & logical operations are 9] Arithmetic & logical operations possible on direct data . are not possible on direct data.

University Questions (EXTC)

Nov-2011
1) Explain I/O mapped I/O and memory mapped I/O. (05 Marks)

Nov-2012
2) What is the difference between memory mapped I/O and I/O mapped I/O. (05 Marks)

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