Chemical Processing for Microelectronics

CHEE 1131

Introduction
1. Moores Law - a predictor of transistor packing density in Silicon integrated circuits. 2. Building semiconductor devices.

The Incredible Shrinking Transistor

1947 1997 2007

1 cm

60 nm
FUTURE?

Moores Law
Moores Law has been the economic driving force behind the semiconductor industry for the past ~40 years. It will continue to be a driving force in the future, but for how long?

The number of transistors in an integrated circuit (e.g., Intel micro-processors) continues to increase as the size of each transistor shrinks. Check out Intels website.

Scaling Enabler of Moores Law*

95 500 350 250 180 130 97 99 01 04 07 10 13 16

ITRS Lithography Half-Pitch (DRAM)

90 65 45 32 22
95 97 99 01

Feature Size [nm]

ITRS Gate Length

04 07 10 13

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* For Speed, Low-Cost, Low-Power, etc.

Year of Production

*cf. Robert Doering, Texas Instruments

Moores Law

Compaq Portable (1980s)

My first portable computer! IBM compatible Approx 30 lbs 128 KB; Two 5.25"

My current laptop Approx 3 lbs 4 GB memory; 150 GB hard drive

What Are Semiconductor Devices?

Solid-state electronic components based on semiconducting materials. Usually inorganic. Discrete (single) devices
Diodes Transistors light-emitting diodes (LED) lasers

Integrated devices (many devices on the same substrate)

silicon integrated circuit (SIC) consists of millions of transistors, capacitors, resistors. gallium arsenide IC optoelectronic circuits (lasers, detectors, modulation circuitry all on same chip)

Semiconductor Manufacturing
1. 2. 3. 4. 5. 6. 7. 8. Grow large (many kilogram) crystals Slice them up into wafers (i.e. substrates) and polish them Deposit layers on the polished substrate Define patterns on top of the layers by photolithography (also called optical lithography, projection lithography) Transfer the pattern to the film and sometimes the wafer by plasma etching. Repeat steps 3-5 many times (20+) Slice the wafer into devices (IC, laser, etc.) Package the devices (put it in a case, attach wires, etc.)

Integrated Devices

Environment
UH Nanofab (class 10/100 clean room).
Class Particle Size: 10 100 1000 Lithography Bay Particles per Cubic Foot 0.1m 350 NA NA 0.2m 75 750 NA Plasma Etching
Reference: http://nanofab.uh.edu

0.3m 3 30 300

0.5m 1 10 100 Wet Chemistry

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Unit Operations
Many unit operations in semiconductor fabrication Today overview of the following steps:
Silicon growth Ion implantation (silicon doping) Optical lithography Plasma Etching

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c-Silicon
Silicon is used in many types of semiconductor devices (FETs, etc.). Usually single crystal is needed. Usually silicon is doped to increase the density of charge carriers (electrons, holes) at room temperature. Intrinsic and doped Si. Doped Si is n-type, 1021/m3.

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Silicon Growth
1. Purification of silica sand to produce 98% pure silicon: Reduce with carbon (coke, wood chips).

SiC ( s ) + SiO2 ( s ) Si ( s ) + SiO ( g ) + CO ( g )

Metallurgical grade silicon (MGS)

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Silicon Growth
2. Convert MGS to trichlorosilane: Pulverize Si, react with HCl in fluidized bed:

Si ( s ) + 3HCl ( g ) SiHCl3 ( g ) + H 2 ( g )
31.8C boiling pt

Main impurities in reactant are Fe, B, P. So impurities in product are High bp (315, 76, 160C) Low bp (12.5 C)

* Purify trichlorosilane with distillation

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Silicon Growth
3. Convert back to solid silicon by decomposition of silane:

SiHCl3 ( g ) + H 2 ( g ) Si ( s ) + 3HCl ( g )
Electronic Grade Si (EGS) Polycrystalline! (known as Polysilicon) Purity of 99.9999999%

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Process Flow Diagram

http://www.greenrhinoenergy.com/solar/technologies/pv_manufacturing.php
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Silicon Growth
4. Convert polysilicon to c-Si with czochralski (CZ) crystal growth.
Fill silica crucible (SiO2) with undoped EGS Add dopant: Pieces of doped of silicon (for low doping concentrations); Elemental dopants (high doping concentrations). Heat crucible in vacuum to 1420 C to melt poly Si. Add single-crystal Si seed of known crystal orientation. This directs the growth of Si into a single crystal solid.

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Silicon Growth
4. Convert polysilicon to c-Si with Czochralski (CZ) crystal growth.
After seeding, quickly draw a thin neck. This suppresses defects due to large temperature gradient between melt and solid. After neck forms, lower the pulling rate. Lower pulling rates give larger crystal diameters. Crystal length depends on yield strength of silicon neck, crucible size.

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Silicon Growth
Common challenges:
Contamination.
Silica crucible is slightly dissolved, generates oxygen. CZ-Si has around 10 ppma oxygen (parts per million atoms) Silica crucible has impurities like B, Na, Al. These can be incorporated into the CZ-Si. Silica crucible is not very strong. Reinforced by graphite cup. Reaction between crucible and cup generates CO, this leads to carbon contamination in CZ-Si (1016/cm3).

Time and energy consumption ($$$$$).

For 200 mm wafers, pulling time is 30 h. Heating and cooling time takes another 30 h. Slow, high temperature, batch process.

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Ion Implantation
More common approach for building junctions (doping silicon). Used since the 1980s. Ionized impurity atoms are accelerated through an electrostatic field, strike the surface of the wafer. Typical energies of 5-200 keV. Dose controls implant concentration (measure the ion current). Electrostatic field controls penetration depth (junction depth).

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Ion Implantation
Advantages: Low temp, good control and reproducibility, flexible. Can use photoresist as implant mask. Disadvantages: Throughput, capital cost ($2MM each), and damage to the semiconductor lattice.

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Ion Implantation

1. 2. 3. 4. 5.

Ion Source Mass Spectrometer High-Voltage Accelerator (Up to 5 MeV) Scanning System Target Chamber

Includes Faraday cup for dose measurement

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Optical Lithography
Lithography: Lithos (stone), graphos (writing) Critical step to pattern microscale or nanoscale devices. Replicate a master pattern.

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Optical Lithography
Print a pattern in a sacrificial polymer film called a ``resist Radiation source: Ultraviolet light
Spin-cast resist, Bake to remove residual solvent.

These steps are collectively called lithography

Might need another bake step

``solubility switching is the basis for patterning

http://pluggedin.kodak.com/ 26

Optical Lithography
Pattern transfer (to build a device).

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Optical Lithography
Initial template is called a mask. Typical mask is fused silica with chromium patterns. Quartz = UV transparent, Chrome = opaque.

http://www.phonon.com
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Optical Lithography
Different ways to transfer the mask pattern:
1. 2. 3. Contact printing (press mask onto the resist-coated wafer). 1960s. Damage to the mask was a problem. Proximity printing (mask near the wafer). No damage to mask, but lots of blur. Projection lithography (image projected with lenses). 1970s. No damage, minimal blur. Stepper design. Systems have evolved to meet the demands of Moores Law.

Projection lithography is the current industry standard.

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Optical Lithography

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Optical Lithography
Light sources:
Hg lamp (80s to early 90s):
Decrease (historically) Increase (recent) g-line: 436 nm h-line: 405 nm i-line: 365 nm

Excimer lasers (90s to Now):

Krypton fluoride: 248 nm Argon fluoride: 193 nm Future?

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Lithography
Light sources:
157 nm was next. However, the industry could not develop appropriate ``glass for optics and masks. In general, when you move to shorter wavelengths you encounter problems with transparency.

Next-generation light sources:

Extreme ultraviolet: 13.5 nm. Reflection optics. Electrons: 0.62 . Usually mask-less. Ions: 0.12 . Usually mask-less. Hard X-rays: < 4 nm. Masks and optics OK. Hard to develop resists.

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Projection Lithography
Resolution limit = Rmin = k1 */NA
= wavelength of light source; k1 = process parameter; NA = numerical aperture of your optics.

For academic lithography:

= g, h, and i-line. Rmin 1- 2 m. NA < 1.

For industrial lithography:

= 193 nm. Rmin 20-40 nm. NA 0.9-1.3.

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Tricks to Enhance Resolution

1. New optics 2. New light sources 3. New technologies

These are techniques used in industrial manufacturing, not academic facilities.

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New Optics
193 nm light. Optics immersed in water (n=1.33). Similar to optical microscopes! Single exposure resolves 40 nm (half-pitch). (k1 0.3) Double exposure hits 32 nm.

Source: IBM
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New Light Source

=13.5 nm. Soft X-Rays. Called EUV. NA 0.25-0.45. Reflective optics and masks Vacuum operation Single exposure, so might be simpler than multiple patterning. Very expensive tools (ca. $80 MM)

Decrease (historically)

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EUV Lithography: Reflective Mask

13.5 nm

Absorber/buffer

40-50 alternating layers of silicon and molybdenum, Period /2. Low thermal expansion substrate.
http://www.photomask.com/products/euv-masks

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Academic Instrumentation

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Lithography
Contact aligner (academic facility). Broadband light (436, 405, 365 nm). Resolution limit of approximately 1-2 m. microscope mask timer hv substrate joystick

What you need: Photomask, resist and developer.

Reference: http://nanofab.uh.edu

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Contact/Proximity Printing
Instrumentation:

Reference: http://www.cleanroom.byu.edu

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Contact/Proximity Lithography
Operation:

Alignment is critical to build a multilayer device.

Wafer must be level, or your image will look terrible. This means your substrate should be free of dust.

Reference: http://www.cleanroom.byu.edu

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Process Flow Diagram for Photolithography

Valid for academic or industrial lithography

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HMDS = hexamethyldisilizane

Depends on resist chemistry.

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Materials Overview
Common positive-tone, negative-tone resist materials for academia and industry.

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Positive-Tone DQN Resist

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Positive-Tone DQN Resist

Diazo compounds are of the general structure:

R=N =N

Solvent removed by baking after spin-on Matrix : PAC = 1:1 Expose to UV light (g, h, i-line). Matrix is not changed, but PAC is:

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Positive-Tone DQN Resist

R=

Developer

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Positive-Tone DQN Resist

Developer is a basic solution (such as TMAH dissolved in water, or KOH dissolved in water). Carboxylic acid dissolves, but un-exposed DQ does not. Typically, you post-bake the resist to drive off volatile compounds and make the resist better for plasma etching. The DQN chemistry is very popular for academic lithography. For example, S1813 by MicroChem.

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Chemically-Amplified Resists
Industry standard. Invented at IBM by Willson, Ito, and Frechet. Can be positive or negative tone. Positive tone is standard in industry.

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Chemically-Amplified Resists
Advantages:
Really fast exposures. (Very sensitive to radiation.) Tons of choices for resin and catalyst, so can be used with many different types of radiation sources.

Disadvantages:
Resolution will ultimately be limited by acid catalyst diffusion. Sensitivity and resolution are inversely proportional:

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Plasma Etching
Critical pattern transfer unit operation.

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Plasma Etching
Important classifications: Isotropic vs. anisotropic

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Plasma Basics
A partially ionized gas. Equal number of positive charges (e.g. positive ions) and negative charges (e.g. electrons, negative ions).

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Plasma Overview
Types of processes:
(produces radicals)

Ion milling: Uses A+ (noble gas ions like Ar+) to physically sputter material. Ion etching: Radicals and ions react with sample. Volatile products.

* Means an excited state with energy much higher than ground state

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Plasma Reactor
1. Two parallel plate electrodes attached to power supply (DC or RF, DC in cartoon below). 2. Gas initially acts as an insulator. 3. Connect high-voltage source to start the plasma. Electric field in the reactor exceeds the breakdown field of the gas. High voltage arc will flash between the two electrodes, create a large number of ions and free electrons. 4. Electrons are accelerated toward the anode (fast), ions move to cathode (slow). 5. Ions strike the sample at the cathode, sputters and/or etches material. Volatile products.
Cathode Anode

+ +
electron Ion

Gas breakdown by avalanche ionization

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Plasma Etching at UH Nanofab

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Nano Cougar

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