FOUR BIT PROCESSOR DESIGN This document consist the design specification of individual blocks along with processor

specifications. 1. XOR GATE Write a behavioral description without using XOR construct. (Two single bit inputs and one single bit output) 2. 4-BIT FULL ADDER: Write a structural description of a 4-bit full adder and verify using a good testbench. You should use XOR gate step-1. The adder takes two 4-bit numbers & Cin as inputs & gives one 4-bit number Sum & Cout as outputs. 3. 4-BIT ALU This has three selection bits: S2, S1 and S0 and hence support 8 operations. It uses the adder of step 2. The functionality is as described in the table. The ALU takes the three selection bits, two 4-bit numbers and Cin for the adder as inputs and outputs a 4-bit number f and cout. S2 0 0 0 0 0 0 0 0 1 1 1 1 S1 0 0 0 0 1 1 1 1 0 0 1 1 S0 0 0 1 1 0 0 1 1 0 1 0 1 Cin 0 1 0 1 0 1 0 1 X X X X Operation F=A F = A +1 F =A+B F=A+B+1 F=A+(NOTB) F=A+(NOTB)+1 F=A-1 F=A F=A|b F=A^B F=A&B F=~A; Description Transfer A (Maintain B=0000) Increment A (Maintain B=0000) Add B to A Add B to A with carry Subtract with borrow Subtract Decrement A (Maintain B = 1111) Transfer A (Maintain B = 1111) OR XOR AND Compliment

Note: In ALU modeling, arithmetic and transfer operations are performed using 4bit Fulladder.

4. 4-BIT REGISTERED ALU Register the output signals f and cout from the ALU of step3. The output should be synchronized to rising edge of clock. The active low asynchronous reset signal controls the initialization of these output signals.

5. 16X4 RAM MODEL The RAM is of 16 location depth and 4-bit wide. The input/output ports are addr (4 Bit Vector) datain (4 Bit Vector) csn (1 Bit): Chip Select, it is 0 when memory is in use rwn (1 Bit): 1 Read Memory : 0 - Write Memory Clk_In Dataout (4-Bit Vector) Whenever Dataout is not used i.e., when memory is in write mode or if chip select is high, the Dataout is set to XXXX.

6. INSTRUCTION DECODER

The module is a state-machine which takes input compromising of a 3-bit opcode and two 4-bit operands. When asynchronous reset (reset_n=0) reset the decoder unit goes to init state. With the positive edge of every subsequent clock the unit cycles between Fetch Fetches data from the location specified by the first operand. Execute Execute the Instruction using ALU after setting all control lines depending on instruction. Load Store the data back into the location specified by first operand.

7. FOUR BIT PROCESSOR It is a structural modeling in which ALU, Instruction Decoder, RAM are instantiated. The block diagram of the Processor is given below. It has inputs consisting of 3-Bit opcode, and two 4-bit operands (Pop1a & Pop1b) along with clock, reset, carry-in and gives output of 5Bits (1-Bit Pcout+ 4-Bit Presult).

Note: 1) The operand (Opr1) is the address and the operand (Opr2) is immediate. 2) For any given operation three steps are performed, i) Data is read from the memory using first operand (Opr1). ii) Read Data along with other inputs is provided to registered ALU for specific operation. iii) Obtained result is written back to the memory specified by the first operand.