Design Considerations for HighSpeed, Low-Power CMOS A/D Converters Introduction: Technology and Architecture Considerations Design of Low-Power

er Pipeline A/D Converters Comparison with Alternative Approaches Possible Future Trends and Barriers

AACD-1994, PRG SLIDE 1

Role of Analog Interfaces in VLSI Electronic Systems

Transmission Media Physical sensors and Actuators

VLSI Digital System

Imagers and Displays

Storage media

Audio I/O

AACD-1994, PRG SLIDE 2

High vs. Low Integration level in A/D Interface Systems

Low-Integration Interface

High-Integration Interface

AACD-1994, PRG SLIDE 3

Key Problems in ADC Implementations Must be compatible with high-integration solutions,

quasi-digital technology

Drive to lower supplies complicates all aspects of

design

ADC Performance can be optimized for system

application

Drive toward digital solutions tends to increase ADC

performance requirements
AACD-1994, PRG SLIDE 4

Example Applications for High-Speed CMOS ADCs

Wireless LAN Data Channel (1-50MS/s, 6-10b) Magnetic Storage Read Channel(50-200MS/s,6-8b) ADSL data channel (3-10MS/sec, 12-16b) Digital Multi-standard TV Baseband ADC(20MS/sec, 8-10b) Digital Video Camera ADC(20MS/sec, 8-12b) CATV Decoder Modem ADC(10-20MS/s,8-10b)A HDTV, various apps, (50-75MS/s, 10b) Digital-IF for Multi-standard Broadcast TV rcvr(100200Mb/sec, 8-12b)

AACD-1994, PRG SLIDE 5

Qualitative Comparison of ADC Techniques

Flash, Pipeline
14 12 Bits of Resol ution 10 8 6 4 2

t=1

Succs. Approx t-n

2nd order Sigma-delta 1-bit

t=2(0.4n+1)

Serial

t=2(n)

10

100

1000

10000

Clock Cycles per output sample

Key point: For Video Rates, only candidates are ash, multistep, and pipeline
AACD-1994, PRG SLIDE 6

Where does Power go in a High Speed ADC?

Precision comparators Resistor string Op amps, etc.

Key Aspects of Architecture Selection:

Minimum Number of precision comparators No R-string Low power op amp

=>Promising Approach: Power-Optimized Pipeline
AACD-1994, PRG SLIDE 7

Parallel A/D Converter

High Speed- 10MS/sec->500MS/sec Complex- requires 2N Comparators, High Power Used mainly for very high-speed signal acquisition
AACD-1994, PRG SLIDE 8

Two-step Flash ADCs

input + S/H ADC DAC ADC Fine result

Coarse result Advantages:

Much less hardware than ash

Disadvantages:

No gain in path- requires precision comparators Requires at least three full clocks Usually requires R-string Exponential hardware growth with resolution
AACD-1994, PRG SLIDE 9

Quantized Feedforward ADCs

Output Register
k bits
Input Input S/H Stage

k bits

k bits

...

Stage i

...

Stage Ns

vo vin
k-bit k-bit

S/H

vo

00

01

10

11

vin
Disadvantage:

ADC

DAC

Advantages:

Same throughput as ash Much less hardware than ash

Requires fast
interstage processing

AACD-1994, PRG SLIDE 10

Design Considerations for HighSpeed, Low-Power CMOS A/D Converters Introduction: Technology and Architecture Considerations Design of Low-Power Pipeline A/D Converters Comparison with Alternative Approaches Possible Future Trends and Barriers

AACD-1994, PRG SLIDE 11

Design of Low-Power Pipeline ADCs Some Basic Pipeline Concepts Low-Power Interstage Gain Blocks Dynamic Comparator Implementation Bootstrapped Clock Driver Design Capacitor Size Optimization Experimental Results

AACD-1994, PRG SLIDE 12

Pipelined ADC Stage-Typical CMOS Implementation

v+ in vin
Comps k bits
0 0 0 1 1 1 1

CS +100

CI

v+ o vo

-+
vDAC
0 0 0 1 0 0 0 0

vDAC

CS

CI

Decode Logic

Analog Mux DAC

Bias

Reference Level Generator

Clocks
Ref: C. Conroy, VLSI92

AACD-1994, PRG SLIDE 13

Typical Implementation: Capacitive DAC

VREF CS1 CS2 CS3 ... ... + ADC CP CI

VIN

VOUT

Code
ADC usually R-string ash or Cap-based ash.
AACD-1994, PRG SLIDE 14

Power Minimization in SwitchedCapacitor Gain Blocks

First consider simplest ampliers:

Folded Cascode Cs

Cf Cl

Unfolded Cascode (Telescopic)

AACD-1994, PRG SLIDE 15

Key Issue: What is the fastest attainable settling?

Simplest possible op amp: Cf Cs Cl Cs Cl Cp Cf+Cgd=Cft

Cgs

Cl+Cp =CLt
This is a single-time-constant circuit! C gs C = Ft 1 2f t C 1 + C Lt Ft

1 g m

(C

+ C

gs

1 + 1 + C

Ft
+ C

Lt C

Fixed Vgs-Vt
s = 1 + C 2f 1 t gs C
1 + 1 + C

C gs

Ft
+ C

Lt C

Ft

Device Width and Drain Current

AACD-1994, PRG SLIDE 16

Max Attainable Speed, Contd

What is the best achievable speed as a functon of technology and charge gain?

1 2f t

C 1 + C

Lt Ft

m in

m in

1 2f t

1 + (A

Where Aq = Charge Gain of circuit

Assumptions: 1. Square law applies 2. No slewing 3. Vgs-Vt = 0.5V 4. Neglects all second order device effects. 5. Aq = 1, Cl=Cf

m in

0.5ns 0.2ns 0.1ns 0.8u1.0u 1.5u 3u

AACD-1994, PRG SLIDE 17

What is the Minimum Obtainable Power?

=

1 g m

(C

+ C

gs

1 + 1 + C

C gs

Ft
+ C

Lt C

Ft

Minimize: Result:

= g s (o p t )

C C F

+ CL

2 2f T

(1 +

C C

L F

) = 2

m in

opt

8V

dd

1 ( 1 + A ) 2 C + q S 2

C C F

L2 + CL 2
C L

AACD-1994, PRG SLIDE 18

Observations:

Optimum Cgs is equal to Cequiv Power is very sensitive to charge gain- use low gain/ stage in pipelines Power drops rapidly with technology line width Analysis says pwr goes as square of speed, channel
length, but actually it is more like linear because of Slew Rate, Velocity Saturation.
Leff, Microns 0.8 0.8 0.8 0.8 Desired Time Const. 400ps 400ps 400ps 400ps kT/C noise for 1/6 lsb, Vswing=1V 8bits, 600uVRMS 10bits, 150uVRMS 12bits, 37uVRMS 14bits, 9uVRMS Cs 10fF 160fF 2.5pF 40pF 5fF 80fF 1.25pF 20pF Cf 5fF 80fF 1.25pF 20pF Cl Power, Vdd=3V 72uW 1.1mW 18mW 200mW

AACD-1994, PRG SLIDE 19

More Practical Amplier Congurations

Design Issues with FC, Telescopic:

Poor voltage gain-settling time trade-off Poor voltage swing-settling time trade-off Barely usable at 3V, not usable at 1.5V
Alternative Approaches:

Add broadband input stage to telescopic Two-stage Miller compensated w/one stage cascoded Multi-stage Nested Miller amplier

AACD-1994, PRG SLIDE 20

Telescopic Amplier with Gain Boost Stage

Gain-Boost Amplier Vdd = 3.3V Bias1 Bias2 sw1 C1 sw2 Bias 4 C2

Bias1 C3 Vout+

Vdd = 3.3V Vdd = 3.3V

Bias1 C4 Vout-

Bias3 Vin+ VinBias4

Bias3

ts = 17ns(0.1%) Cs = 0.39pF Cf = 0.39pF Cl = 1.8pF Pd = 4.1mW Vdd=3.3V Av>60dB Swing = +/1Volt P-P

AACD-1994, PRG SLIDE 21

Dynamic Comparators in Pipeline ADCs

Conventional Comparator Design:

Vin

Latch

dout

Broadband, Low-offset preamp

Clk

Key Goal:

Get rid of preamp with its power dissipation, use

dynamic latch as comparator

Key Question:

How much comparator offset can be tolerated?

AACD-1994, PRG SLIDE 22

Gain and Offset Errors in Pipelines

Vin Offset Error Gain Error S/H Offset Error + Gain Error S/H + Offset Error Gain Error S/H

n1bit ADC

n1bit DAC

n2bit ADC

n2bit DAC

n3bit ADC n3 bits

n1 bits Error: Input Gain Other Gains Offsets

n2 bits Effect on Linearity: None Reduced by 1st stg gain None

AACD-1994, PRG SLIDE 23

Effect of ADC Nonlinearity Errors

2-bit example:
Case 1: Ideal ADC, DAC Residual 00 Vr 4 Vr Residual -Vr Input referred nonlinearity error + 2 bit ADC 2 bit DAC Case 2: Nonideal ADC, Ideal DAC Residual 00 Vr 01 10 11 Vin Vr -Vr 2 bits Negative Decision Level Error Positive Decision Level Error 01 10 11 Vin

Vin

+ S/H

Key Point: Can remove ADC Errors by Increasing ADC range in next stg

AACD-1994, PRG SLIDE 24

Digital Correction in Pipelines

Vin

0.5 Stage 1 Stage 2

n2 bit reg n1 bit reg n1 bit reg

Correction Logic

n1+n2-1 bits out

Reduce Gain to Increase Conversion Range Correction Logic is Simple Comparators: Need additional, but they are much simpler

Final Result: DAC Linearity and amplier gain errors ultimately limit linearity

AACD-1994, PRG SLIDE 25

Important Case: 1.5 bit/Stage with Digital Correction

vout
+1 Key Point: Tolerates comparator offset on the order of 1/4 full scale!

00

01

10

0 -1

vin
1 2

1 4

1 4

1 2

+1

2-bit 222 = 2 comps G = 221 = 2

-1

q q

refs: C. Conroy, VLSI92, Jusuf ICCAD90, Lee VLSI93, Jespers ESSCIRC91

AACD-1994, PRG SLIDE 26

Incorporation of ADC Reference Level Function in Comparator

latch / reset

Vdd VoutVout+

VrefM1

VinVin+ M2 M3 M4

Vref+

AACD-1994, PRG SLIDE 27

Dynamic Comparator Implementation

latch/reset Vdd VoutVout+ Voutlatch/reset Vdd Vout+

Vin+ VinVrefw2 w1 w1 Vref+ w2

R1

R2

If w1 = M x w2, Vdecision = Vref / M Well dened built-in Vdecision based on ratio Simple design for low input cap. No DC power!
AACD-1994, PRG SLIDE 28

Low Voltage Switched-Capacitor Gain Blocks

Switch
Vin

Cs

DAC
STAGE i

Vref Vin -Vref

C C

B+1 bits

- op + amp B (2 - 1) x C B+1 bits ash ADC Interstage Amplier

Vout

AACD-1994, PRG SLIDE 29

Low-Voltage Options for MOS Transmission Gates

Conductance vs. Voltage * (Vthn=|Vthp| = 0.8V)
Gon

Vin

GND Vdd

GND -Vthp

Vdd -Vthn

Vdd=5V

GND Gon = gdsn+gdsp GND

Vdd=3.3V

Gap!
Vdd=1.5V

*Integrated A/D&D/A Converter, OCATE, July 1991 Low Power ADC by Vlado Valencic

AACD-1994, PRG SLIDE 30

Low-Voltage Transmission Gates, contd

Possible solutions Dual Vth process (0Vth Native dev) Low Vth Process Global charge pump Local charge pump Good (+) / Bad (-)

+ standard design approach - need process mod + Needed for digital anyway - Big cost in power due to limited swing to rail - possible cross-talk to sensitive nodes - difcult to predict CL + no cross-talk (can isolate sensitive nodes) + easy to predict CL

AACD-1994, PRG SLIDE 31

High-Voltage Clock Generator

Vdd = 3.3 V C1 C2 CL 0
Vsub_hi

Vhi = ~5V

3.3 0

Vhi

C2

+ C L + C parasitic

C2

2Vdd

Only NMOS switch needed Less parasitic cap.

AACD-1994, PRG SLIDE 32

Optimum Scaling of Pipeline Stages for Power Dissipation

N bit ADC, B bits/stage ex) N=10, B=1
10bit 9bit 8bit

Without Scaling
STAGE 4

Vin

STAGE 1

STAGE 2

STAGE 3

10bit

9bit 8bit

With Scaling
STAGE 3 STAGE 4

Vin

STAGE 1

STAGE 2

AACD-1994, PRG SLIDE 33

Optimization result:
Power

Unscaled

Noise Limited

Speed Limited (Due to parasitic capacitance)

Scaled!
1 2 N-1 N Stage

Approx. 40 - 50% reduction in static power consumption! Minimum performance degradation Requires auto-calibration to correct cap mismatches for front stages
AACD-1994, PRG SLIDE 34

Experimental Prototype 1.2m 2-poly, 1-metal CMOS Technology 3.2x3.3mm active area

AACD-1994, PRG SLIDE 35

Experimentally Observed Power vs. Sampling Rate Master bias current adjusted for each sample rate
Power(mW) 30 20 15 10

5 3 1 2 5
AACD-1994, PRG SLIDE 36

Fs (MS/s) 10 20

Integral and Differential Nonlinearity

(a)Measured DNL, 3.3V, 25C, Code Density (b)Measured INL, 3.3V, 25C, Code Density
(LSB) 1.0 0.5 0.0 -0.5 -1.0 0 (LSB) 1.0 0.5 0.0 -0.5 -1.0 0 code (b) 1000 code (a) 1000

AACD-1994, PRG SLIDE 37

SNDR versus Input Level

3.3V Supply, 25C
SNDR (dB) 60 55 50 45 40 35 30 25 20 -40 -30 -20 -10 Input level (dB) 0

Ideal 10 bit 10MHz Input 100kHz Input

AACD-1994, PRG SLIDE 38

Measurement Results
ADC Performance: 3.3V @ 25C
Technology Resolution Conversion Rate Active Area Differential Input Range Input Capacitance Power Dissipation DNL/INL SNDR 1.2-m CMOS 10 b 20 MS/s 3.2 x 3.3 mm2 +/- 1 V 1 pF (single-ended) 35 mW* at 20MS/s (2.8 mW* at 1MS/s) 0.5 / 0.6 LSB 59.1 dB (Fin=100 kHz) 55.0 dB (Fin= 10 MHz)

*: Output pad driver power not included

AACD-1994, PRG SLIDE 39

Power/fs vs. Technology

Power/fs (mW/MS/s) 100
10bit [88] [90] [92] [91] [92] [94] [94]

10

[93] Matsushita,ISSCC93

0.1

10bit ADC
[Year]

This Work

3m

2m 1.5m

1m

1/L(m) 0.8m

AACD-1994, PRG SLIDE 40

Summary of High Speed ADC Performance

Author Type rate bit s 8 tech S/ H ? N PSV Pwr Area FM1 FM2

1. Sekino,Sony,ISSCC82 2. Tsukada,Hitach i, ISSCC85 3. Dingwall, RCA,ISSCC85 4. Peetz, HP,ISSCC86 5.Lewis,UCB,I SSCC86 6. V.D.Grift,Phil, ISSCC87 7. Yoshi,Sony,ISSCC87 8. Akazaw,NTT,ISSCC87 9. Tsutomoto,NTT,ISSCC 88 10. V.D.Plaasche,Ph,ISSC C88

2step

30M

4Gbip

5V

0.7

35K

7.5

2.74

FL

25M

2uCMOS

5V

0.3

33K

16

13.6

2step

5M

2uCMOS

5V

0.15

6K

3.3

5.6

FL

250M

7Gbip

12

48K

36

0.77

Pipe

5M

3uCMOS

10

0.18

10K

7.2

23.0

Fold

50M

7.5Gbip

0.3

10K

6.6

5.63

FL

350M

10Gbip

1.5

22K

35

5.97

FL

400M

18Gbip

2.7

65K

22

2.08

FL

2G

26Gbip

18K

76

9.73

Fold

100M

12Gbip

0.8

17K

8.3

2.65

AACD-1994, PRG SLIDE 41

ADC Performance, Contd

11. Matsuura,Hit a,ISSCC88 12. Song,Univ Ill,ISSCC88 13. Shimitzu,ISSCC88 14. Kerth, Xtal, CICC88 15. Masayuki,NTT,ISS CC89 16. Chin, Nat,ISSCC89 17. Fukishima,Sony,ISSC C89 18. Robertson, AD,ISSCC90 19. Song, Univ Ill,ISSCC90 20. Zojer,Seimens,ISSCC90 2step 20M 8 2u Y 5 0.2 11K 13 16.4

Pipe

1M

12

1.5CMOS

0.4

7.8K

0.4

4.0

2step

20M

10 b 12 b 8b

4.5Gbip

0.9

40K

4.4

5.06

2step

1M

3uCMOS

10

0.7

150K

1.4

8.0

2st

40M

1uCMOS

0.6

20K

8.0

3.41

2st

1.5M

10 b 8b

2uCMOS

0.15

15K

1.0

6.82

2st

40M?

1.4CMOS

0.1

8.1K

22.2

56.8?

Pipe

20M

10 b 10 b 10 b

BICMOS

1.0

85K

10.0

10.2

2step

15M

1uCMOS

0.250

4K

3.0

12.28

2step

75M

7Gbip

23K

10.7

5.476

AACD-1994, PRG SLIDE 42

ADC Performance, Contd

21. Mats.,Mistub, ISSCC90 22. Lin, UCB,VLSI90 23. Lewis,ATT,CICC91 24. Gendai, Sony,ISSCC91 25. Matsuzawa, Mats.,ISSCC91 26. ValBerg,Phil,ISSCC92 27. Vorenkamp,Phil,ISSCC 92 28. Corcoran,HP,ISSCC92 29. Rezavi,Stan, ISSCC92 30. Karanicolas,MIT,ISSCC 93 2st 30M 10 b 13 b 10 b 8b 7GBCMOS Y 10 0.75 40K 4.3 5.87

Pipe

2.5M

3uCMOS

5V

0.1

40K

3.6

144(12b ) 13.6

Pipe

20M

1uCMOS

5V

0.3

12K

4.0

FL

500M

10Gbip

5V

3.1

35K

50

4.1

FL

1G

6b

13Gbip

5V

2.8

40K

75

6.8

fold

600M

8b

5V

0.9

7K

50(est)

14.2

Pipe

50M

10 b

3Gbip

5V

0.75

18K

16

21.8

Pipe

20M

12 b 12 b

7Gbip

10V

3.5

26K

3.5

2step

5M

1uCMOS

5V

0.2

16K

0.8

16.2

Pipe

1M

15 b

4G,2.4uBiCM OS

10

1.8

100K

025

4.4

AACD-1994, PRG SLIDE 43

ADC Performance, Contd:

31. Kusumoto,Ma ts,ISSCC93 32. Sone, NEC,ISSCC93 33. Colleran, UCLA,ISSCC9 3 34. Conroy, VLSI 92 35. Tada, ISSCC93 Pipe 20M 10 b 10 b 10 b 0.8uCMOS Y 5 0.030 10K 2 68.3

Pipe

100M

0.8uBiCMOS

5V

0.95

32K

5-10?

10.7

Pipe

100M

12Gbip

0.8

30K

10.2

Parallel pipe 2-step

85M

8b

1.2uCMOS

0.8

35K

18

5.7

30M

10 b

0.8uCMOS

3.3

0.030+

20K

3.5

90

FM1 is ratio of sampling rate to equivalent technology ft multiplied by 103 FM2 is a power gure of merit normalized to technology ft. It is given by
FM2 = 2 B
(S R )

Pf

P= power dissipation B= number of bits SR=sample rate

AACD-1994, PRG SLIDE 44

100

35

This work 22

31

FM2 30.0
11 2
26

5 23
33 32

27

FM2 =

(S R )

Pf

19 18
33

29

10.0

9
25

14 12
28

34

3.0

15 8 1 10

24

7 6 3

16 20 13 21

1.0

Flash 2-step Folding Pipeline

0.30 6 7 8 9 10 Resolution, bits

11

12

13

Comparison of Power Figure of Merit, Recently Published Flash, 2-step, and Pipeline ADCs
AACD-1994, PRG SLIDE 45

Effective ft vs. Channel Length Silicon MOSFET

10 9 8 7 Approximate 6 Value of NMOS 5 Device ft, Ghz 4
(Assumes bias point of Vgs-VT = 0.5V)

QbicI NMOS(RGM 1994 data)

3 2 1 0.8u 5u 3u 2u 1.5u 1.2u 1u Drawn Channel Length 0.6u

AACD-1994, PRG SLIDE 46

Design Considerations for HighSpeed, Low-Power CMOS A/D Converters Introduction: Technology and Architecture Considerations Design of Low-Power Pipeline A/D Converters Comparison with Alternative Approaches Possible Future Trends and Barriers

AACD-1994, PRG SLIDE 47

Comparison of Pwr in Pipelines, Sigma-Delta Converters Typical Sigma-Delta Front End:

Vin+ VdacVdac+ VinTo second and later stages

In-band kT/C: 2 v n

f pb f 2 s

kT C s

Conclusion: For each 2x increase in OSR,

Cs can be 2x smaller Sample rate is 2x higher Power remains constant for constant in-band noise
One-bit increase in SNR costs 4X in cap value, power
AACD-1994, PRG SLIDE 48

Comparison of FM3 for Sigma Delta, Pipelines

Modul ator Samp. Rate 3.25M Output Resoluti on 14b

Author

Type

Out SR 200K

Techn

PSV

Mod. Pwr 40mW

FM3

1. Dedic, ISSCC94 2. Alexander, ISSCC94 3. Ritoneime, ISSCC94 4. Ray, pc 5. Mats., ISSCC94 6. Tcho

6th ord. 4th ord. 4th ord. 4th ord. 2nd ord. pipe

1.2uC MOS 1uBiC MOS 1.2uB iCMO S 1uCM OS 0.5uC MOS 1.2uC MOS
=

5V

7.8e-16

200mW/ MS/sec

12M

192K

14b(lim by xtalk) 16b

5V

150m W(est) 100m W 25mW 1.5mW 35mW

350e-16

2.5M

44K

5V

5.5e-16

2.3mW/ kS/sec 43mW/ MS/sec 3.9mW/ MS/sec 1.7mW/ MS/sec

18M 6M 20M

584K 380K 20M

13b 9b 10b

5V 1V 3V

6.6e-16 39e-16 15e-16

FM 3

P f 2 s 2B

AACD-1994, PRG SLIDE 49

Typical Power Performance Levels, Recently Published ADCs

Power, mW/MS/sec
3

1000 100
4 1

10 1

5 6

10

12

14

16

Effective Resolution, bits

AACD-1994, PRG SLIDE 50

Design Considerations for HighSpeed, Low-Power CMOS A/D Converters Introduction: Technology and Architecture Considerations Design of Low-Power Pipeline A/D Converters Comparison with Alternative Approaches Possible Future Trends and Barriers

AACD-1994, PRG SLIDE 51

Key Issues in High-Speed ADCs Going Forward

Where do we get another major power increment?

Class B op amps? Charge-domain operation?

How do we get to 1.5 volts at reasonable power?

Nested Miller op amps? More coarse/ne sampling?

How do we solve the Digital supply noise problem?

More effective on-board sub-regulation? Better CAD tools for simulation? Process/package enhancements?
How do we push sample rates to 200-300 Mhz in CMOS?

More parallelism plus self-cal? Better analysis of MOS sample/hold?

AACD-1994, PRG SLIDE 52

Projecting Integration levels in A/D Interface Systems

High-Integration Interface, 1994

Low-Integration Interface, 1984

Super-integrated subsystem, 2004 0.15 micron technology 1.5-2.5V Vdd, >108 xistors/chip Analog content<5%

Key Issue: Does Analog stay on board?

AACD-1994, PRG SLIDE 53