Increased demand for faster, smaller, low-power chips continues to drive the geometry shrink as one of the ways

to manage the low-power, higher performance goals in smaller form factor. 40nm chips are state-of-the-art, 32nm/28nm designs are right around the corner, and companies are already planning for 20nm ows, methodologies, and products. While these advanced process nodes promise tremendous advantages in power, performance, and design capacity, it also raises tough design challenges. These challenges include increased timing and power variability, complex layout rules, and incredibly large designs with massive amounts of IP. A major new challenge at 20nm is the requirement for extra masks (double patterning) to make existing lithography work at this advanced process node. Escalating data volume and denser, more complex chips are testing the limits of traditional routing architectures. Even the slightest perturbations in the design ow can cause dramatic swings in design integrity. Design teams face a predictability crisis riddled with silicon failures, performance degradation, and prolonged design schedules. And new process and design innovations, such as high-k metal gate, SOI, and 3D packaging, are intensifying the pressures of adoption and rapid deployment. We have assembled these FAQs to provide our customers with information on common concerns that linger around 20nm, and help them understand what tool capabilities and ows will be needed to enable predictable success at this node. For detailed perspectives on 20nm, please refer to Cadence white papers that have been published. Q1. What are the key advantages of moving to 20nm, and where are we seeing the most interest? A. There are three primary reasons why we are seeing more system and semiconductor companies consider 20nm: performance, power, and area (PPA) in terms of how much power and area you can save, and the amount of transistors/IP you can put on the chip. Within our customer base, we are seeing a lot of interest in the wireless space, which includes smartphones, tablets, and consumer devices. In this market you have to support different standards, the device has to be really fast, it has to have Internet access, and all this has to be done at lower power so you dont drain the battery. Were also seeing interest in 20nm in other segments like computing and graphics processors.

Q2. Overall, what are the primary design challenges at 20nm? A. There are three kinds of challenges. 1. Silicon manufacturability and managing variations a. How do you maximize yield and manufacturability at 20nm? As you go to 20nm there is an explosion in the different rules you have to deal withthere are about 400 advanced layout rules for the metal layers. Additionally, double patterning comes into the picture. b. Timing and power variations are dramatic at 20nm. Here the design might work, but not at the level of performance or power you intend. Metal pitches have gone from 100nm to 80nm and 64nm, and there is increased coupling between the wires. There are also more parasitics in device modeling

because of the increased interconnect. You have more layout-dependent effects, where the proximity of cells near each other leads to variations in both timing and power. 2. Giga-scale design productivity a. EDA tools must handle the design size and complexity that comes along with 20nm. That requires an ability to handle exponentially increasing IP and an entire SoC. Designers also need to do power management on entire SoCs and do verication signoff in a reasonable period of time. 3. Concurrent performance, power, and area optimization a. The major objective behind the shrinking process node is to achieve the required performance and power savings in the minimal area possible. However, it gets harder and harder to get the most optimized tradeoff between these three aspects. The integrated approach to synthesis, implementation, and signoff becomes critical to ensure design convergence and predictable success at 20nm.

Concurrent PPA Optimization

GigaHertz and Clocks Low Power High-Density IP Reuse - 3D-IC TSV

Giga-Scale Design and Productivity

Abstractions to Handle Complexity Automation/ Multi-CPU to Accelerate Closure Mixed-Signal Pervasive

Silicon Manufacturability and Variation

Complex Design Rules >400 DRC Double Patterning (DPT) Variations LayoutDependent Effects (LDE) Accuracy and Pessimism Removal Indesign Signoff

Q3. Do you really need double-patterning technology (DPT) at 20nm? Can I do without DPT? A. We see different schools of thoughts now in the industry mostly everybody moving to 20nm will need to use it, because conventional lithography is not cutting it any more, but there are few who say grey scale would do to have minimal impact on the design process. Here are the pros and cons regarding each approach: With DPT: Layout features are completely disappearing because of lithography distortion, and its not treatable because of the optical resolution limit. Double patterning gives a new lease on life of the existing [lithography] technology. Without DPT: Some users build margins to account for DPT effects, but that dees the very purpose of moving to 20nm, which is area. So although it might be simpler from a design perspective to build margins and carry on the normal way of designing at 20nm, this approach has overhead of area as well as iterations at the back end when manufacturing cant close on the performance and power the customer is shooting for.

Q4. What design challenges come with double patterning? A. To relieve designers from dealing with additional DPT considerations, we are building some capabilities right into the tools. But here are some things you should know about: The rst thing that double patterning impacts is cell and library generation. You need to make sure silicon IP is compliant with double-patterning layout rules. It is also critical to account for double patterning during placement. Cadence has a unique technology that does automatic colorized placement, and the end benet is a less congested design. With less congestion it is much easier to meet timing and power requirements.

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 And, the biggest impact is in routing. The double patterning has to be integrated inside the routing solutionit cannot be an afterthought where you nish the routing and then run decomposition. It has to be done correct-byconstruction and thats our approach to it. We carry double-patterning intent forward from cell and IP generation to double-pattern aware routing, and nally to signoff physical verication. This provides faster convergence because intent is carried forward throughout the ow. A second benet is better quality of results.

Q5. What kinds of transistor counts can be expected at 20nm, what should I watch out for, and how can EDA tools help? A. 20nm is expected to provide 8 to 12 billion transistors, so thats a huge increase in the size of designs, and its done with a 2x density shrink and 50% better performance. There are several considerations: To handle these large designs, it is a must to down-size the scale such that you retain important information to make the right decisions throughout the design process. This requires a unique abstraction technique. Cadence has been working on something called GigaFlex models, which allow you to abstract out large design macros or blocks from a physical and timing point of view at different levels (depending on the design process youre using). GigaFlex technology helps reduce the netlist to somewhere from 80% to 90% (depending on the design style) and helps accelerate the implementation design closure up to 5x. The clock network gets really complex at 40nm and 28nm. At 20nm, many more clocks are introduced. People are gating clocks, there are power shutoffs, and there are many modes and corners. A traditional clock design methodology will just not cut ityou need a new architecture that has been designed from scratch. In the traditional clock design methodology, clocks are treated as an afterthought. At 20nm, you need clock design that is concurrent with the rest of the logic and physical design. You need to manage useful skew. Having acquired and integrated Azuro clock-concurrent optimization (CCOpt) technology within our digital solution, customers get a much better end result in performance, power, and area. Q6. Variability is already a problem at 40nm and 28nm. What is new and different at 20nm? A. One aspect that gets worse involves layout-dependent effects (LDE). At 20nm, cells are much closer to each other and the proximity effect of different kinds of cells and interconnects has a worse effect on both timing and power. LDE due to lithography and stress need to be characterized up front, and whats needed is context-driven placement and optimization. The Cadence custom and digital implementation system determines how different cells are going to interact and how one layout conguration affects timing and power compared to another. It takes care of those effects during schematic and place-and-route itself, choosing the right neighbors to get better performance andpower.

Q7. What is the new routing layer at 20nm? A. At 28nm and above, the manufacturing ow consists of two parts: front-end-of-the-line (FEOL) and back-end-of-theline (BEOL). The FEOL involves the formation of the transistors and logic, while BEOL handles the vias, interconnects, and other structures. At 20nm, foundries are now talking about a third layer of interconnect. That layerMOLwill become another challenge in the manufacturing ow. MOL allows very dense local routing below rst metal. To address this new routing layer, the industry will require new methodologies. Cadence has enhanced its routers to support the MOL both in the custom and digital world.
LiPo connects to Poly Metal 1 V0 Li2 Li1 Metal 1 V0 LiPo Poly Li1
Active (+)

MOL
Metal 1 V0 Li2 Li1 Active (+) Metal 1 V0 LiPo Li2 Li1 Active (+) Li2 connects Li1 to LiPo

Li1 connects to Active

Metal 1 V0 Li2

Active (-) Nwell Substrate Substrate

Q8. Whats needed in a 20nm design tool ow? Will a point tool approach work? A. Point tools will not work. At Cadence, we have two goals: mitigate 20nm design risk, and help customers accelerate 20nm designs. Both of these goals require an end-to-end ow. Things like double patterning, clock design, and layout-dependent effects all have to be considered upfront in the design ow, from IP characterization to placement and routing to nal signoff.

Preventanalyzeoptimize is key to success at 20nm. This is how we have architected our 20m offering, which covers both custom and digital design. Prevent issues upfront by integrating layout with the schematic generation process, by integrating signoff within the implementation stage, and by removing dependencies at the very end of the design process to accelerate design closure. Cadence has been collaborating closely with our 20nm ecosystem partners for a long time, and we engage with them very early in the cycle. We even help them dene 20nm technical specications and interfaces. Right now we are working on multiple test-chip tapeouts with our partners to make sure that our modeling, abstraction, and ow will produce the best results. Theres still more 20nm work involved in moving to production, and there will be additional ne-tuning of our tools and methodologies, but we are going through that exercise right now.

Q9. At which stages of digital implementation does double patterning need to be handled correctly? A. DPT needs to be handled correctly by the tool throughout the ow: placement, optimization, clock tree synthesis, routing, and signoff. The Cadence Encounter Digital Implementation (EDI) System handles double-patterning requirements during placement through automatic colorization of standard cell metal shapes, or by honoring color information in standard cells that have been pre-colored. During optimization, DPT-correct placement is honored. During routing and post-route optimization stages, EDI Systems built-in 20nm DRC and DPT engine in NanoRoute Router ensures a routing topology that meets both DRC and DPT requirements. This correct-by- construction approach enables routability of higher utilization designs, leading to a smaller possible die area.

Q10. How are electrical characteristics different at 20nm? A. A major pothole in 20nm is the electrical characteristics of the process. This includes things like transistor threshold voltages, transistor on-current, parasitic resistance and capacitance, wire reliability, electromigration, and more. (Some of the trends are shown below.) This create several design challenges to manage the power/performance goals for 20nm process.

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Q11. How do 20nm manufacturing requirements affect timing and power signoff? A. Mask shifting due to double patterning results in slight capacitive variation between different metal shapes, even within the same MMMC corner. This is captured using a multi-value SPEF approach, supported by Cadence QRC Extraction, Encounter Timing System, and Encounter Power System. In addition, cell characterization requires a more accurate method of modeling in timing libraries, which is also supported in Encounter Timing System and Encounter Power System today. From a power signoff perspective, DC and AC electromigration effects are more severe in 20nm than previous nodes, and require more accurate EM analysis and xing. These are a few examples of how the Encounter signoff solution supports 20nm process technology.

Q12. If Im designing sensitive, matched circuits, how do I minimize variation due to double patterning? A. Double patterning will split a layer on to two masks, which could introduce alignment issues and, hence, parametric variation. We have worked with all foundries to enable the capability to assign sensitive nets to be on the same mask.

Q13. Im designing layout by hand. How will I manage these 400 new layout rules? A. With these many new rules, a correct-by-construction methodology is required. This entails using design rule-driven layout editor that understands these rules and guides the creation of correct layout. It also requires using an in-design verication system to automatically check these DRC and DPT rules dynamically, during design, to dramatically reduce the cycle time.

Q14. Im currently doing Monte Carlo analysis to look at process variability. Can I apply that to LDE? A. Yes. When the layout is ready, the device parameters can be back-annotated into the simulation for Monte Carlo analysis. The key is to quickly generate the layout (i.e. before the entire layout is LVS clean). Techniques such as automated device placement/routing and partial layout extraction are used to quickly create the layout for LDEanalysis.

Q15. Memory continues to grow in signicance for SoCs in terms of both area and power consumption. What can be done to reduce leakage power of memories? A. A major contributor to power is drive voltage, so operating near VMIN is needed. ARM offers multi-Vt periphery options for memories that, combined with multiple sleep states, can be used to manage power.

Q16. ARM is strong in mobile market and IP may be optimized for low power. How will your physical IP and POPs work for networking / enterprise applications? A. Last year ARM announced V8 architecture, which is 64 bit. Networking applications use large memory banks, so the range will increase in compilers. POPs can be used for power optimization or performance optimization, depending on the application.

Q17. What are the overall benets of 20nm process technology? A. 2x gate density Improvement 20% speed improvement at Vdd=0.85V 25% switching power reduction Multiple Vt and Lg options extends performance coverage Q18. Which layer will require double patterning? All of them, or just the metal layers? A. Mainly metal layers.

Q19. Is pre-coloring necessary? A. No. Pre-coloring (i.e. manually assigning layouts to the same mask) offers user exibility to manage mask alignment variation to minimize skew variation on input nets of differential pair, clock networks, and to prevent performance degradation of high-speed nets.

Q20. Will the coloring done by EDA tools be maintained during manufacturing for mask assignments? A. Yes.

Cadence is transforming the global electronics industry through a vision called EDA360. With an application-driven approach to design, our software, hardware, IP, and services help customers realize silicon, SoCs, and complete systems efciently and protably. www.cadence.com
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