Main Levels of Floor planning

Floor planning styles and methodology Global routing Clock distribution Power distribution Packaging and pads

Floor planning is chip-level layout design. When designing a leaf cell, we used transistors and vias as basic components, but in floorplanning uses the adders, registers, and F !s as the building blocks. "he fundamental difference between floorplanning and leaf-cell design is that floorplanning works with components that are much larger than the wires connecting them. "his great si#e mismatch forces us to analy#e the layout differently and to make different trade-offs during design. !any chips are composed from cells of a variety of shapes and si#es, as shown in Figure

We call the layout cells blocks during floorplanning because we use them like building blocks to construct the floorplan. $n bricks-and-mortar style layout, the cells may have radically different si#es and shapes. "he layout program must place the components on the chip by position and orientation, leaving sufficient space between the components for the necessary wires. %locks may be redesigned to change their aspect ratio in order to improve the floorplan. &s we will see, the more comple' traffic pattern of wiring areas

makes routing wires in a bricks-and-mortar layout much harder than in a standard cell layout. Floorplanning is divided into three phases: block placement, global routing, and detailed routing. "hese three phases successively refine the design until the layout is complete. %lock placement, as the name implies, places the blocks on the chip. Floorplanning occurs throughout the design process(

)arly in the design process, a floorplan is designed using estimates of the si#es of the blocks and of the number of wires between those blocks. "he area re*uired for wiring is estimated during floorplanning. "his initial floorplan serves as a budget for the design+if the si#es of components or of wires actually implemented are significantly different from those in the initial floorplan, the floorplan needs to be rethought. ,aving a budget for blocks and wires encourages the designers of those sections to live within their allocated areas. "he design of the initial floorplan defines the interface re*uirements for the blocks. -nce those blocks are designed, the chip layout can be assembled from the blocks. %locks may need to be modified due to errors in estimating the properties of the blocks during floorplanning.

)ven with layout design divided into placement and routing, the design of the complete chip layout is a daunting task. Chip-level wiring design is usually divided into two phases( global routing assigns wires to routing channels between the blocks. detailed routing designs the layouts for the wiring. Placement and global routing divide the routing region into smaller sections that can be designed independently, greatly simplifying the detailed routing of those sections. $nteractive floorplan editors and global placement-and-routing tools are a big help in floorplan design. "he si#e of the floorplan and the disparity in scales between large blocks and individual wires make it difficult to manage a manually-designed floorplan. Floorplanning tools may allow you to enter blocks with pinouts, plot rat/s nests to evaluate routability, define routing channels, and perform global routing. Global layout tools perform detailed block placement, global routing, and detailed routing, making sure that the results of the various switchbo' and channel routing tools are assembled into a complete layout. Global and detailed routing design layouts for signals. We use speciali#ed methods to route power0ground nets and clocks because each has speciali#ed re*uirements. 122 and 1 must be supplied to the logic gates with minimal voltage drop and must be ade*uately wide to carry the re*uired current. Clocks must be distributed throughout the chip to minimi#e skew. pecial care must be taken on both power0ground and clock nets in large chips.

Floorplanning a moderate-si#e chip is necessary but not overwhelming. A few simple rules of thumb help you get to an easy-to-implement, easy-to-change design more *uickly.

2evelop a wiring plan. 3ou should think about how to use layers to make connections as part of planning your wiring. "he hori#ontal metal 4-vertical metal 5 scheme used by channel routers is an e'ample of a wiring plan. ketch the plan to help you think about rational, regular schemes for assigning layers to wires. 6sing different layers for different directions or for different types of nets helps reduce alternatives to a manageable number and make choices clearer. ,andcrafted blocks, such as data paths, may have their own wiring plans. weep small components into larger ones. %lock diagrams often have isolated gates or slightly larger components. While these small components help describe system operation, they create lots of problems during floorplanning( they re*uire e'tra effort for power0ground routing and they disrupt the flow of wires across the chip. Put these small components into an e'isting larger block or create a glue logic block to contain all the miscellaneous elements. 2esign wiring that looks simple. $f your sketch of the block diagram or floorplan looks like a plate of spaghetti, it will be hard to route. !ore importantly, it will be harder to change the design when you need to make logic changes or redesign to reduce delays. !ove blocks, then move pin locations to simplify routing topology. 2esign planar wiring. & set of nets is planar if all the nets can all be routed in the plane without crossing. While most interesting chips don/t have planar wiring, a subset of the wires may be planar. $t may help organi#e your thinking to first design a floorplan on which the most important signals have a planar routing, then add the less-critical signals later. 2raw separate wiring plans for power and clock signals . 3ou may want to include these signals in your floorplan sketch, but they may be hard to distinguish from the ma#e of signals on the chip. & separate chart of power and clock routing will help you convince yourself that your design is good for signals, power, and clock.