Republic of the Philippines Polytechnic University of the Philippines COLLEGE OF ENGINEERING

Sta. Mesa, Manila Tel. No. 716-78-32 to 45

CE VISION The College of Engineering envisions itself to be a center of excellence in engineering education. CE MISSION The College of Engineering is committed to produce competitive engineers who will serve as catalyst for sustainable growth and development in national and international levels.

COURSE SYLLABUS ADVANCED LOGIC CIRCUIT DESIGN Revised AY 2003-2004 nd 2 SEMESTER, AY 2013-2014

I. II.

COURSE CODE: COURSE TITLE:

COEN 3174 ADVANCED LOGIC CIRCUITS DESIGN

CE GOALS 1. Provide Quality education through instruction, advance research and extension services: 2. Produce world -class professionals as potential industry leaders and job providers 3. Develop and improve facilities through the use of adapted technology and indigenous materials and: 4. Maintain, upgrade and improve facilities through the adaptation of engineering techniques. OBJECTIVES 1. Strengthen the CE program consistent with global trends; 2. Develop faculty as competent mentors and quality researchers, through advanced studies and other facets of continuing Professional education; 3. Develop the critical thinking and Communication skills of students, giving emphasis to research and extension services; 4. Equip graduates with appropriate knowledge and technical skills imbued with desirable work attitudes and moral values, through enhanced teaching/learning process by using multimedia facilities on top of traditional methods; 5. Create a conducive teaching and learning atmosphere with emphasis to faculty and students growth and academic freedom; 6. Establish network with educational institutions, Industries, GOs and NGOs, local and international, which could serve as: a. Funding sources and/or partners of researches, b. Sources of new technology, c. Centers for faculty and students exchange programs and on -the-job trainings, and d. Grantees of scholarships/ additional facilities and; 7. Continuously conduct action researches on the Needs of laboratory and other facilities that could Be locally produced or innovated using local Materials and adapted technology Engr. Engr. Noli Sibayan CE Chair Engr. Pedrito Tenerife Jr. COE Chair Engr. Ana Liza Publico ECE Chair Engr. Faustino Rural EE Chair Prof. Joselinda Golpeo IE Chair Engr. Jesus Callanta ME Chair Engr. Marianito Gallego Jr. RnD Coordinator Engr. Carmelita Durias ES Chair Engr. Guillermo Bernabe College Dean

III.

PRE-REQUISITE: COEN 3134 (Logic Circuits and Switching Theory) CREDIT UNITS: 4

IV. VI.

COURSE DESCRIPTION:
Types of Flip-flops; Gate Structures and modes of triggering; formal procedures for the analysis and design of synchronous sequential circuits; sequential digital components, registers and counters; state machine design using the ASM Method. This course on digital design focuses on different methodologies and styles in hardware modeling with emphasis on the use of hardware description languages (HDLs). It covers very high speed integrated circuit hardware description language (VHDL) fundamental language concepts and elements and the different levels of descriptions such as behavioral and structural.

VI. OBJECTIVES: At the end of the course the students are expected to:
1.) To study and learn the formal procedures and analysis and design of synchronous sequential circuits and sequential machines. To understand the operation of sequential digital components and its applications to sequential machine design. To apply the concept of Algorithmic State Machine in the design of multi-input sequential machines. To apply the concept of VHDL in designing and analysis of sequential logic circuits

2.)

3.) 4.)

VII. COURSE OUTLINE: TOPICS I. Classroom Orientation PUP VMGO CE VMGO Classroom Policies II. SYNCHRONOUS SEQUENTIAL CIRCUITS Review of Flip-Flops Types of Triggering mechanisms Sequential Circuits Models State Diagrams and State Table Analysis of clocked sequential logic circuits State Reduction and State Assignments Design of sequential logic circuits - Sequence Detector NO. OF HOURS 2 REFERENCE(S) NO. 1,2,3,4,5

LONG EXAMINATION No. 1 III. COUNTERS and REGISTERS Counters Types of Counters Design of Counters Pre-settable Counters Design Applications on Counters Registers Types of Register Shift Register Design Applications of Shift Registers MIDTERM EXAMINATION IV. Algorithmic State Machine (ASM) ASM Chart Timing Consideration Control Implementation Designing using - D- Flip-flop and a decoder - One Flip-flip per state - Multiplexers Long Exam No. 2 V. Design and Analysis of Sequential Circuits Using VHDL (VERILOG) Overview of Digital Systems Evolution of Digital System Design Methodology History of VHDL Advantages and Disadvantages of VHDL LONG EXAMINATION No. 3

2 12 1,2,3,4,5

V. VHDL using VERILOG Hardware modeling using VERILOG Levels of Modeling in VERILOG VHDL Model Components or Structural elements VHDL Language VHDL Lexical Elements and Syntaxes VHDL Expressions and Operators Control Structures Basic Modeling Concepts Subprogram Packages FINAL EXAMINATION VIII. ACTIVITIES Lecture Group Workshops/ Discussions Hands-on Experiments Design Project Presentation Written Examinations IX. REFERENCES:

Tocci, Ronald, Digital System, 6th edition(2012) Malvino and Brown, Digital Computer Electronics (2011) Drosser, F, The Art of Digital Design: An Introduction to Top-Down Design, 4th edition (2013) Mano, Morris, Digital Design, 6th Edition (2012) Roth, Charles, Fundamentals of Logic Design, 5th Edition, (2013)

X. GRADING SYSTEM Major Exam Ave Long Quiz Ave Assignment/Seatwork Project/Practical Exam Experiment Total 35% 25% 5% 25% 10% 100%

Prepared by:
Engr. Julius S.Cansino

Endorsed by:
Engr. Pedrito M. Tenerife Jr.

Approved by: Guillermo O. Bernabe College Dean

Engr.

Subject Teacher

Dept. Chairperson