Nama : Jeffry Immanuel Putra Npm : 13410739 Thermal Considerations in Pac a!in! "s the po#er consumption of inte!

rated circuits rises$ it %ecomes increasin!ly important to efficiently remo&e the heat !enerated %y the chips' " lar!e num%er of failure mecha( nisms in ICs are accentuated %y increased temperatures' )*amples are lea a!e in re&erse( %iased diodes$ electromi!ration$ and hot(electron trappin!' To pre&ent failure$ the temper( ature of the die must %e ept #ithin certain ran!es' The supported temperature ran!e for commercial de&ices durin! operation e+uals 0, to 70,C' -ilitary parts are more demand( in! and re+uire a temperature ran!e &aryin! from .//, to 10/,C' The coolin! effecti&eness of a pac a!e depends upon the thermal conduction of the pac a!e material$ #hich consists of the pac a!e su%strate and %ody$ the pac a!e composi( tion$ and the effecti&eness of the heat transfer %et#een pac a!e and coolin! medium' 1tandard pac a!in! approaches use still or circulatin! air as the coolin! medium' The transfer efficiency can %e impro&ed %y addin! finned metal heat sin s to the pac a!e' -ore e*pensi&e pac a!in! approaches$ such as those used in mainframes or supercomputers$ force air$ li+uids$ or inert !ases throu!h tiny ducts in the pac a!e to achie&e e&en !reater coolin! efficiencies'

"s an e*ample$ a 40(pin 2IP has a thermal resistance of 33 ,C45 and 0/ ,C45 for natural and forced con&ection of air' This means that a 2IP can dissipate 0 #atts 63 #atts7 of po#er #ith natural 6forced7 air con&ection$ and still eep the temperature difference %et#een the die and the en&ironment %elo# 7/ ,C' 8or comparison$ the thermal resistance of a ceramic P9" ran!es from 1/ , to 30 ,C45' 1ince pac a!in! approaches #ith decreased thermal resistance are prohi%iti&ely e*pensi&e$ eepin! the po#er dissipation of an inte!rated circuit #ithin %ounds is an eco( nomic necessity' The increasin! inte!ration le&els and circuit performance ma e this tas nontri&ial' "n interestin! relationship in this conte*t has %een deri&ed %y Na!ata' It pro&ides a %ound on the inte!ration comple*ity and performance as a func( tion of the thermal parameters 6N94tp7 :; 6<T4=)7 #here N9 is the num%er of !ates on the chip$ tp the propa!ation delay$ >T the ma*imum temperature difference %et#een chip and en&ironment$ ? the thermal resistance %et#een them$ and ) the s#itchin! ener!y of each !ate' )*ample 0'0 Thermal @ounds An Inte!ration

8or >T ; 100 ,C$ ? ; 0'/ ,C45 and ) ; 0'1 pJ$ this results in N94tp B 4 C 10 / 6!ates4nsec7' In other #ords$ the ma*imum num%er of !ates on a chip$ #hen all !ates are operatin! simulta(

neously$ must %e less than 400$000 if the s#itchin! speed of each !ate is 1 nsec' This is e+ui&( alent to a po#er dissipation of 40 5' 8ortunately$ not all !ates are operatin! simultaneously in real systems' The ma*i( mum num%er of !ates can %e su%stantially lar!er$ %ased on the acti&ity in the circuit' 8or instance$ it #as e*perimentally deri&ed that the ratio %et#een the a&era!e s#itchin! period and the propa!ation delay ran!es from 00 to 000 in mini( and lar!e( scale computers' Ne&ertheless$ the e+uation demonstrates that heat dissipation and thermal concerns present an important limitation on circuit inte!ration' 2esi!n approaches for lo# po#er that reduce either ) or the acti&ity factor are rapidly !ainin! importance'

1um%er : "' Chandra asan$ di!ital inte!rated circuits$ a desi!n perspecti&e 60nd edition7