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Lecture 20
no contact!
safety margin to allow for misalignment Design Rules are needed: Interface between designer & process engineer Guidelines for designing masks
Professor N Cheung, U.C. Berkeley
EE143 F2010
Lecture 20
1 2
Registration of one mask to the next (also called alignment and overlay) is a crucial aspect of lithography
Professor N Cheung, U.C. Berkeley
EE143 F2010
Lecture 20
B A B
1 2
B A B
1 2
Lets look again at cross-section A-A to understand the consequence of this misalignment. Note contact mask 2m
EE143 F2010
Lecture 20
B A B
1 2
Al
p-type layer
STEP 7
EE143 F2010
Lecture 20
1 2
Al Al
p-type layer
STEP 7
Thus we need safety margins in layout which take into account the possible tolerances in fabrication. Each process has a set of design rules which specify the safety margins.
Professor N Cheung, U.C. Berkeley
EE143 F2010
Lecture 20
EE143 F2010
Lecture 20
EE143 F2010
Lecture 20
l l
l
n+ SiO2
Al n+ SiO2
p-sub
Professor N Cheung, U.C. Berkeley
p-sub
8
EE143 F2010
Lecture 20
3l
2l
Line 2
[Rationale]
EE143 F2010
Lecture 20
l l
l
SiO2 Si
Etching problem
10
EE143 F2010
Lecture 20
l
2l 2l
4l
Configuration 1
l
l
2l
Configuration 2
l
11
EE143 F2010
Lecture 20
2l 2l
l
poly
4l 4l
Professor N Cheung, U.C. Berkeley
12
EE143 F2010
Lecture 20
l l
poly
Note: Both metal and poly linewidths will enlarge to accommodate contact hole overlay error l
13
EE143 F2010
Lecture 20
2l
2l
Min spacing = 3 l
2l
3l
14
EE143 F2010
Lecture 20
15
EE143 F2010
Lecture 20
3. Poly-Si Gate
Min gate-overlap of field oxide = 2l
2l
n+
16
EE143 F2010
Lecture 20
2l
2l
17
EE143 F2010
Lecture 20
Comment: Al to poly contact should not be directly on top of gate oxide area Gate oxide Si
Al
Poly gate
Al Poly SiO2
~400OC Al spike
Al Poly SiO2
Si
Professor N Cheung, U.C. Berkeley
Si
18
EE143 F2010
Lecture 20
19
EE143 F2010
Lecture 20
20
EE143 F2010
Lecture 20
Example
Minimum size contact = 2lx2l Minimum thin-oxide-region underlap of contact = l Minimum source/drain contact to gate spacing = 2l Minimum L = 2l Minimum W = 2l Minimum gate overlap of field-oxide region = 2l Minimum metal overlap of contact = l Minimum thin-oxide-region to thin-oxide-region spacing = 3l * Layout area /transistor = 15lx7l = 105 l2
Professor N Cheung, U.C. Berkeley