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Experiment 5

Digital Circuits Cumulative 4-bit Adder

2012-13 Monsoon

Cumulative addition means the addition of a sequence of numbers applied one after another, as you do on a calculator. Thus each step of cumulative addition involves the addition of the new number to the Partial Sum generated by adding the preceding numbers. Clearly, the Partial Sum has to be saved in some storage device in order that it is available to the Adder in the next step when the next number is to be added. Such a storage device is called a egister, having the simple model shown in ig! 5!1"a#. The slashed arrows denote multi!bit "ata #$nput or %utput&. The n!bit "ata $nput is stored #saved& in the egister when a Pulse is applied to the Cloc' $nput. The data stored in the egister appears as the "ata %utput, and remains unaffected by changes in the "ata $nput as long as no Cloc' Pulse is applied. The data stored in the egister is reset to (ero value when a Pulse is applied to the eset $nput. $ 'nput n-bit Adder A 'nput n!bit )umber ig! 5!1 A cumulative n!bit adder can then be visualised as a circuit consisting of an n!bit Adder and an n!bit egister interconnected as shown in ig! 5!1"b#. The egister %utput is initially eset to (ero value by applying a eset Pulse once. The Adder adds the number applied to its A $nput to the egister %utput applied at the $ $nput and the Sum generated by the Adder is applied to the egister $nput. The resulting Partial Sum is stored in the egister by applying a Cloc' Pulse after every new number is fed in. )ote that the Carry %utput generated by the Adder cannot be saved in the egister and hence cumulative addition is possible in this simple circuit only if the Partial Sum does not exceed an n!bit value at any stage. The chips actually to be used for this experiment are the *!bit binary Adder +*,S-. and the *!bit egister C"*/.0. The pin connections of these chips are given in ig! 5!2.
2. S. C% C$ 1nd 2/ A/ S/ 6"" 75 78 7. ". "8 "5 "/

n!bit "ata $nput

n!bit n-bit +egister %utput eset $nput "a#

n-bit +egister Cloc' "b#

%utput

Cloc' $nput

eset

*!bit Adder +*,S-. A. S8 A8 28 6CC S5 25 A5 7/ T9C:

*!bit egister C"*/.0 ;/: </ C; = 1nd

ig! 5!2 The Adder chip has two *!bit inputs A3A2A1A0 and $3$2$1$0 and a *!bit Sum output %3%2%1%0 along with a Carry %utput C&. The Adder chip also has a Carry $nput pin C', which has to be 'ept connected to 1nd throughout this experiment. The egister chip has *!bit input D3D2D1D0( *!bit output )3)2)1)0, Cloc' input C* and eset input +. 2esides these, the chip has * more input pins that have to be connected as follows3 M 4 5, ,-C. 4 5, /0 and *0. left open.

1! "raw the complete circuit diagram of the Cumulative *!bit Adder using the Adder and egister chips as explained above, writing down the pin numbers for every connection. >ou must complete this before coming to the lab to do the experiment. 2! Test the *!bit 2inary Adder +*,S-. by applying A3A2A1A0 and $3$2$1$0 from - $nput Switches, with the Carry $nput C' 4 /, and observing the *!bit Sum %3%2%1%0 and the Carry %utput bit C& on 0 ,?" indicators for several combinations of the inputs 3! =a'e the following connections for the *!bit egister C"*/.0. These connections will remain unchanged throughout the entire experiment. #a& Connect the M and ,-C. inputs to 6"". ,eave /0 and *0. inputs open. #b& Connect C* and + inputs to the normally LOW outputs of the red Push!button Switches at the lower left corner of the ;it. This will enable one to apply Cloc' and eset pulses to the egister whenever required. #c& Connect the egister %utput )3)2)1)0 to * ,?" indicators. 4! Apply a "ata $nput D3D2D1D0 from * $nput Switches, and observe the egister %utput )3)2)1)0 on * ,?" indicators in the following sequence3 #a& the initial value #can be anything&, #b& the value after applying a eset pulse #should become ////&, #c& the value after applying a Cloc' pulse #should become the same as D3D2D1D0&. 5! epeat step * for several values of D3D2D1D0 to complete the testing of the egister. 0! )ow set up the complete circuit of the Cumulative Adder according to your circuit diagram. @se four $nput Switches for applying the A!input to the Adder and display the Adder %utput consisting of the Carry %utput C& and the *!bit Sum %3%2%1%0 on 0 ,?" indicators for displaying the Partial Sum at each step. 1! Apply some A!input from the $nput Switches, and eset the egister. 6erify that the Adder output is now the same as the A!input. 2! Apply a Cloc' pulse and note the egister output as well as the Adder output. 6erify that the former is the same as the Adder output in step +. <ustify the new value of the Adder output. 3! Change the value of the A!input and repeat step -. 10! ;eep repeating step A, 'eeping watch on the C& output of the Adder. emember that further A!inputs will not be added properly after C& becomes 5 at any stage.

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